^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** O.S : Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ** FILE NAME : arcmsr.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** BY : Nick Cheng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** Description: SCSI RAID Device Driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** ARECA RAID Host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** Web site: www.areca.com.tw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** E-mail: support@areca.com.tw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ** GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ** notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ** documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ** 3. The name of the author may not be used to endorse or promote products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ** derived from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct device_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*The limit of outstanding scsi command that firmware can handle*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ARCMSR_MAX_FREECCB_NUM 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ARCMSR_MAX_OUTSTANDING_CMD 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ARCMSR_DEFAULT_OUTSTANDING_CMD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ARCMSR_MIN_OUTSTANDING_CMD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARCMSR_DRIVER_VERSION "v1.50.00.02-20200819"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARCMSR_SCSI_INITIATOR_ID 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ARCMSR_MAX_XFER_SECTORS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ARCMSR_MAX_XFER_SECTORS_B 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ARCMSR_MAX_XFER_SECTORS_C 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ARCMSR_MAX_TARGETID 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ARCMSR_MAX_TARGETLUN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ARCMSR_MAX_CMD_PERLUN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ARCMSR_DEFAULT_CMD_PERLUN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ARCMSR_MIN_CMD_PERLUN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ARCMSR_MAX_QBUFFER 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ARCMSR_DEFAULT_SG_ENTRIES 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ARCMSR_MAX_HBB_POSTQUEUE 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ARCMSR_MAX_ARC1214_POSTQUEUE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ARCMSR_MAX_ARC1214_DONEQUEUE 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ARCMSR_MAX_HBE_DONEQUEUE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ARCMSR_CDB_SG_PAGE_LENGTH 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ARCMST_NUM_MSIX_VECTORS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifndef PCI_DEVICE_ID_ARECA_1880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_ARECA_1880 0x1880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifndef PCI_DEVICE_ID_ARECA_1214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCI_DEVICE_ID_ARECA_1214 0x1214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifndef PCI_DEVICE_ID_ARECA_1203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_ARECA_1203 0x1203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifndef PCI_DEVICE_ID_ARECA_1884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_DEVICE_ID_ARECA_1884 0x1884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCI_DEVICE_ID_ARECA_1886 0x188A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ARCMSR_HOURS (1000 * 60 * 60 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ARCMSR_MINUTES (1000 * 60 * 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) **********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) **********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ARC_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ARC_FAILURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ** split 64bits dma addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ** MESSAGE CONTROL CODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct CMD_MESSAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) uint32_t HeaderLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uint8_t Signature[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) uint32_t Timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint32_t ControlCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint32_t ReturnCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint32_t Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ** IOP Message Transfer Data for user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ARCMSR_API_DATA_BUFLEN 1032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct CMD_MESSAGE_FIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct CMD_MESSAGE cmdmessage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* IOP message transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ARCMSR_MESSAGE_FAIL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* DeviceType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ARECA_SATA_RAID 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* FunctionCode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FUNCTION_READ_RQBUFFER 0x0801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FUNCTION_WRITE_WQBUFFER 0x0802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FUNCTION_CLEAR_RQBUFFER 0x0803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FUNCTION_CLEAR_WQBUFFER 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FUNCTION_RETURN_CODE_3F 0x0806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FUNCTION_SAY_HELLO 0x0807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FUNCTION_SAY_GOODBYE 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FUNCTION_GET_FIRMWARE_STATUS 0x080A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FUNCTION_HARDWARE_RESET 0x080B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* ARECA IO CONTROL CODE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ARCMSR_MESSAGE_READ_RQBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ARCMSR_MESSAGE_WRITE_WQBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ARCMSR_MESSAGE_RETURN_CODE_3F \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ARCMSR_MESSAGE_SAY_HELLO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ARECA_SATA_RAID | FUNCTION_SAY_HELLO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ARCMSR_MESSAGE_SAY_GOODBYE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* ARECA IOCTL ReturnCode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ** structure for holding DMA address data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IS_DMA64 (sizeof(dma_addr_t) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IS_SG64_ADDR 0x01000000 /* bit24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct SG32ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __le32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }__attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct SG64ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __le32 addresshigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }__attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ** Q Buffer of IOP Message Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct QBUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint32_t data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint8_t data[124];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct FIRMWARE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) uint32_t signature; /*0, 00-03*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) uint32_t request_len; /*1, 04-07*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) uint32_t numbers_queue; /*2, 08-11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) uint32_t sdram_size; /*3, 12-15*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) uint32_t ide_channels; /*4, 16-19*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) char vendor[40]; /*5, 20-59*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) char model[8]; /*15, 60-67*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) char firmware_ver[16]; /*17, 68-83*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) char device_map[16]; /*21, 84-99*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) uint8_t cfgSerial[16]; /*26,104-119*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) uint32_t cfgPicStatus; /*30,120-123*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* signature of set and get firmware config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* message code of inbound message register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* doorbell interrupt generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* ccb areca cdb flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* outbound firmware ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* ARC-1680 Bus Reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ARCMSR_ARC1680_BUS_RESET 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* ARC-1880 Bus Reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ** SPEC. for Areca Type B adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* ARECA HBB COMMAND for its FIRMWARE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* window of "instruction flags" from driver to iop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ARCMSR_DRV2IOP_DOORBELL 0x00020400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* window of "instruction flags" from iop to driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ARCMSR_IOP2DRV_DOORBELL 0x00020408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* window of "instruction flags" from iop to driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* window of "instruction flags" from driver to iop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* ARECA FLAG LANGUAGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* ioctl transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* ioctl transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ARCMSR_MESSAGE_START_BGRB 0x00060008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* ioctl transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* ioctl transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* data tunnel buffer between user space program and its firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* user space data to iop 128bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* iop data to user space 128bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* iop message_rwbuffer for message command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ** SPEC. for Areca HBC adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Host Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Host Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ** Set if Outbound Doorbell register bits 30:1 have a non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ** value. This bit clears only when Outbound Doorbell bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ** Clear register clears bits in the Outbound Doorbell register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ** Set whenever the Outbound Post List Producer/Consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ** Register (FIFO) is not empty. It clears when the Outbound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ** Post List FIFO is empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ** This bit indicates a SAS interrupt from a source external to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ** the PCIe core. This bit is not maskable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* DoorBell*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*inbound message 0 ready*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*more than 12 request completed in a time*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*outbound DATA WRITE isr door bell clear*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*outbound DATA READ isr door bell clear*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*outbound message 0 ready*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*outbound message cmd isr door bell clear*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ** SPEC. for Areca Type D adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ARCMSR_ARC1214_CHIP_ID 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ARCMSR_ARC1214_RESET_REQUEST 0x00108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Host Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Host Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* DoorBell*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*inbound message 0 ready*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*outbound DATA WRITE isr door bell clear*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*outbound message 0 ready*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*outbound message cmd isr door bell clear*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ** SPEC. for Areca Type E adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define ARCMSR_SIGNATURE_1884 0x188417D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* ARC-1884 doorbell sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ** SPEC. for Areca Type F adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define ARCMSR_SIGNATURE_1886 0x188617D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) // Doorbell and interrupt definition are same as Type E adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* ARC-1886 doorbell sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) //set host rw buffer physical address at inbound message 0, 1 (low,high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct ARCMSR_CDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uint8_t Bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) uint8_t TargetID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uint8_t LUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uint8_t Function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint8_t CdbLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t sgcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define ARCMSR_CDB_FLAG_BIOS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define ARCMSR_CDB_FLAG_WRITE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define ARCMSR_CDB_FLAG_HEADQ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uint8_t msgPages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint32_t msgContext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint32_t DataLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint8_t Cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint8_t DeviceStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define ARCMSR_DEV_CHECK_CONDITION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ARCMSR_DEV_ABORTED 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define ARCMSR_DEV_INIT_FAIL 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uint8_t SenseData[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct SG32ENTRY sg32entry[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct SG64ENTRY sg64entry[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct MessageUnit_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint32_t resrved0[4]; /*0000 000F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) uint32_t inbound_msgaddr0; /*0010 0013*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) uint32_t inbound_msgaddr1; /*0014 0017*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) uint32_t outbound_msgaddr0; /*0018 001B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uint32_t outbound_msgaddr1; /*001C 001F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint32_t inbound_doorbell; /*0020 0023*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uint32_t inbound_intstatus; /*0024 0027*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uint32_t inbound_intmask; /*0028 002B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uint32_t outbound_doorbell; /*002C 002F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) uint32_t outbound_intstatus; /*0030 0033*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) uint32_t outbound_intmask; /*0034 0037*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) uint32_t reserved1[2]; /*0038 003F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uint32_t inbound_queueport; /*0040 0043*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) uint32_t outbound_queueport; /*0044 0047*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) uint32_t reserved2[2]; /*0048 004F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uint32_t reserved3[492]; /*0050 07FF 492*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) uint32_t reserved4[128]; /*0800 09FF 128*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) uint32_t reserved5[32]; /*0E80 0EFF 32*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) uint32_t reserved6[32]; /*0F80 0FFF 32*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct MessageUnit_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint32_t postq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) uint32_t doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) uint32_t __iomem *drv2iop_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uint32_t __iomem *drv2iop_doorbell_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uint32_t __iomem *iop2drv_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) uint32_t __iomem *iop2drv_doorbell_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) uint32_t __iomem *message_rwbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) uint32_t __iomem *message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) uint32_t __iomem *message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ** LSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct MessageUnit_C{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) uint32_t message_unit_status; /*0000 0003*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) uint32_t slave_error_attribute; /*0004 0007*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint32_t slave_error_address; /*0008 000B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uint32_t posted_outbound_doorbell; /*000C 000F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) uint32_t master_error_attribute; /*0010 0013*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) uint32_t master_error_address_low; /*0014 0017*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uint32_t master_error_address_high; /*0018 001B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) uint32_t hcb_size; /*001C 001F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) uint32_t inbound_doorbell; /*0020 0023*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) uint32_t diagnostic_rw_data; /*0024 0027*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) uint32_t diagnostic_rw_address_low; /*0028 002B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) uint32_t diagnostic_rw_address_high; /*002C 002F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint32_t host_int_status; /*0030 0033*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) uint32_t host_int_mask; /*0034 0037*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) uint32_t dcr_data; /*0038 003B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint32_t dcr_address; /*003C 003F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) uint32_t inbound_queueport; /*0040 0043*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) uint32_t outbound_queueport; /*0044 0047*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uint32_t hcb_pci_address_low; /*0048 004B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint32_t hcb_pci_address_high; /*004C 004F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) uint32_t iop_int_status; /*0050 0053*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uint32_t iop_int_mask; /*0054 0057*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) uint32_t iop_inbound_queue_port; /*0058 005B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) uint32_t iop_outbound_queue_port; /*005C 005F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) uint32_t inbound_free_list_index; /*0060 0063*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uint32_t inbound_post_list_index; /*0064 0067*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) uint32_t outbound_free_list_index; /*0068 006B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) uint32_t outbound_post_list_index; /*006C 006F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) uint32_t inbound_doorbell_clear; /*0070 0073*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) uint32_t i2o_message_unit_control; /*0074 0077*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) uint32_t last_used_message_source_address_low; /*0078 007B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) uint32_t last_used_message_source_address_high; /*007C 007F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) uint32_t message_dest_address_index; /*0090 0093*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) uint32_t utility_A_int_counter_timer; /*0098 009B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) uint32_t outbound_doorbell; /*009C 009F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) uint32_t outbound_doorbell_clear; /*00A0 00A3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) uint32_t message_source_address_index; /*00A4 00A7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) uint32_t message_done_queue_index; /*00A8 00AB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uint32_t reserved0; /*00AC 00AF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uint32_t inbound_msgaddr0; /*00B0 00B3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uint32_t inbound_msgaddr1; /*00B4 00B7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) uint32_t outbound_msgaddr0; /*00B8 00BB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) uint32_t outbound_msgaddr1; /*00BC 00BF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) uint32_t inbound_queueport_low; /*00C0 00C3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) uint32_t inbound_queueport_high; /*00C4 00C7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uint32_t outbound_queueport_low; /*00C8 00CB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uint32_t outbound_queueport_high; /*00CC 00CF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uint32_t message_dest_queue_port_low; /*00E0 00E3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uint32_t message_dest_queue_port_high; /*00E4 00E7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) uint32_t host_diagnostic; /*00F8 00FB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) uint32_t write_sequence; /*00FC 00FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) uint32_t reserved1[34]; /*0100 0187*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) uint32_t reserved2[1950]; /*0188 1FFF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) uint32_t message_wbuffer[32]; /*2000 207F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) uint32_t reserved3[32]; /*2080 20FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) uint32_t message_rbuffer[32]; /*2100 217F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) uint32_t reserved4[32]; /*2180 21FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ** Messaging Unit (MU) of Type D processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct InBound_SRB {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) uint32_t addressLow; /* pointer to SRB block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) uint32_t addressHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uint32_t length; /* in DWORDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) uint32_t reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct OutBound_SRB {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) uint32_t addressLow; /* pointer to SRB block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) uint32_t addressHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct MessageUnit_D {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) volatile struct OutBound_SRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u16 postq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) volatile u16 doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 __iomem *chip_id; /* 0x00004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 __iomem *cpu_mem_config; /* 0x00008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 __iomem *sample_at_reset; /* 0x00100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 __iomem *reset_request; /* 0x00108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 __iomem *host_int_status; /* 0x00200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 __iomem *pcief0_int_enable; /* 0x0020C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 __iomem *inbound_msgaddr0; /* 0x00400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 __iomem *inbound_msgaddr1; /* 0x00404 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 __iomem *outbound_msgaddr0; /* 0x00420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 __iomem *outbound_msgaddr1; /* 0x00424 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 __iomem *inbound_doorbell; /* 0x00460 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 __iomem *outbound_doorbell; /* 0x00480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 __iomem *inboundlist_base_low; /* 0x01000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 __iomem *inboundlist_base_high; /* 0x01004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 __iomem *outboundlist_base_low; /* 0x01060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 __iomem *outboundlist_base_high; /* 0x01064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 __iomem *message_wbuffer; /* 0x2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 __iomem *message_rbuffer; /* 0x2100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ** Messaging Unit (MU) of Type E processor(LSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct MessageUnit_E{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint32_t iobound_doorbell; /*0000 0003*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint32_t write_sequence_3xxx; /*0004 0007*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uint32_t host_diagnostic_3xxx; /*0008 000B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uint32_t posted_outbound_doorbell; /*000C 000F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) uint32_t master_error_attribute; /*0010 0013*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint32_t master_error_address_low; /*0014 0017*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint32_t master_error_address_high; /*0018 001B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uint32_t hcb_size; /*001C 001F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) uint32_t inbound_doorbell; /*0020 0023*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) uint32_t diagnostic_rw_data; /*0024 0027*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) uint32_t diagnostic_rw_address_low; /*0028 002B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) uint32_t diagnostic_rw_address_high; /*002C 002F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) uint32_t host_int_status; /*0030 0033*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uint32_t host_int_mask; /*0034 0037*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) uint32_t dcr_data; /*0038 003B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uint32_t dcr_address; /*003C 003F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) uint32_t inbound_queueport; /*0040 0043*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) uint32_t outbound_queueport; /*0044 0047*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) uint32_t hcb_pci_address_low; /*0048 004B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) uint32_t hcb_pci_address_high; /*004C 004F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) uint32_t iop_int_status; /*0050 0053*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) uint32_t iop_int_mask; /*0054 0057*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uint32_t iop_inbound_queue_port; /*0058 005B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) uint32_t iop_outbound_queue_port; /*005C 005F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uint32_t inbound_free_list_index; /*0060 0063*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uint32_t inbound_post_list_index; /*0064 0067*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint32_t reply_post_producer_index; /*0068 006B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) uint32_t reply_post_consumer_index; /*006C 006F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint32_t inbound_doorbell_clear; /*0070 0073*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) uint32_t i2o_message_unit_control; /*0074 0077*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint32_t last_used_message_source_address_low; /*0078 007B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint32_t last_used_message_source_address_high; /*007C 007F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint32_t message_dest_address_index; /*0090 0093*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) uint32_t utility_A_int_counter_timer; /*0098 009B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) uint32_t outbound_doorbell; /*009C 009F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) uint32_t outbound_doorbell_clear; /*00A0 00A3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) uint32_t message_source_address_index; /*00A4 00A7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) uint32_t message_done_queue_index; /*00A8 00AB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) uint32_t reserved0; /*00AC 00AF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) uint32_t inbound_msgaddr0; /*00B0 00B3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uint32_t inbound_msgaddr1; /*00B4 00B7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uint32_t outbound_msgaddr0; /*00B8 00BB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) uint32_t outbound_msgaddr1; /*00BC 00BF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) uint32_t inbound_queueport_low; /*00C0 00C3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) uint32_t inbound_queueport_high; /*00C4 00C7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uint32_t outbound_queueport_low; /*00C8 00CB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) uint32_t outbound_queueport_high; /*00CC 00CF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) uint32_t message_dest_queue_port_low; /*00E0 00E3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) uint32_t message_dest_queue_port_high; /*00E4 00E7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) uint32_t host_diagnostic; /*00F8 00FB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) uint32_t write_sequence; /*00FC 00FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uint32_t reserved1[34]; /*0100 0187*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) uint32_t reserved2[1950]; /*0188 1FFF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) uint32_t message_wbuffer[32]; /*2000 207F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uint32_t reserved3[32]; /*2080 20FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint32_t message_rbuffer[32]; /*2100 217F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) uint32_t reserved4[32]; /*2180 21FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ** Messaging Unit (MU) of Type F processor(LSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct MessageUnit_F {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uint32_t iobound_doorbell; /*0000 0003*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uint32_t write_sequence_3xxx; /*0004 0007*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uint32_t host_diagnostic_3xxx; /*0008 000B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) uint32_t posted_outbound_doorbell; /*000C 000F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint32_t master_error_attribute; /*0010 0013*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) uint32_t master_error_address_low; /*0014 0017*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) uint32_t master_error_address_high; /*0018 001B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uint32_t hcb_size; /*001C 001F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uint32_t inbound_doorbell; /*0020 0023*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uint32_t diagnostic_rw_data; /*0024 0027*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint32_t diagnostic_rw_address_low; /*0028 002B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) uint32_t diagnostic_rw_address_high; /*002C 002F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) uint32_t host_int_status; /*0030 0033*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) uint32_t host_int_mask; /*0034 0037*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) uint32_t dcr_data; /*0038 003B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint32_t dcr_address; /*003C 003F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) uint32_t inbound_queueport; /*0040 0043*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) uint32_t outbound_queueport; /*0044 0047*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) uint32_t hcb_pci_address_low; /*0048 004B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) uint32_t hcb_pci_address_high; /*004C 004F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) uint32_t iop_int_status; /*0050 0053*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) uint32_t iop_int_mask; /*0054 0057*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) uint32_t iop_inbound_queue_port; /*0058 005B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) uint32_t iop_outbound_queue_port; /*005C 005F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) uint32_t inbound_free_list_index; /*0060 0063*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) uint32_t inbound_post_list_index; /*0064 0067*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) uint32_t reply_post_producer_index; /*0068 006B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uint32_t reply_post_consumer_index; /*006C 006F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uint32_t inbound_doorbell_clear; /*0070 0073*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint32_t i2o_message_unit_control; /*0074 0077*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint32_t last_used_message_source_address_low; /*0078 007B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint32_t last_used_message_source_address_high; /*007C 007F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) uint32_t message_dest_address_index; /*0090 0093*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uint32_t utility_A_int_counter_timer; /*0098 009B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) uint32_t outbound_doorbell; /*009C 009F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) uint32_t outbound_doorbell_clear; /*00A0 00A3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) uint32_t message_source_address_index; /*00A4 00A7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) uint32_t message_done_queue_index; /*00A8 00AB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) uint32_t reserved0; /*00AC 00AF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) uint32_t inbound_msgaddr0; /*00B0 00B3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint32_t inbound_msgaddr1; /*00B4 00B7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uint32_t outbound_msgaddr0; /*00B8 00BB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) uint32_t outbound_msgaddr1; /*00BC 00BF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) uint32_t inbound_queueport_low; /*00C0 00C3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) uint32_t inbound_queueport_high; /*00C4 00C7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) uint32_t outbound_queueport_low; /*00C8 00CB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) uint32_t outbound_queueport_high; /*00CC 00CF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) uint32_t message_dest_queue_port_low; /*00E0 00E3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) uint32_t message_dest_queue_port_high; /*00E4 00E7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) uint32_t host_diagnostic; /*00F8 00FB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) uint32_t write_sequence; /*00FC 00FF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) uint32_t reserved1[46]; /*0100 01B7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) uint32_t reply_post_producer_index1; /*01B8 01BB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) uint32_t reply_post_consumer_index1; /*01BC 01BF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define MESG_RW_BUFFER_SIZE (256 * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) typedef struct deliver_completeQ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) uint16_t cmdFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) uint16_t cmdSMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) uint16_t cmdLMID; // reserved (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) uint16_t cmdFlag2; // reserved (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ** Adapter Control Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct AdapterControlBlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) uint32_t adapter_type; /* adapter A,B..... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 ioqueue_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct pci_dev * pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct Scsi_Host * host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) unsigned long vir2phy_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Offset is used in making arc cdb physical to virtual calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) uint32_t outbound_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uint32_t cdb_phyaddr_hi32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) uint32_t reg_mu_acc_handle0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) uint64_t cdb_phyadd_hipart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) spinlock_t eh_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) spinlock_t ccblist_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) spinlock_t postq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) spinlock_t doneq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spinlock_t rqbuffer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) spinlock_t wqbuffer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct MessageUnit_A __iomem *pmuA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct MessageUnit_B *pmuB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct MessageUnit_C __iomem *pmuC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct MessageUnit_D *pmuD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct MessageUnit_E __iomem *pmuE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct MessageUnit_F __iomem *pmuF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* message unit ATU inbound base address0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) void __iomem *mem_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) void __iomem *mem_base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) //0x000 - COMPORT_IN (Host sent to ROC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uint32_t *message_wbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) //0x100 - COMPORT_OUT (ROC sent to Host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) uint32_t *message_rbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) uint32_t acb_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u16 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) uint8_t adapter_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define ACB_F_SCSISTOPADAPTER 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define ACB_F_MSG_STOP_BGRB 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* stop RAID background rebuild */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define ACB_F_MSG_START_BGRB 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* stop RAID background rebuild */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define ACB_F_IOPDATA_OVERFLOW 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* iop message data rqbuffer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* message clear wqbuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* message clear rqbuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define ACB_F_BUS_RESET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define ACB_F_IOP_INITED 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* iop init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define ACB_F_ABORT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define ACB_F_FIRMWARE_TRAP 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define ACB_F_ADAPTER_REMOVED 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define ACB_F_MSG_GET_CONFIG 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* used for memory free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct list_head ccb_free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* head of free ccb list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) atomic_t ccboutstandingcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*The present outstanding command number that in the IOP that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) waiting for being handled by FW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void * dma_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* dma_coherent used for memory free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dma_addr_t dma_coherent_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* dma_coherent_handle used for memory free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dma_addr_t dma_coherent_handle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) void *dma_coherent2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned int uncache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* data collection buffer for read from 80331 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int32_t rqbuf_getIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* first of read buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int32_t rqbuf_putIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* last of read buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* data collection buffer for write to 80331 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int32_t wqbuf_getIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* first of write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int32_t wqbuf_putIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* last of write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* id0 ..... id15, lun0...lun7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define ARECA_RAID_GONE 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define ARECA_RAID_GOOD 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) uint32_t num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) uint32_t num_aborts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) uint32_t firm_request_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) uint32_t firm_numbers_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) uint32_t firm_sdram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) uint32_t firm_hd_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uint32_t firm_cfg_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) char firm_model[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) char firm_version[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) char device_map[20]; /*21,84-99*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct work_struct arcmsr_do_message_isr_bh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct timer_list eternal_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned short fw_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define FW_NORMAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define FW_BOG 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define FW_DEADLOCK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) uint32_t maxOutstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int vector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uint32_t maxFreeCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct timer_list refresh_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) uint32_t doneq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) uint32_t ccbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) uint32_t in_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) uint32_t out_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) uint32_t completionQ_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pCompletion_Q pCompletionQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) uint32_t completeQ_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };/* HW_DEVICE_EXTENSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ** Command Control Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ** this CCB length must be 32 bytes boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct CommandControlBlock{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct list_head list; /*x32: 8byte, x64: 16byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define CCB_FLAG_READ 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define CCB_FLAG_WRITE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define CCB_FLAG_ERROR 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define CCB_FLAG_FLUSHCACHE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define CCB_FLAG_MASTER_ABORTED 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) uint16_t startdone; /*x32:2byte,x32:2byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define ARCMSR_CCB_DONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define ARCMSR_CCB_START 0x55AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define ARCMSR_CCB_ABORTED 0xAA55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define ARCMSR_CCB_ILLEGAL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) uint32_t smid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #if BITS_PER_LONG == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* ======================512+64 bytes======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) uint32_t reserved[3]; /*12 byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* ======================512+32 bytes======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) uint32_t reserved[8]; /*32 byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* ======================================================= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct ARCMSR_CDB arcmsr_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ** ARECA SCSI sense data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct SENSE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) uint8_t ErrorCode:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define SCSI_SENSE_CURRENT_ERRORS 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define SCSI_SENSE_DEFERRED_ERRORS 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) uint8_t Valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uint8_t SegmentNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) uint8_t SenseKey:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint8_t Reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) uint8_t IncorrectLength:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) uint8_t EndOfMedia:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) uint8_t FileMark:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) uint8_t Information[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) uint8_t AdditionalSenseLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) uint8_t CommandSpecificInformation[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) uint8_t AdditionalSenseCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uint8_t AdditionalSenseCodeQualifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) uint8_t FieldReplaceableUnitCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint8_t SenseKeySpecific[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ** Outbound Interrupt Status Register - OISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define ARCMSR_MU_OUTBOUND_HANDLE_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) |ARCMSR_MU_OUTBOUND_DOORBELL_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) |ARCMSR_MU_OUTBOUND_PCI_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ** Outbound Interrupt Mask Register - OIMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct QBUFFER __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) extern struct device_attribute *arcmsr_host_attrs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags