^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD am53c974 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "esp_scsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRV_MODULE_NAME "am53c974"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_MODULE_VERSION "1.00"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static bool am53c974_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static bool am53c974_fenab = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define esp_dma_log(f, a...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (am53c974_debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) shost_printk(KERN_DEBUG, esp->host, f, ##a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ESP_DMA_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ESP_DMA_STC 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ESP_DMA_SPA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ESP_DMA_WBC 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ESP_DMA_WAC 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ESP_DMA_STATUS 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ESP_DMA_SMDLA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ESP_DMA_WMAC 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ESP_DMA_CMD_IDLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ESP_DMA_CMD_BLAST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ESP_DMA_CMD_ABORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ESP_DMA_CMD_START 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ESP_DMA_CMD_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ESP_DMA_CMD_DIAG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ESP_DMA_CMD_MDL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ESP_DMA_CMD_INTE_P 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ESP_DMA_CMD_INTE_D 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ESP_DMA_CMD_DIR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ESP_DMA_STAT_PWDN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ESP_DMA_STAT_ERROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ESP_DMA_STAT_ABORT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ESP_DMA_STAT_DONE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ESP_DMA_STAT_SCSIINT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ESP_DMA_STAT_BCMPLT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* EEPROM is accessed with 16-bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DC390_EEPROM_READ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DC390_EEPROM_LEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * DC390 EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 8 * 4 bytes of per-device options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * followed by HBA specific options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Per-device options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DC390_EE_MODE1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DC390_EE_SPEED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* HBA-specific options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DC390_EE_ADAPT_SCSI_ID 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DC390_EE_MODE2 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DC390_EE_DELAY 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DC390_EE_TAG_CMD_NUM 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DC390_EE_MODE1_PARITY_CHK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DC390_EE_MODE1_SYNC_NEGO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DC390_EE_MODE1_EN_DISC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DC390_EE_MODE1_SEND_START 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DC390_EE_MODE1_TCQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DC390_EE_MODE2_MORE_2DRV 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DC390_EE_MODE2_GREATER_1G 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DC390_EE_MODE2_RST_SCSI_BUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DC390_EE_MODE2_NO_SEEK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DC390_EE_MODE2_LUN_CHECK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pci_esp_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct esp *esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 dma_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void pci_esp_dma_drain(struct esp *esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return dev_get_drvdata(esp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) iowrite8(val, esp->regs + (reg * 4UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ioread8(esp->regs + (reg * 4UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return iowrite32(val, esp->regs + (reg * 4UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int pci_esp_irq_pending(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pci_esp_priv *pep = pci_esp_get_priv(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (pep->dma_status & (ESP_DMA_STAT_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ESP_DMA_STAT_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ESP_DMA_STAT_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ESP_DMA_STAT_SCSIINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void pci_esp_reset_dma(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Nothing to do ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void pci_esp_dma_drain(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 resid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int lim = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Data-In or Data-Out, nothing to be done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) while (--lim > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (resid <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * When there is a residual BCMPLT will never be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * (obviously). But we still have to issue the BLAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * command, otherwise the data will not being transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * But we'll never know when the BLAST operation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * finished. So check for some time and give up eventually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) lim = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (--lim == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* BLAST residual handling is currently untested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (WARN_ON_ONCE(resid == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct esp_cmd_entry *ent = esp->active_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ent->flags |= ESP_CMD_FLAG_RESIDUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void pci_esp_dma_invalidate(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pci_esp_priv *pep = pci_esp_get_priv(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) esp_dma_log("invalidate DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pep->dma_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int pci_esp_dma_error(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct pci_esp_priv *pep = pci_esp_get_priv(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (pep->dma_status & ESP_DMA_STAT_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (pep->dma_status & ESP_DMA_STAT_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 dma_count, int write, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct pci_esp_priv *pep = pci_esp_get_priv(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BUG_ON(!(cmd & ESP_CMD_DMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pep->dma_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Set DMA engine to IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* DMA write direction logic is inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val |= ESP_DMA_CMD_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (esp->config2 & ESP_CONFIG2_FENAB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_esp_write8(esp, (esp_count >> 16) & 0xff, ESP_TCHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_esp_write32(esp, esp_count, ESP_DMA_STC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pci_esp_write32(esp, addr, ESP_DMA_SPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) esp_dma_log("start dma addr[%x] count[%d:%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) addr, esp_count, dma_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) scsi_esp_cmd(esp, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Send DMA Start command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static u32 pci_esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int dma_limit = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 base, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * If CONFIG2_FENAB is set we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * handle up to 24 bit addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (esp->config2 & ESP_CONFIG2_FENAB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dma_limit = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (dma_len > (1U << dma_limit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dma_len = (1U << dma_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Prevent crossing a 24-bit address boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) base = dma_addr & ((1U << 24) - 1U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) end = base + dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (end > (1U << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) end = (1U <<24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dma_len = end - base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct esp_driver_ops pci_esp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .esp_write8 = pci_esp_write8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .esp_read8 = pci_esp_read8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .irq_pending = pci_esp_irq_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .reset_dma = pci_esp_reset_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .dma_drain = pci_esp_dma_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .dma_invalidate = pci_esp_dma_invalidate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .send_dma_cmd = pci_esp_send_dma_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .dma_error = pci_esp_dma_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .dma_length_limit = pci_esp_dma_length_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Read DC-390 eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 carry_flag = 1, j = 0x80, bval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 0; i < 9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (carry_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pci_write_config_byte(pdev, 0x80, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bval = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bval = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pci_write_config_byte(pdev, 0x80, bval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_write_config_byte(pdev, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) carry_flag = (cmd & j) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) j >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static u16 dc390_eeprom_get_data(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u16 wval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 bval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) wval <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pci_write_config_byte(pdev, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pci_write_config_byte(pdev, 0x80, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pci_read_config_byte(pdev, 0x00, &bval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (bval == 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) wval |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void dc390_read_eeprom(struct pci_dev *pdev, u16 *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 cmd = DC390_EEPROM_READ, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) for (i = 0; i < DC390_EEPROM_LEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pci_write_config_byte(pdev, 0xc0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dc390_eeprom_prepare_read(pdev, cmd++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *ptr++ = dc390_eeprom_get_data(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pci_write_config_byte(pdev, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pci_write_config_byte(pdev, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) udelay(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void dc390_check_eeprom(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct pci_dev *pdev = to_pci_dev(esp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 EEbuf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u16 *ptr = (u16 *)EEbuf, wval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dc390_read_eeprom(pdev, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) wval += *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* no Tekram EEprom found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (wval != 0x1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_printk(KERN_INFO, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "No valid Tekram EEprom found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (EEbuf[DC390_EE_MODE2] & DC390_EE_MODE2_ACTIVE_NEGATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) esp->config4 |= ESP_CONFIG4_RADE | ESP_CONFIG4_RAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int pci_esp_probe_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct scsi_host_template *hostt = &scsi_esp_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct esp *esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct pci_esp_priv *pep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_printk(KERN_INFO, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "failed to set 32bit DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto fail_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) shost = scsi_host_alloc(hostt, sizeof(struct esp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!shost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_printk(KERN_INFO, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "failed to allocate scsi host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto fail_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!pep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_printk(KERN_INFO, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "failed to allocate esp_priv\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto fail_host_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) esp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) esp->host = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) esp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) esp->ops = &pci_esp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * The am53c974 HBA has a design flaw of generating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * spurious DMA completion interrupts when using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * DMA for command submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) esp->flags |= ESP_FLAG_USE_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Enable CONFIG2_FENAB to allow for large DMA transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (am53c974_fenab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) esp->config2 |= ESP_CONFIG2_FENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pep->esp = esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (pci_request_regions(pdev, DRV_MODULE_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_printk(KERN_ERR, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "pci memory selection failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto fail_priv_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!esp->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto fail_release_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) esp->dma_regs = esp->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) esp->command_block = dma_alloc_coherent(&pdev->dev, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &esp->command_block_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!esp->command_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_printk(KERN_ERR, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "failed to allocate command block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto fail_unmap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pci_set_drvdata(pdev, pep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DRV_MODULE_NAME, esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto fail_unmap_command_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) esp->scsi_id = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dc390_check_eeprom(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) shost->this_id = esp->scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) shost->max_id = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) shost->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) shost->io_port = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) shost->n_io_port = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) shost->unique_id = shost->io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) esp->scsi_id_mask = (1 << esp->scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Assume 40MHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) esp->cfreq = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) err = scsi_esp_register(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto fail_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) fail_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) free_irq(pdev->irq, esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fail_unmap_command_block:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dma_free_coherent(&pdev->dev, 16, esp->command_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) esp->command_block_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fail_unmap_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_iounmap(pdev, esp->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fail_release_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fail_priv_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) kfree(pep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) fail_host_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fail_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void pci_esp_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct pci_esp_priv *pep = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct esp *esp = pep->esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) scsi_esp_unregister(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) free_irq(pdev->irq, esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dma_free_coherent(&pdev->dev, 16, esp->command_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) esp->command_block_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pci_iounmap(pdev, esp->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) kfree(pep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) scsi_host_put(esp->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct pci_device_id am53c974_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct pci_driver am53c974_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = DRV_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .id_table = am53c974_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .probe = pci_esp_probe_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .remove = pci_esp_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) module_pci_driver(am53c974_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_DESCRIPTION("AM53C974 SCSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_VERSION(DRV_MODULE_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MODULE_ALIAS("tmscsim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) module_param(am53c974_debug, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_PARM_DESC(am53c974_debug, "Enable debugging");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) module_param(am53c974_fenab, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MODULE_PARM_DESC(am53c974_fenab, "Enable 24-bit DMA transfer sizes");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags