^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Aic94xx SAS/SATA driver hardware interface header file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005 Gilbert Wu <gilbert_wu@adaptec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _AIC94XX_SDS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _AIC94XX_SDS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) FLASH_METHOD_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) FLASH_METHOD_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) FLASH_METHOD_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FLASH_MANUF_ID_AMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FLASH_MANUF_ID_ST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FLASH_MANUF_ID_FUJITSU 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FLASH_MANUF_ID_MACRONIX 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FLASH_MANUF_ID_INTEL 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FLASH_MANUF_ID_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FLASH_DEV_ID_AM29LV008BT 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FLASH_DEV_ID_AM29LV800DT 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FLASH_DEV_ID_STM29W800DT 0xD7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FLASH_DEV_ID_STM29LV640 0xDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FLASH_DEV_ID_STM29008 0xEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FLASH_DEV_ID_MBM29LV800TE 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FLASH_DEV_ID_MBM29DL800TA 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FLASH_DEV_ID_MBM29LV008TA 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FLASH_DEV_ID_AM29LV640MT 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FLASH_DEV_ID_AM29F800B 0xD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FLASH_DEV_ID_MX29LV800BT 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FLASH_DEV_ID_MX29LV008CT 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FLASH_DEV_ID_I28LV00TAT 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FLASH_DEV_ID_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* status bit mask values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FLASH_STATUS_BIT_MASK_DQ6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FLASH_STATUS_BIT_MASK_DQ5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FLASH_STATUS_BIT_MASK_DQ2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* minimum value in micro seconds needed for checking status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FLASH_STATUS_ERASE_DELAY_COUNT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FLASH_STATUS_WRITE_DELAY_COUNT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FLASH_SECTOR_SIZE 0x010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FLASH_SECTOR_SIZE_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FLASH_OK 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FAIL_OPEN_BIOS_FILE 0x000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FAIL_CHECK_PCI_ID 0x000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FAIL_CHECK_SUM 0x000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FAIL_UNKNOWN 0x000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FAIL_VERIFY 0x000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FAIL_RESET_FLASH 0x000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FAIL_FIND_FLASH_ID 0x000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FAIL_ERASE_FLASH 0x000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FAIL_WRITE_FLASH 0x000900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FAIL_FILE_SIZE 0x000a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FAIL_PARAMETERS 0x000b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FAIL_OUT_MEMORY 0x000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FLASH_IN_PROGRESS 0x001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct controller_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 vendor; /* PCI Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 device; /* PCI Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 sub_vendor; /* PCI Subvendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 sub_device; /* PCI Subdevice ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct image_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 ImageId; /* Identifies the image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 ImageOffset; /* Offset the beginning of the file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 ImageLength; /* length of the image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 ImageChecksum; /* Image checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 ImageVersion; /* Version of the image, could be build number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct bios_file_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 signature[32]; /* Signature/Cookie to identify the file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 checksum; /*Entire file checksum with this field zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 antidote; /* Entire file checksum with this field 0xFFFFFFFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct controller_id contrl_id; /*PCI id to identify the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 filelen; /*Length of the entire file*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 chunk_num; /*The chunk/part number for multiple Image files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 total_chunks; /*Total number of chunks/parts in the image file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 num_images; /* Number of images in the file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 build_num; /* Build number of this image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct image_info image_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int asd_verify_flash_seg(struct asd_ha_struct *asd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const void *src, u32 dest_offset, u32 bytes_to_verify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int asd_write_flash_seg(struct asd_ha_struct *asd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const void *src, u32 dest_offset, u32 bytes_to_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int asd_chk_write_status(struct asd_ha_struct *asd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 sector_addr, u8 erase_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int asd_check_flash_type(struct asd_ha_struct *asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int asd_erase_nv_sector(struct asd_ha_struct *asd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 flash_addr, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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