Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Aic94xx SAS/SATA driver hardware interface header file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2005 Adaptec, Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _AIC94XX_HWI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _AIC94XX_HWI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <scsi/libsas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "aic94xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "aic94xx_sas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Define ASD_MAX_PHYS to the maximum phys ever. Currently 8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ASD_MAX_PHYS       8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ASD_PCBA_SN_SIZE   12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct asd_ha_addrspace {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	void __iomem  *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned long  start;       /* pci resource start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned long  len;         /* pci resource len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned long  flags;       /* pci resource flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* addresses internal to the host adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 swa_base; /* mmspace 1 (MBAR1) uses this only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 swb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 swc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct bios_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int    present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8     maj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8     min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32    bld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct unit_element_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u16    num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u16    size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	void   *area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct flash_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32    bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int    present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int    wide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u8     manuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8     dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8     sec_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8     method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32    dir_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct asd_phy_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* From CTRL-A settings, then set to what is appropriate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8     sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u8     max_sas_lrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u8     min_sas_lrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u8     max_sata_lrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8     min_sata_lrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8     flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ASD_CRC_DIS  1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ASD_SATA_SPINUP_HOLD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8     phy_control_0; /* mode 5 reg 0x160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8     phy_control_1; /* mode 5 reg 0x161 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u8     phy_control_2; /* mode 5 reg 0x162 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8     phy_control_3; /* mode 5 reg 0x163 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct asd_dma_tok {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	void *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct hw_profile {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct bios_struct bios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct unit_element_struct ue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct flash_struct flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8     sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	char   pcba_sn[ASD_PCBA_SN_SIZE+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u8     enabled_phys;	  /* mask of enabled phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct asd_phy_desc phy_desc[ASD_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32    max_scbs;	  /* absolute sequencer scb queue size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct asd_dma_tok *scb_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32    max_ddbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct asd_dma_tok *ddb_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	spinlock_t ddb_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	void  *ddb_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int    num_phys;	  /* ENABLEABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int    max_phys;	  /* REPORTED + ENABLEABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned addr_range;	  /* max # of addrs; max # of possible ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned port_name_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned dev_name_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned sata_name_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct asd_ascb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct asd_ha_struct *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct scb *scb;	  /* equals dma_scb->vaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct asd_dma_tok dma_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct asd_dma_tok *sg_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	void (*tasklet_complete)(struct asd_ascb *, struct done_list_struct *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u8     uldd_timer:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* internally generated command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct completion *completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8        tag_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	__be16    tag;		  /* error recovery only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* If this is an Empty SCB, index of first edb in seq->edb_arr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int    edb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* Used by the timer timeout function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int    tc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	void   *uldd_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ASD_DL_SIZE_BITS   0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ASD_DL_SIZE        (1<<(2+ASD_DL_SIZE_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ASD_DEF_DL_TOGGLE  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct asd_seq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	spinlock_t pend_q_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u16    scbpro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int    pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct list_head pend_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int    can_queue;	  /* per adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct asd_dma_tok next_scb; /* next scb to be delivered to CSEQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	spinlock_t tc_index_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	void **tc_index_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	void *tc_index_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int   tc_index_bitmap_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct tasklet_struct dl_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct done_list_struct *dl; /* array of done list entries, equals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct asd_dma_tok *actual_dl; /* actual_dl->vaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int    dl_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int    dl_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int    num_edbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct asd_dma_tok **edb_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int    num_escbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct asd_ascb **escb_arr; /* array of pointers to escbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* This is an internal port structure. These are used to get accurate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * phy_mask for updating DDB 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct asd_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8  sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8  attached_sas_addr[SAS_ADDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* This is the Host Adapter structure.  It describes the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * SAS adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct asd_ha_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct pci_dev   *pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	const char       *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct sas_ha_struct sas_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u8                revision_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int               iospace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	spinlock_t        iolock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct asd_ha_addrspace io_handle[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct hw_profile hw_prof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct asd_phy    phys[ASD_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	spinlock_t        asd_ports_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct asd_port   asd_ports[ASD_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct asd_sas_port   ports[ASD_MAX_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct dma_pool  *scb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct asd_seq_data  seq; /* sequencer related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32    bios_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	const struct firmware *bios_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* ---------- Common macros ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ASD_BUSADDR_LO(__dma_handle) ((u32)(__dma_handle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ASD_BUSADDR_HI(__dma_handle) (((sizeof(dma_addr_t))==8)     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)                                     ? ((u32)((__dma_handle) >> 32)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)                                     : ((u32)0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define dev_to_asd_ha(__dev)  pci_get_drvdata(to_pci_dev(__dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SCB_SITE_VALID(__site_no) (((__site_no) & 0xF0FF) != 0x00FF   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				 && ((__site_no) & 0xF0FF) > 0x001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* For each bit set in __lseq_mask, set __lseq to equal the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * position of the set bit and execute the statement following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * __mc is the temporary mask, used as a mask "counter".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define for_each_sequencer(__lseq_mask, __mc, __lseq)                        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (((__mc) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define for_each_phy(__lseq_mask, __mc, __lseq)                              \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		if (((__mc) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PHY_ENABLED(_HA, _I) ((_HA)->hw_prof.enabled_phys & (1<<(_I)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* ---------- DMA allocs ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline struct asd_dma_tok *asd_dmatok_alloc(gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return kmem_cache_alloc(asd_dma_token_cache, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline void asd_dmatok_free(struct asd_dma_tok *token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	kmem_cache_free(asd_dma_token_cache, token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline struct asd_dma_tok *asd_alloc_coherent(struct asd_ha_struct *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 						     asd_ha, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 						     gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct asd_dma_tok *token = asd_dmatok_alloc(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		token->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		token->vaddr = dma_alloc_coherent(&asd_ha->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 						  token->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 						  &token->dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 						  flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (!token->vaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			asd_dmatok_free(token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			token = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static inline void asd_free_coherent(struct asd_ha_struct *asd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				     struct asd_dma_tok *token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dma_free_coherent(&asd_ha->pcidev->dev, token->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				  token->vaddr, token->dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		asd_dmatok_free(token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline void asd_init_ascb(struct asd_ha_struct *asd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				 struct asd_ascb *ascb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	INIT_LIST_HEAD(&ascb->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ascb->scb = ascb->dma_scb.vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ascb->ha = asd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	timer_setup(&ascb->timer, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ascb->tc_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Must be called with the tc_index_lock held!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void asd_tc_index_release(struct asd_seq_data *seq, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	seq->tc_index_array[index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	clear_bit(index, seq->tc_index_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Must be called with the tc_index_lock held!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static inline int asd_tc_index_get(struct asd_seq_data *seq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	index = find_first_zero_bit(seq->tc_index_bitmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				    seq->tc_index_bitmap_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (index == seq->tc_index_bitmap_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	seq->tc_index_array[index] = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	set_bit(index, seq->tc_index_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Must be called with the tc_index_lock held!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static inline void *asd_tc_index_find(struct asd_seq_data *seq, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return seq->tc_index_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  * asd_ascb_free -- free a single aSCB after is has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * @ascb: pointer to the aSCB of interest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * This frees an aSCB after it has been executed/completed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * the sequencer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline void asd_ascb_free(struct asd_ascb *ascb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (ascb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		struct asd_ha_struct *asd_ha = ascb->ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		BUG_ON(!list_empty(&ascb->list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		spin_lock_irqsave(&ascb->ha->seq.tc_index_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		asd_tc_index_release(&ascb->ha->seq, ascb->tc_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		spin_unlock_irqrestore(&ascb->ha->seq.tc_index_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			      ascb->dma_scb.dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		kmem_cache_free(asd_ascb_cache, ascb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * asd_ascb_list_free -- free a list of ascbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  * @ascb_list: a list of ascbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  * This function will free a list of ascbs allocated by asd_ascb_alloc_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  * It is used when say the scb queueing function returned QUEUE_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  * and we do not need the ascbs any more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline void asd_ascb_free_list(struct asd_ascb *ascb_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	LIST_HEAD(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct list_head *n, *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	__list_add(&list, ascb_list->list.prev, &ascb_list->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	list_for_each_safe(pos, n, &list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		list_del_init(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		asd_ascb_free(list_entry(pos, struct asd_ascb, list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* ---------- Function declarations ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int  asd_init_hw(struct asd_ha_struct *asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) irqreturn_t asd_hw_isr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				     *asd_ha, int *num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 				     gfp_t gfp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int  asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int  asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int  asd_init_post_escbs(struct asd_ha_struct *asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void asd_build_control_phy(struct asd_ascb *ascb, int phy_id, u8 subfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int  asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void asd_ascb_timedout(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int  asd_chip_hardrst(struct asd_ha_struct *asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif