Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Aic94xx SAS/SATA DDB management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2005 Adaptec, Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * $Id: //depot/aic94xx/aic94xx_dev.c#21 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "aic94xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "aic94xx_hwi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "aic94xx_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "aic94xx_sas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define FIND_FREE_DDB(_ha) find_first_zero_bit((_ha)->hw_prof.ddb_bitmap, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 					       (_ha)->hw_prof.max_ddbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SET_DDB(_ddb, _ha) set_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLEAR_DDB(_ddb, _ha) clear_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int asd_get_ddb(struct asd_ha_struct *asd_ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int ddb, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	ddb = FIND_FREE_DDB(asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	if (ddb >= asd_ha->hw_prof.max_ddbs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		ddb = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	SET_DDB(ddb, asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	for (i = 0; i < sizeof(struct asd_ddb_ssp_smp_target_port); i+= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		asd_ddbsite_write_dword(asd_ha, ddb, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	return ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define INIT_CONN_TAG   offsetof(struct asd_ddb_ssp_smp_target_port, init_conn_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DEST_SAS_ADDR   offsetof(struct asd_ddb_ssp_smp_target_port, dest_sas_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SEND_QUEUE_HEAD offsetof(struct asd_ddb_ssp_smp_target_port, send_queue_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DDB_TYPE        offsetof(struct asd_ddb_ssp_smp_target_port, ddb_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CONN_MASK       offsetof(struct asd_ddb_ssp_smp_target_port, conn_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DDB_TARG_FLAGS  offsetof(struct asd_ddb_ssp_smp_target_port, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DDB_TARG_FLAGS2 offsetof(struct asd_ddb_stp_sata_target_port, flags2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define EXEC_QUEUE_TAIL offsetof(struct asd_ddb_ssp_smp_target_port, exec_queue_tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SEND_QUEUE_TAIL offsetof(struct asd_ddb_ssp_smp_target_port, send_queue_tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SISTER_DDB      offsetof(struct asd_ddb_ssp_smp_target_port, sister_ddb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX_CCONN       offsetof(struct asd_ddb_ssp_smp_target_port, max_concurrent_conn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define NUM_CTX         offsetof(struct asd_ddb_ssp_smp_target_port, num_contexts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ATA_CMD_SCBPTR  offsetof(struct asd_ddb_stp_sata_target_port, ata_cmd_scbptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SATA_TAG_ALLOC_MASK offsetof(struct asd_ddb_stp_sata_target_port, sata_tag_alloc_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define NUM_SATA_TAGS   offsetof(struct asd_ddb_stp_sata_target_port, num_sata_tags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SATA_STATUS     offsetof(struct asd_ddb_stp_sata_target_port, sata_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define NCQ_DATA_SCB_PTR offsetof(struct asd_ddb_stp_sata_target_port, ncq_data_scb_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ITNL_TIMEOUT    offsetof(struct asd_ddb_ssp_smp_target_port, itnl_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void asd_free_ddb(struct asd_ha_struct *asd_ha, int ddb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (!ddb || ddb >= 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	asd_ddbsite_write_byte(asd_ha, ddb, DDB_TYPE, DDB_TYPE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	CLEAR_DDB(ddb, asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void asd_set_ddb_type(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int ddb = (int) (unsigned long) dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (dev->dev_type == SAS_SATA_PM_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		asd_ddbsite_write_byte(asd_ha,ddb, DDB_TYPE, DDB_TYPE_PM_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	else if (dev->tproto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		asd_ddbsite_write_byte(asd_ha,ddb, DDB_TYPE, DDB_TYPE_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		asd_ddbsite_write_byte(asd_ha,ddb,DDB_TYPE,DDB_TYPE_INITIATOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int asd_init_sata_tag_ddb(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int ddb, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ddb = asd_get_ddb(asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (ddb < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	for (i = 0; i < sizeof(struct asd_ddb_sata_tag); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		asd_ddbsite_write_word(asd_ha, ddb, i, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	asd_ddbsite_write_word(asd_ha, (int) (unsigned long) dev->lldd_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			       SISTER_DDB, ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) void asd_set_dmamode(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct ata_device *ata_dev = sas_to_ata_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int ddb = (int) (unsigned long) dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 qdepth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (dev->dev_type == SAS_SATA_DEV || dev->dev_type == SAS_SATA_PM_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (ata_id_has_ncq(ata_dev->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			qdepth = ata_id_queue_depth(ata_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		asd_ddbsite_write_dword(asd_ha, ddb, SATA_TAG_ALLOC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 					(1ULL<<qdepth)-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		asd_ddbsite_write_byte(asd_ha, ddb, NUM_SATA_TAGS, qdepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (qdepth > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		if (asd_init_sata_tag_ddb(dev) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			spin_lock_irqsave(dev->sata_dev.ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			ata_dev->flags |= ATA_DFLAG_NCQ_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			spin_unlock_irqrestore(dev->sata_dev.ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int asd_init_sata(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ddb = (int) (unsigned long) dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	asd_ddbsite_write_word(asd_ha, ddb, ATA_CMD_SCBPTR, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (dev->dev_type == SAS_SATA_DEV || dev->dev_type == SAS_SATA_PM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	    dev->dev_type == SAS_SATA_PM_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		struct dev_to_host_fis *fis = (struct dev_to_host_fis *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			dev->frame_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		asd_ddbsite_write_byte(asd_ha, ddb, SATA_STATUS, fis->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	asd_ddbsite_write_word(asd_ha, ddb, NCQ_DATA_SCB_PTR, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int asd_init_target_ddb(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int ddb, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u8 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ddb = asd_get_ddb(asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (ddb < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dev->lldd_dev = (void *) (unsigned long) ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	asd_ddbsite_write_byte(asd_ha, ddb, 0, DDB_TP_CONN_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	asd_ddbsite_write_byte(asd_ha, ddb, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	asd_ddbsite_write_word(asd_ha, ddb, INIT_CONN_TAG, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	for (i = 0; i < SAS_ADDR_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		asd_ddbsite_write_byte(asd_ha, ddb, DEST_SAS_ADDR+i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				       dev->sas_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	asd_ddbsite_write_word(asd_ha, ddb, SEND_QUEUE_HEAD, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	asd_set_ddb_type(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	asd_ddbsite_write_byte(asd_ha, ddb, CONN_MASK, dev->port->phy_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (dev->port->oob_mode != SATA_OOB_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		flags |= OPEN_REQUIRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if ((dev->dev_type == SAS_SATA_DEV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		    (dev->tproto & SAS_PROTOCOL_STP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			struct smp_resp *rps_resp = &dev->sata_dev.rps_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			if (rps_resp->frame_type == SMP_RESPONSE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			    rps_resp->function == SMP_REPORT_PHY_SATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			    rps_resp->result == SMP_RESP_FUNC_ACC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				if (rps_resp->rps.affil_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 					flags |= STP_AFFIL_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				if (rps_resp->rps.affil_supp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					flags |= SUPPORTS_AFFIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			flags |= CONCURRENT_CONN_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			if (!dev->parent && dev_is_expander(dev->dev_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				asd_ddbsite_write_byte(asd_ha, ddb, MAX_CCONN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 						       4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				asd_ddbsite_write_byte(asd_ha, ddb, MAX_CCONN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 						       dev->pathways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			asd_ddbsite_write_byte(asd_ha, ddb, NUM_CTX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (dev->dev_type == SAS_SATA_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		flags |= SATA_MULTIPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	asd_ddbsite_write_byte(asd_ha, ddb, DDB_TARG_FLAGS, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (dev->tproto & SAS_PROTOCOL_STP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		flags |= STP_CL_POL_NO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	asd_ddbsite_write_byte(asd_ha, ddb, DDB_TARG_FLAGS2, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	asd_ddbsite_write_word(asd_ha, ddb, EXEC_QUEUE_TAIL, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	asd_ddbsite_write_word(asd_ha, ddb, SEND_QUEUE_TAIL, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	asd_ddbsite_write_word(asd_ha, ddb, SISTER_DDB, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (dev->dev_type == SAS_SATA_DEV || (dev->tproto & SAS_PROTOCOL_STP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		i = asd_init_sata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			asd_free_ddb(asd_ha, ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (dev->dev_type == SAS_END_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		struct sas_end_device *rdev = rphy_to_end_device(dev->rphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (rdev->I_T_nexus_loss_timeout > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			asd_ddbsite_write_word(asd_ha, ddb, ITNL_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					       min(rdev->I_T_nexus_loss_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 						   (u16)ITNL_TIMEOUT_CONST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			asd_ddbsite_write_word(asd_ha, ddb, ITNL_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 					       (u16)ITNL_TIMEOUT_CONST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int asd_init_sata_pm_table_ddb(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ddb, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ddb = asd_get_ddb(asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ddb < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	for (i = 0; i < 32; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		asd_ddbsite_write_word(asd_ha, ddb, i, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	asd_ddbsite_write_word(asd_ha, (int) (unsigned long) dev->lldd_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			       SISTER_DDB, ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PM_PORT_FLAGS offsetof(struct asd_ddb_sata_pm_port, pm_port_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PARENT_DDB    offsetof(struct asd_ddb_sata_pm_port, parent_ddb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * asd_init_sata_pm_port_ddb -- SATA Port Multiplier Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * @dev: pointer to domain device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * For SATA Port Multiplier Ports we need to allocate one SATA Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * Multiplier Port DDB and depending on whether the target on it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * supports SATA II NCQ, one SATA Tag DDB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int asd_init_sata_pm_port_ddb(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int ddb, i, parent_ddb, pmtable_ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u8  flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ddb = asd_get_ddb(asd_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ddb < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	asd_set_ddb_type(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	flags = (dev->sata_dev.port_no << 4) | PM_PORT_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	asd_ddbsite_write_byte(asd_ha, ddb, PM_PORT_FLAGS, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	asd_ddbsite_write_word(asd_ha, ddb, SISTER_DDB, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	asd_ddbsite_write_word(asd_ha, ddb, ATA_CMD_SCBPTR, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	asd_init_sata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	parent_ddb = (int) (unsigned long) dev->parent->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	asd_ddbsite_write_word(asd_ha, ddb, PARENT_DDB, parent_ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	pmtable_ddb = asd_ddbsite_read_word(asd_ha, parent_ddb, SISTER_DDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	asd_ddbsite_write_word(asd_ha, pmtable_ddb, dev->sata_dev.port_no,ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (asd_ddbsite_read_byte(asd_ha, ddb, NUM_SATA_TAGS) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		i = asd_init_sata_tag_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			asd_free_ddb(asd_ha, ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int asd_init_initiator_ddb(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * asd_init_sata_pm_ddb -- SATA Port Multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * @dev: pointer to domain device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * For STP and direct-attached SATA Port Multipliers we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * one target port DDB entry and one SATA PM table DDB entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int asd_init_sata_pm_ddb(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	res = asd_init_target_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	res = asd_init_sata_pm_table_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		asd_free_ddb(dev->port->ha->lldd_ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			     (int) (unsigned long) dev->lldd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int asd_dev_found(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	spin_lock_irqsave(&asd_ha->hw_prof.ddb_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	switch (dev->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	case SAS_SATA_PM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		res = asd_init_sata_pm_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case SAS_SATA_PM_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		res = asd_init_sata_pm_port_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (dev->tproto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			res = asd_init_target_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			res = asd_init_initiator_ddb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	spin_unlock_irqrestore(&asd_ha->hw_prof.ddb_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void asd_dev_gone(struct domain_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int ddb, sister_ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	spin_lock_irqsave(&asd_ha->hw_prof.ddb_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ddb = (int) (unsigned long) dev->lldd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	sister_ddb = asd_ddbsite_read_word(asd_ha, ddb, SISTER_DDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (sister_ddb != 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		asd_free_ddb(asd_ha, sister_ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	asd_free_ddb(asd_ha, ddb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	dev->lldd_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	spin_unlock_irqrestore(&asd_ha->hw_prof.ddb_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }