^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Product specific probe and attach routines for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 3940, 2940, aic7895, aic7890, aic7880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * aic7870, aic7860 and aic7850 SCSI controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 1994-2001 Justin T. Gibbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2000-2001 Adaptec Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "aic7xxx_osm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "aic7xxx_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "aic7xxx_93cx6.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "aic7xxx_pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline uint64_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) uint64_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) id = subvendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) | (subdevice << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) | ((uint64_t)vendor << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) | ((uint64_t)device << 48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return (id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DEVID_9005_TYPE(id) ((id) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DEVID_9005_MAXRATE_U160 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DEVID_9005_MAXRATE_ULTRA2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEVID_9005_MAXRATE_ULTRA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DEVID_9005_MAXRATE_FAST 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SUBID_9005_TYPE(id) ((id) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SUBID_9005_TYPE_KNOWN(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SUBID_9005_MAXRATE_ULTRA2 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SUBID_9005_MAXRATE_ULTRA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SUBID_9005_MAXRATE_U160 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SUBID_9005_MAXRATE_RESERVED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SUBID_9005_SEEPTYPE(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ? ((id) & 0xC0) >> 6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : ((id) & 0x300) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SUBID_9005_SEEPTYPE_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SUBID_9005_SEEPTYPE_1K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SUBID_9005_SEEPTYPE_2K_4K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SUBID_9005_SEEPTYPE_RESERVED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SUBID_9005_AUTOTERM(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ? (((id) & 0x400) >> 10) == 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) : (((id) & 0x40) >> 6) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SUBID_9005_NUMCHAN(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ? ((id) & 0x300) >> 8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) : ((id) & 0xC00) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SUBID_9005_LEGACYCONN(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ? 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) : ((id) & 0x80) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SUBID_9005_MFUNCENB(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ? ((id) & 0x800) >> 11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) : ((id) & 0x1000) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Informational only. Should use chip register to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * certain, but may be use in identification strings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static ahc_device_setup_t ahc_aic785X_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static ahc_device_setup_t ahc_aic7860_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static ahc_device_setup_t ahc_apa1480_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static ahc_device_setup_t ahc_aic7870_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static ahc_device_setup_t ahc_aic7870h_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static ahc_device_setup_t ahc_aha394X_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static ahc_device_setup_t ahc_aha394Xh_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static ahc_device_setup_t ahc_aha494X_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static ahc_device_setup_t ahc_aha494Xh_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static ahc_device_setup_t ahc_aha398X_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static ahc_device_setup_t ahc_aic7880_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static ahc_device_setup_t ahc_aic7880h_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static ahc_device_setup_t ahc_aha2940Pro_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static ahc_device_setup_t ahc_aha394XU_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static ahc_device_setup_t ahc_aha394XUh_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static ahc_device_setup_t ahc_aha398XU_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static ahc_device_setup_t ahc_aic7890_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static ahc_device_setup_t ahc_aic7892_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static ahc_device_setup_t ahc_aic7895_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static ahc_device_setup_t ahc_aic7895h_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static ahc_device_setup_t ahc_aic7896_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static ahc_device_setup_t ahc_aic7899_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static ahc_device_setup_t ahc_aha29160C_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static ahc_device_setup_t ahc_raid_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static ahc_device_setup_t ahc_aha394XX_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static ahc_device_setup_t ahc_aha494XX_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static ahc_device_setup_t ahc_aha398XX_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct ahc_pci_identity ahc_pci_ident_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* aic7850 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ID_AHA_2902_04_10_15_20C_30C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ahc_aic785X_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* aic7860 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ID_AHA_2930CU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "Adaptec 2930CU SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ahc_aic7860_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ID_AHA_1480A & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "Adaptec 1480A Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ahc_apa1480_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "Adaptec 2940A Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ahc_aic7860_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "Adaptec 2940A/CN Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ahc_aic7860_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "Adaptec 2930C Ultra SCSI adapter (VAR)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ahc_aic7860_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* aic7870 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ID_AHA_2940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "Adaptec 2940 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ahc_aic7870_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ID_AHA_3940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Adaptec 3940 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ahc_aha394X_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ID_AHA_398X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "Adaptec 398X SCSI RAID adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ahc_aha398X_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ID_AHA_2944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "Adaptec 2944 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ahc_aic7870h_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ID_AHA_3944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "Adaptec 3944 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ahc_aha394Xh_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ID_AHA_4944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "Adaptec 4944 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ahc_aha494Xh_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* aic7880 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ID_AHA_2940U & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "Adaptec 2940 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ahc_aic7880_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ID_AHA_3940U & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "Adaptec 3940 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ahc_aha394XU_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ID_AHA_2944U & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "Adaptec 2944 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ahc_aic7880h_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ID_AHA_3944U & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "Adaptec 3944 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ahc_aha394XUh_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ID_AHA_398XU & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "Adaptec 398X Ultra SCSI RAID adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ahc_aha398XU_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * XXX Don't know the slot numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * so we can't identify channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ID_AHA_4944U & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "Adaptec 4944 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ahc_aic7880h_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ID_AHA_2930U & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "Adaptec 2930 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ahc_aic7880_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "Adaptec 2940 Pro Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ahc_aha2940Pro_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "Adaptec 2940/CN Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ahc_aic7880_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Ignore all SISL (AAC on MB) based controllers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ID_9005_SISL_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ID_9005_SISL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* aic7890 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ID_AHA_2930U2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Adaptec 2930 Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ID_AHA_2940U2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "Adaptec 2940B Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ID_AHA_2940U2_OEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ID_AHA_2940U2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "Adaptec 2940 Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ID_AHA_2950U2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "Adaptec 2950 Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ID_AIC7890_ARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ID_AAA_131U2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "Adaptec AAA-131 Ultra2 RAID adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* aic7892 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ID_AHA_29160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "Adaptec 29160 Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ID_AHA_29160_CPQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ID_AHA_29160N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "Adaptec 29160N Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ID_AHA_29160C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "Adaptec 29160C Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ahc_aha29160C_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ID_AHA_29160B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "Adaptec 29160B Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ID_AHA_19160B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Adaptec 19160B Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ID_AIC7892_ARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ID_AHA_2915_30LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "Adaptec 2915/30LP Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* aic7895 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ID_AHA_2940U_DUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "Adaptec 2940/DUAL Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ahc_aic7895_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ID_AHA_3940AU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "Adaptec 3940A Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ahc_aic7895_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ID_AHA_3944AU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "Adaptec 3944A Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ahc_aic7895h_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ID_AIC7895_ARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ID_AIC7895_ARO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "Adaptec aic7895 Ultra SCSI adapter (ARO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ahc_aic7895_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* aic7896/97 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ID_AHA_3950U2B_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "Adaptec 3950B Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ahc_aic7896_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ID_AHA_3950U2B_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "Adaptec 3950B Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ahc_aic7896_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ID_AHA_3950U2D_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "Adaptec 3950D Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ahc_aic7896_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ID_AHA_3950U2D_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "Adaptec 3950D Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ahc_aic7896_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ID_AIC7896_ARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ahc_aic7896_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* aic7899 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ID_AHA_3960D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "Adaptec 3960D Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ahc_aic7899_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ID_AHA_3960D_CPQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ahc_aic7899_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ID_AIC7899_ARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ahc_aic7899_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Generic chip probes for devices we don't know 'exactly' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ID_AIC7850 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "Adaptec aic7850 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ahc_aic785X_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ID_AIC7855 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "Adaptec aic7855 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ahc_aic785X_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ID_AIC7859 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "Adaptec aic7859 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ahc_aic7860_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ID_AIC7860 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "Adaptec aic7860 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ahc_aic7860_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ID_AIC7870 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "Adaptec aic7870 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ahc_aic7870_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ID_AIC7880 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "Adaptec aic7880 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ahc_aic7880_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ID_AIC7890 & ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "Adaptec aic7890/91 Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ahc_aic7890_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ID_AIC7892 & ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "Adaptec aic7892 Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ahc_aic7892_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ID_AIC7895 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "Adaptec aic7895 Ultra SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ahc_aic7895_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ID_AIC7896 & ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "Adaptec aic7896/97 Ultra2 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ahc_aic7896_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ID_AIC7899 & ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "Adaptec aic7899 Ultra160 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ahc_aic7899_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ID_AIC7810 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "Adaptec aic7810 RAID memory controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ahc_raid_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ID_AIC7815 & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "Adaptec aic7815 RAID memory controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ahc_raid_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define AHC_394X_SLOT_CHANNEL_A 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define AHC_394X_SLOT_CHANNEL_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define AHC_398X_SLOT_CHANNEL_A 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define AHC_398X_SLOT_CHANNEL_B 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define AHC_398X_SLOT_CHANNEL_C 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define AHC_494X_SLOT_CHANNEL_A 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define AHC_494X_SLOT_CHANNEL_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define AHC_494X_SLOT_CHANNEL_C 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define AHC_494X_SLOT_CHANNEL_D 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define DEVCONFIG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define PCIERRGENDIS 0x80000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SCBSIZE32 0x00010000ul /* aic789X only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define REXTVALID 0x00001000ul /* ultra cards only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define MPORTMODE 0x00000400ul /* aic7870+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define RAMPSM 0x00000200ul /* aic7870+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define VOLSENSE 0x00000100ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SCBRAMSEL 0x00000080ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MRDCEN 0x00000040ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define EXTSCBTIME 0x00000020ul /* aic7870 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define EXTSCBPEN 0x00000010ul /* aic7870 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define BERREN 0x00000008ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DACEN 0x00000004ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define STPWLEVEL 0x00000002ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define CSIZE_LATTIME 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define CACHESIZE 0x0000003ful /* only 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define LATTIME 0x0000ff00ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* PCI STATUS definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define DPE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SSE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define RMA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define RTA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define STA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define DPR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uint16_t subdevice, uint16_t subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int ahc_ext_scbram_present(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int pcheck, int fast, int large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct seeprom_config *sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void configure_termination(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct seeprom_descriptor *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u_int adapter_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u_int *sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void ahc_new_term_detect(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int *enableSEC_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int *enableSEC_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int *enablePRI_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int *enablePRI_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int *eeprom_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int *internal68_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int *externalcable_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int *eeprom_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int *externalcable_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int *eeprom_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static uint8_t read_brdctl(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void ahc_pci_intr(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int ahc_pci_chip_init(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) uint16_t subdevice, uint16_t subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Default to invalid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (vendor == 0x9005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) && subvendor == 0x9005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) && subdevice != device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) switch (SUBID_9005_TYPE(subdevice)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case SUBID_9005_TYPE_MB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case SUBID_9005_TYPE_CARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case SUBID_9005_TYPE_LCCARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Currently only trust Adaptec cards to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * get the sub device info correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) result = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case SUBID_9005_TYPE_RAID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return (result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) const struct ahc_pci_identity *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ahc_find_pci_device(ahc_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uint64_t full_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint16_t device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint16_t vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint16_t subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint16_t subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) const struct ahc_pci_identity *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u_int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * If the second function is not hooked up, ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Unfortunately, not all MB vendors implement the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * subdevice ID as per the Adaptec spec, so do our best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * to sanity check it prior to accepting the subdevice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * ID as valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ahc_get_pci_function(pci) > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) && SUBID_9005_MFUNCENB(subdevice) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) for (i = 0; i < ahc_num_pci_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) entry = &ahc_pci_ident_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (entry->full_id == (full_id & entry->id_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Honor exclusion entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (entry->name == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return (entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ahc_pci_config(struct ahc_softc *ahc, const struct ahc_pci_identity *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u_int command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u_int our_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u_int sxfrctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u_int scsiseq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u_int dscommand0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) uint8_t sblkctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) our_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) error = entry->setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ahc->chip |= AHC_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ahc->description = entry->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) error = ahc_pci_map_registers(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * Before we continue probing the card, ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * its interrupts are *disabled*. We don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * a misstep to hang the machine in an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * storm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ahc_intr_enable(ahc, FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * If we need to support high memory, enable dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * address cycles. This bit must be set to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * high address bit generation even if we are on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * 64bit bus (PCI64BIT set in devconfig).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) printk("%s: Enabling 39Bit Addressing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) devconfig |= DACEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Ensure that pci error generation, a test feature, is disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) devconfig |= PCIERRGENDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Ensure busmastering is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) command |= PCIM_CMD_BUSMASTEREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* On all PCI adapters, we allow SCB paging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ahc->flags |= AHC_PAGESCBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) error = ahc_softc_init(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Disable PCI parity error checking. Users typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * do this to work around broken PCI chipsets that get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * the parity timing wrong and thus generate lots of spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * errors. The chip only allows us to disable *all* parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * error reporting when doing this, so CIO bus, scb ram, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * scratch ram parity errors will be ignored too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ahc->seqctl |= FAILDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ahc->bus_intr = ahc_pci_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ahc->bus_chip_init = ahc_pci_chip_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Remember how the card was setup in case there is no SEEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ahc_pause(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) our_id = ahc_inb(ahc, SCSIID) & OID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) scsiseq = ahc_inb(ahc, SCSISEQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) sxfrctl1 = STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) our_id = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) scsiseq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) error = ahc_reset(ahc, /*reinit*/FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return (ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if ((ahc->features & AHC_DT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u_int sfunct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Perform ALT-Mode Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ahc_outb(ahc, OPTIONMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ahc_outb(ahc, SFUNCT, sfunct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Normal mode setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) |TARGCRCENDEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dscommand0 = ahc_inb(ahc, DSCOMMAND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dscommand0 |= MPARCKEN|CACHETHEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((ahc->features & AHC_ULTRA2) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * DPARCKEN doesn't work correctly on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * some MBs so don't use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dscommand0 &= ~DPARCKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * Handle chips that must have cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * streaming (dis/en)abled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dscommand0 |= CACHETHEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dscommand0 &= ~CACHETHEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ahc_outb(ahc, DSCOMMAND0, dscommand0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ahc->pci_cachesize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*bytes*/1) & CACHESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ahc->pci_cachesize *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) && ahc->pci_cachesize == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 0, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ahc->pci_cachesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * We cannot perform ULTRA speeds without the presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * of the external precision resistor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if ((ahc->features & AHC_ULTRA) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) devconfig = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if ((devconfig & REXTVALID) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ahc->features &= ~AHC_ULTRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* See if we have a SEEPROM and perform auto-term */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) check_extport(ahc, &sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Take the LED out of diagnostic mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) sblkctl = ahc_inb(ahc, SBLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if ((ahc->features & AHC_ULTRA2) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ahc->flags & AHC_USEDEFAULTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * PCI Adapter default setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Should only be used if the adapter does not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * a SEEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* See if someone else set us up already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) && scsiseq != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) printk("%s: Using left over BIOS settings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ahc->flags &= ~AHC_USEDEFAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ahc->flags |= AHC_BIOS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Assume only one connector and always turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * on termination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) our_id = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) sxfrctl1 = STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ahc->our_id = our_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * Take a look to see if we have external SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * We currently do not attempt to use SRAM that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * shared among multiple controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ahc_probe_ext_scbram(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * Record our termination setting for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * generic initialization routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if ((sxfrctl1 & STPWEN) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ahc->flags |= AHC_TERM_ENB_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Save chip register configuration data for chip resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * that occur during runtime and resume events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ahc->bus_softc.pci_softc.devconfig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ahc->bus_softc.pci_softc.command =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ahc->bus_softc.pci_softc.csize_lattime =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if ((ahc->features & AHC_DT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u_int sfunct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ahc_outb(ahc, SFUNCT, sfunct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ahc->bus_softc.pci_softc.crccontrol1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ahc_inb(ahc, CRCCONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if ((ahc->features & AHC_MULTI_FUNC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Core initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) error = ahc_init(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ahc->init_level++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * Allow interrupts now that we are completely setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return ahc_pci_map_int(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * Test for the presence of external sram in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * "unshared" configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ahc_ext_scbram_present(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u_int chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int ramps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int single_user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) chip = ahc->chip & AHC_CHIPID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) devconfig = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) single_user = (devconfig & MPORTMODE) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * External SCBRAM arbitration is flakey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * on these chips. Unfortunately this means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * we don't use the extra SCB ram space on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * 3940AUW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ramps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) else if (chip >= AHC_AIC7870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ramps = (devconfig & RAMPSM) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ramps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (ramps && single_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * Enable external scbram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int fast, int large)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ahc->features & AHC_MULTI_FUNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * Set the SCB Base addr (highest address bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * depending on which channel we are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ahc->flags &= ~AHC_LSCBS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (large)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ahc->flags |= AHC_LSCBS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if ((ahc->features & AHC_ULTRA2) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u_int dscommand0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dscommand0 = ahc_inb(ahc, DSCOMMAND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dscommand0 &= ~INTSCBRAMSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dscommand0 |= INTSCBRAMSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (large)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dscommand0 &= ~USCBSIZE32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dscommand0 |= USCBSIZE32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ahc_outb(ahc, DSCOMMAND0, dscommand0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (fast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) devconfig &= ~EXTSCBTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) devconfig |= EXTSCBTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) devconfig &= ~SCBRAMSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) devconfig |= SCBRAMSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (large)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) devconfig &= ~SCBSIZE32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) devconfig |= SCBSIZE32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (pcheck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) devconfig |= EXTSCBPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) devconfig &= ~EXTSCBPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * Take a look to see if we have external SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * We currently do not attempt to use SRAM that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * shared among multiple controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ahc_probe_ext_scbram(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int num_scbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int test_num_scbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int pcheck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) int large;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) enable = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pcheck = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) fast = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) large = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) num_scbs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (ahc_ext_scbram_present(ahc) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Probe for the best parameters to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) num_scbs = ahc_probe_scbs(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (num_scbs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* The SRAM wasn't really present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) enable = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * Clear any outstanding parity error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * and ensure that parity error reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ahc_outb(ahc, SEQCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ahc_outb(ahc, CLRINT, CLRBRKADRINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Now see if we can do parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) num_scbs = ahc_probe_scbs(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pcheck = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Clear any resulting parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ahc_outb(ahc, CLRINT, CLRBRKADRINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* Now see if we can do fast timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) test_num_scbs = ahc_probe_scbs(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (test_num_scbs == num_scbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) fast = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * See if we can use large SCBs and still maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * the same overall count of SCBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if ((ahc->features & AHC_LARGE_SCBS) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) test_num_scbs = ahc_probe_scbs(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (test_num_scbs >= num_scbs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) large = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) num_scbs = test_num_scbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (num_scbs >= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * We have enough space to move the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * "busy targets table" into SCB space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * and make it qualify all the way to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * lun level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ahc->flags |= AHC_SCB_BTT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * Disable parity error reporting until we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * can load instruction ram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Clear any latched parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ahc_outb(ahc, CLRINT, CLRBRKADRINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (bootverbose && enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) printk("%s: External SRAM, %s access%s, %dbytes/SCB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ahc_name(ahc), fast ? "fast" : "slow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pcheck ? ", parity checking enabled" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) large ? 64 : 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ahc_scbram_config(ahc, enable, pcheck, fast, large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * Perform some simple tests that should catch situations where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * our registers are invalidly mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ahc_pci_test_register_access(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u_int status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) uint32_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) uint8_t hcntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) error = EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * Enable PCI error interrupt status, but suppress NMIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * generated by SERR raised due to target aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * First a simple test to see if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * registers can be read. Reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * HCNTRL has no side effects and has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * at least one bit that is guaranteed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * be zero so it is a good register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * use for this test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) hcntrl = ahc_inb(ahc, HCNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (hcntrl == 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if ((hcntrl & CHIPRST) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * The chip has not been initialized since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * PCI/EISA/VLB bus reset. Don't trust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * "left over BIOS data".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ahc->flags |= AHC_NO_BIOS_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Next create a situation where write combining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * or read prefetching could be initiated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * CPU or host bridge. Our device does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * either, so look for data corruption and/or flagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * PCI errors. First pause without causing another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * chip reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) hcntrl &= ~CHIPRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) while (ahc_is_paused(ahc) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* Clear any PCI errors that occurred before our driver attached. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) status1 = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) status1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ahc_outb(ahc, SEQCTL, PERRORDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ahc_outb(ahc, SCBPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) status1 = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if ((status1 & STA) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Silently clear any latched errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) status1 = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) status1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * Check the external port logic for a serial eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * and termination/cable detection contrls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct seeprom_descriptor sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct seeprom_config *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) int have_seeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) int have_autoterm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) sd.sd_ahc = ahc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) sd.sd_control_offset = SEECTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) sd.sd_status_offset = SEECTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) sd.sd_dataout_offset = SEECTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) sc = ahc->seep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * For some multi-channel devices, the c46 is simply too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * small to work. For the other controller types, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * get our information from either SEEPROM type. Set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * type to start our probe with accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (ahc->flags & AHC_LARGE_SEEPROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) sd.sd_chip = C56_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) sd.sd_chip = C46;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) sd.sd_MS = SEEMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) sd.sd_RDY = SEERDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) sd.sd_CS = SEECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) sd.sd_CK = SEECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) sd.sd_DO = SEEDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) sd.sd_DI = SEEDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) have_seeprom = ahc_acquire_seeprom(ahc, &sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) printk("%s: Reading SEEPROM...", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u_int start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) start_addr = 32 * (ahc->channel - 'A');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) start_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) sizeof(*sc)/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (have_seeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) have_seeprom = ahc_verify_cksum(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (have_seeprom != 0 || sd.sd_chip == C56_66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (bootverbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (have_seeprom == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) printk ("checksum error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) printk ("done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) sd.sd_chip = C56_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ahc_release_seeprom(&sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Remember the SEEPROM type for later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (sd.sd_chip == C56_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ahc->flags |= AHC_LARGE_SEEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * Pull scratch ram settings and treat them as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * if they are the contents of an seeprom if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * the 'ADPT' signature is found in SCB2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * We manually compose the data as 16bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * to avoid endian issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ahc_outb(ahc, SCBPTR, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ahc_inb(ahc, SCB_BASE) == 'A'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) && ahc_inb(ahc, SCB_BASE + 1) == 'D'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) && ahc_inb(ahc, SCB_BASE + 2) == 'P'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) uint16_t *sc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sc_data = (uint16_t *)sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) for (i = 0; i < 32; i++, sc_data++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) j = i * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) *sc_data = ahc_inb(ahc, SRAM_BASE + j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) have_seeprom = ahc_verify_cksum(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (have_seeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ahc->flags |= AHC_SCB_CONFIG_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * Clear any SCB parity errors in case this data and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * its associated parity was not initialized by the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ahc_outb(ahc, CLRINT, CLRBRKADRINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (!have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) printk("%s: No SEEPROM available.\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ahc->flags |= AHC_USEDEFAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) kfree(ahc->seep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ahc->seep_config = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) sc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ahc_parse_pci_eeprom(ahc, sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * Cards that have the external logic necessary to talk to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * a SEEPROM, are almost certain to have the remaining logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * necessary for auto-termination control. This assumption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * hasn't failed yet...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) have_autoterm = have_seeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * Some low-cost chips have SEEPROM and auto-term control built
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * in, instead of using a GAL. They can tell us directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * if the termination logic is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if ((ahc->features & AHC_SPIOCAP) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) have_autoterm = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (have_autoterm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ahc->flags |= AHC_HAS_TERM_LOGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ahc_acquire_seeprom(ahc, &sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ahc_release_seeprom(&sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) } else if (have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) *sxfrctl1 &= ~STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if ((sc->adapter_control & CFSTERM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) *sxfrctl1 |= STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) printk("%s: Low byte termination %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) (*sxfrctl1 & STPWEN) ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * Put the data we've collected down into SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * where ahc_init will find it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) int max_targ = sc->max_targets & CFMAXTARG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u_int scsi_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) uint16_t discenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) uint16_t ultraenb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) discenable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ultraenb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if ((sc->adapter_control & CFULTRAEN) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * Determine if this adapter has a "newstyle"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * SEEPROM format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) for (i = 0; i < max_targ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ahc->flags |= AHC_NEWEEPROM_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) for (i = 0; i < max_targ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) u_int scsirate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) uint16_t target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) target_mask = 0x01 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (sc->device_flags[i] & CFDISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) discenable |= target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ultraenb |= target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) } else if ((sc->adapter_control & CFULTRAEN) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ultraenb |= target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if ((sc->device_flags[i] & CFXFER) == 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) && (ultraenb & target_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Treat 10MHz as a non-ultra speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) sc->device_flags[i] &= ~CFXFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ultraenb &= ~target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if ((ahc->features & AHC_ULTRA2) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u_int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (sc->device_flags[i] & CFSYNCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) offset = MAX_OFFSET_ULTRA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ahc_outb(ahc, TARG_OFFSET + i, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * The ultra enable bits contain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * high bit of the ultra2 sync rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) scsirate = (sc->device_flags[i] & CFXFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) | ((ultraenb & target_mask) ? 0x8 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (sc->device_flags[i] & CFWIDEB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) scsirate |= WIDEXFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) scsirate = (sc->device_flags[i] & CFXFER) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (sc->device_flags[i] & CFSYNCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) scsirate |= SOFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (sc->device_flags[i] & CFWIDEB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) scsirate |= WIDEXFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ahc->our_id = sc->brtime_id & CFSCSIID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) scsi_conf = (ahc->our_id & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (sc->adapter_control & CFSPARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) scsi_conf |= ENSPCHK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (sc->adapter_control & CFRESETB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) scsi_conf |= RESET_SCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (sc->bios_control & CFEXTEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ahc->flags |= AHC_EXTENDED_TRANS_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (sc->bios_control & CFBIOSEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ahc->flags |= AHC_BIOS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (ahc->features & AHC_ULTRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* Should we enable Ultra mode? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (!(sc->adapter_control & CFULTRAEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* Treat us as a non-ultra card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ultraenb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (sc->signature == CFSIGNATURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) || sc->signature == CFSIGNATURE2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* Honor the STPWLEVEL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) devconfig = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) devconfig &= ~STPWLEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if ((sc->bios_control & CFSTPWLEVEL) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) devconfig |= STPWLEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* Set SCSICONF info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ahc_outb(ahc, SCSICONF, scsi_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) configure_termination(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct seeprom_descriptor *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) u_int adapter_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) u_int *sxfrctl1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) uint8_t brddat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) brddat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * Update the settings in sxfrctl1 to match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * termination settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) *sxfrctl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * SEECS must be on for the GALS to latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * the data properly. Be sure to leave MS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * on or we will release the seeprom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if ((adapter_control & CFAUTOTERM) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) || (ahc->features & AHC_NEW_TERMCTL) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) int internal50_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int internal68_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) int externalcable_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) int eeprom_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int enableSEC_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) int enableSEC_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) int enablePRI_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) int enablePRI_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) enableSEC_low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) enableSEC_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) enablePRI_low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) enablePRI_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ahc_new_term_detect(ahc, &enableSEC_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) &enableSEC_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) &enablePRI_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) &enablePRI_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) &eeprom_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if ((adapter_control & CFSEAUTOTERM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) printk("%s: Manual SE Termination\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) enableSEC_low = (adapter_control & CFSELOWTERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) enableSEC_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) (adapter_control & CFSEHIGHTERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if ((adapter_control & CFAUTOTERM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) printk("%s: Manual LVD Termination\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) enablePRI_low = (adapter_control & CFSTERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) enablePRI_high = (adapter_control & CFWSTERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* Make the table calculations below happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) internal50_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) internal68_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) externalcable_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) } else if ((ahc->features & AHC_SPIOCAP) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) aic785X_cable_detect(ahc, &internal50_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) &externalcable_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) &eeprom_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* Can never support a wide connector. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) internal68_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) aic787X_cable_detect(ahc, &internal50_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) &internal68_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) &externalcable_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) &eeprom_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if ((ahc->features & AHC_WIDE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) internal68_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (bootverbose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) && (ahc->features & AHC_ULTRA2) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) printk("%s: internal 50 cable %s present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) internal50_present ? "is":"not");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if ((ahc->features & AHC_WIDE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) printk(", internal 68 cable %s present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) internal68_present ? "is":"not");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) printk("\n%s: external cable %s present\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) externalcable_present ? "is":"not");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) printk("%s: BIOS eeprom %s present\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ahc_name(ahc), eeprom_present ? "is" : "not");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * The 50 pin connector is a separate bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * so force it to always be terminated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * In the future, perform current sensing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * to determine if we are in the middle of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * a properly terminated bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) internal50_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * Now set the termination based on what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * we found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * Flash Enable = BRDDAT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * Secondary High Term Enable = BRDDAT6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * Secondary Low Term Enable = BRDDAT5 (7890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * Primary High Term Enable = BRDDAT4 (7890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if ((ahc->features & AHC_ULTRA2) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) && (internal50_present != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) && (internal68_present != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) && (externalcable_present != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) printk("%s: Illegal cable configuration!!. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) "Only two connectors on the "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) "adapter may be used at a "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) "time!\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * Pretend there are no cables in the hope
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * that having all of the termination on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * gives us a more stable bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) internal50_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) internal68_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) externalcable_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if ((ahc->features & AHC_WIDE) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) && ((externalcable_present == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) || (internal68_present == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) || (enableSEC_high != 0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) brddat |= BRDDAT6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (bootverbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) printk("%s: 68 pin termination "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) "Enabled\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) printk("%s: %sHigh byte termination "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) "Enabled\n", ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) enableSEC_high ? "Secondary "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) sum = internal50_present + internal68_present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) + externalcable_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (sum < 2 || (enableSEC_low != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) brddat |= BRDDAT5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) *sxfrctl1 |= STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (bootverbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) printk("%s: 50 pin termination "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) "Enabled\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) printk("%s: %sLow byte termination "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) "Enabled\n", ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) enableSEC_low ? "Secondary "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (enablePRI_low != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) *sxfrctl1 |= STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) printk("%s: Primary Low Byte termination "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) "Enabled\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * Setup STPWEN before setting up the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * the termination per the tech note on the U160 cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (enablePRI_high != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) brddat |= BRDDAT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) printk("%s: Primary High Byte "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) "termination Enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) write_brdctl(ahc, brddat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if ((adapter_control & CFSTERM) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) *sxfrctl1 |= STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) printk("%s: %sLow byte termination Enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) (ahc->features & AHC_ULTRA2) ? "Primary "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if ((adapter_control & CFWSTERM) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) && (ahc->features & AHC_WIDE) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) brddat |= BRDDAT6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) printk("%s: %sHigh byte termination Enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) (ahc->features & AHC_ULTRA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ? "Secondary " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * Setup STPWEN before setting up the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * the termination per the tech note on the U160 cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if ((ahc->features & AHC_WIDE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) write_brdctl(ahc, brddat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) int *enableSEC_high, int *enablePRI_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) int *enablePRI_high, int *eeprom_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) uint8_t brdctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * BRDDAT7 = Eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * BRDDAT6 = Enable Secondary High Byte termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * BRDDAT5 = Enable Secondary Low Byte termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * BRDDAT4 = Enable Primary high byte termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * BRDDAT3 = Enable Primary low byte termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) brdctl = read_brdctl(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) *eeprom_present = brdctl & BRDDAT7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) *enableSEC_high = (brdctl & BRDDAT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *enableSEC_low = (brdctl & BRDDAT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) *enablePRI_high = (brdctl & BRDDAT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) *enablePRI_low = (brdctl & BRDDAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) int *internal68_present, int *externalcable_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) int *eeprom_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) uint8_t brdctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * First read the status of our cables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * Set the rom bank to 0 since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * bank setting serves as a multiplexor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * for the cable detection logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) * BRDDAT5 controls the bank switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) write_brdctl(ahc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * Now read the state of the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * connectors. BRDDAT6 is INT50 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * BRDDAT7 is INT68.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) brdctl = read_brdctl(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * Set the rom bank to 1 and determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * the other signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) write_brdctl(ahc, BRDDAT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * Now read the state of the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * connectors. BRDDAT6 is EXT68 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * BRDDAT7 is EPROMPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) brdctl = read_brdctl(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) int *externalcable_present, int *eeprom_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) uint8_t brdctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) uint8_t spiocap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) spiocap = ahc_inb(ahc, SPIOCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) spiocap &= ~SOFTCMDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) spiocap |= EXT_BRDCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ahc_outb(ahc, SPIOCAP, spiocap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ahc_flush_device_writes(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ahc_delay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ahc_outb(ahc, BRDCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ahc_flush_device_writes(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ahc_delay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) brdctl = ahc_inb(ahc, BRDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if ((ahc->features & AHC_SPIOCAP) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * Request access of the memory port. When access is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * granted, SEERDY will go high. We use a 1 second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * timeout which should be near 1 second more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * is needed. Reason: after the chip reset, there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * should be no contention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SEEPROM_OUTB(sd, sd->sd_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) wait = 1000; /* 1 second timeout in msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ahc_delay(1000); /* delay 1 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) SEEPROM_OUTB(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ahc_release_seeprom(struct seeprom_descriptor *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* Release access to the memory port and the serial EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) SEEPROM_OUTB(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) write_brdctl(struct ahc_softc *ahc, uint8_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) uint8_t brdctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) brdctl = BRDSTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (ahc->channel == 'B')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) brdctl |= BRDCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) } else if ((ahc->features & AHC_ULTRA2) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) brdctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) brdctl = BRDSTB|BRDCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ahc_outb(ahc, BRDCTL, brdctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ahc_flush_device_writes(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) brdctl |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ahc_outb(ahc, BRDCTL, brdctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ahc_flush_device_writes(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) brdctl |= BRDSTB_ULTRA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) brdctl &= ~BRDSTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ahc_outb(ahc, BRDCTL, brdctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ahc_flush_device_writes(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) brdctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) brdctl &= ~BRDCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ahc_outb(ahc, BRDCTL, brdctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static uint8_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) read_brdctl(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) uint8_t brdctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) uint8_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) brdctl = BRDRW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (ahc->channel == 'B')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) brdctl |= BRDCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) } else if ((ahc->features & AHC_ULTRA2) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) brdctl = BRDRW_ULTRA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) brdctl = BRDRW|BRDCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ahc_outb(ahc, BRDCTL, brdctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ahc_flush_device_writes(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) value = ahc_inb(ahc, BRDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) ahc_outb(ahc, BRDCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return (value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ahc_pci_intr(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) u_int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) u_int status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) error = ahc_inb(ahc, ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if ((error & PCIERRSTAT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) status1 = ahc_pci_read_config(ahc->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) printk("%s: PCI error Interrupt at seqaddr = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (status1 & DPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ahc->pci_target_perr_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) printk("%s: Data Parity Error Detected during address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) "or write data phase\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (status1 & SSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) printk("%s: Signal System Error Detected\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (status1 & RMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) printk("%s: Received a Master Abort\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (status1 & RTA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) printk("%s: Received a Target Abort\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (status1 & STA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) printk("%s: Signaled a Target Abort\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (status1 & DPR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) printk("%s: Data Parity Error has been reported via PERR#\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* Clear latched errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) status1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) printk("%s: Latched PCIERR interrupt with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "no status bits set\n", ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ahc_outb(ahc, CLRINT, CLRPARERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) printk(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "%s: WARNING WARNING WARNING WARNING\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "%s: Too many PCI parity errors observed as a target.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) "%s: Some device on this bus is generating bad parity.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) "%s: This is an error *observed by*, not *generated by*, this controller.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) "%s: PCI parity error checking has been disabled.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) "%s: WARNING WARNING WARNING WARNING\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ahc->seqctl |= FAILDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ahc_outb(ahc, SEQCTL, ahc->seqctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ahc_unpause(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ahc_pci_chip_init(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if ((ahc->features & AHC_DT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) u_int sfunct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ahc_outb(ahc, SFUNCT, sfunct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ahc_outb(ahc, CRCCONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ahc->bus_softc.pci_softc.crccontrol1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if ((ahc->features & AHC_MULTI_FUNC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if ((ahc->features & AHC_ULTRA2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return (ahc_chip_init(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ahc_pci_resume(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) * We assume that the OS has restored our register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * mappings, etc. Just update the config space registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * that the OS doesn't know about and rely on our chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * reset handler to handle the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ahc->bus_softc.pci_softc.command, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) struct seeprom_descriptor sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) u_int sxfrctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) sd.sd_ahc = ahc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) sd.sd_control_offset = SEECTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) sd.sd_status_offset = SEECTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) sd.sd_dataout_offset = SEECTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ahc_acquire_seeprom(ahc, &sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) configure_termination(ahc, &sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ahc->seep_config->adapter_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) &sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ahc_release_seeprom(&sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ahc_aic785X_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) uint8_t rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ahc->chip = AHC_AIC7850;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ahc->features = AHC_AIC7850_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (rev >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ahc->instruction_ram_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ahc_aic7860_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) uint8_t rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ahc->chip = AHC_AIC7860;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ahc->features = AHC_AIC7860_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (rev >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ahc->instruction_ram_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ahc_apa1480_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) error = ahc_aic7860_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ahc->features |= AHC_REMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ahc_aic7870_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ahc->chip = AHC_AIC7870;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ahc->features = AHC_AIC7870_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) ahc->instruction_ram_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ahc_aic7870h_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) int error = ahc_aic7870_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ahc->features |= AHC_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) ahc_aha394X_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) error = ahc_aic7870_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) error = ahc_aha394XX_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ahc_aha394Xh_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) int error = ahc_aha394X_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ahc->features |= AHC_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) ahc_aha398X_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) error = ahc_aic7870_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) error = ahc_aha398XX_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ahc_aha494X_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) error = ahc_aic7870_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) error = ahc_aha494XX_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ahc_aha494Xh_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) int error = ahc_aha494X_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ahc->features |= AHC_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ahc_aic7880_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) uint8_t rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ahc->chip = AHC_AIC7880;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) ahc->features = AHC_AIC7880_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (rev >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ahc->instruction_ram_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ahc_aic7880h_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) int error = ahc_aic7880_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ahc->features |= AHC_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) ahc_aha2940Pro_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ahc->flags |= AHC_INT50_SPEEDFLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) return (ahc_aic7880_setup(ahc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) ahc_aha394XU_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) error = ahc_aic7880_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) error = ahc_aha394XX_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ahc_aha394XUh_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) int error = ahc_aha394XU_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) ahc->features |= AHC_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) ahc_aha398XU_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) error = ahc_aic7880_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) error = ahc_aha398XX_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ahc_aic7890_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) uint8_t rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) ahc->chip = AHC_AIC7890;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ahc->features = AHC_AIC7890_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) ahc->flags |= AHC_NEWEEPROM_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) if (rev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) ahc->instruction_ram_size = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ahc_aic7892_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ahc->chip = AHC_AIC7892;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ahc->features = AHC_AIC7892_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ahc->flags |= AHC_NEWEEPROM_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ahc->instruction_ram_size = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ahc_aic7895_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) uint8_t rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * The 'C' revision of the aic7895 has a few additional features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (rev >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ahc->chip = AHC_AIC7895C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ahc->features = AHC_AIC7895C_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) u_int command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ahc->chip = AHC_AIC7895;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ahc->features = AHC_AIC7895_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * The BIOS disables the use of MWI transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * since it does not have the MWI bug work around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * we have. Disabling MWI reduces performance, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * turn it on again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) command |= PCIM_CMD_MWRICEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ahc->bugs |= AHC_PCI_MWI_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * XXX Does CACHETHEN really not work??? What about PCI retry?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) * on C level chips. Need to test, but for now, play it safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) | AHC_CACHETHEN_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) * Cachesize must also be zero due to stray DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) * problem when sitting behind some bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) devconfig |= MRDCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ahc->flags |= AHC_NEWEEPROM_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ahc->instruction_ram_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) ahc_aic7895h_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) int error = ahc_aic7895_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ahc->features |= AHC_HVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ahc_aic7896_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) ahc->chip = AHC_AIC7896;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ahc->features = AHC_AIC7896_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ahc->flags |= AHC_NEWEEPROM_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ahc->instruction_ram_size = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ahc_aic7899_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ahc->chip = AHC_AIC7899;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ahc->features = AHC_AIC7899_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) ahc->flags |= AHC_NEWEEPROM_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) ahc->instruction_ram_size = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ahc_aha29160C_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) error = ahc_aic7899_setup(ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) ahc->features |= AHC_REMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) ahc_raid_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) printk("RAID functionality unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) return (ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ahc_aha394XX_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) switch (ahc_get_pci_slot(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) case AHC_394X_SLOT_CHANNEL_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) case AHC_394X_SLOT_CHANNEL_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) ahc->channel = 'B';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) printk("adapter at unexpected slot %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) "unable to map to a channel\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ahc_get_pci_slot(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) ahc_aha398XX_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) switch (ahc_get_pci_slot(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) case AHC_398X_SLOT_CHANNEL_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) case AHC_398X_SLOT_CHANNEL_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) ahc->channel = 'B';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) case AHC_398X_SLOT_CHANNEL_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) ahc->channel = 'C';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) printk("adapter at unexpected slot %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "unable to map to a channel\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) ahc_get_pci_slot(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ahc->flags |= AHC_LARGE_SEEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) ahc_aha494XX_setup(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) ahc_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) pci = ahc->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) switch (ahc_get_pci_slot(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) case AHC_494X_SLOT_CHANNEL_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) case AHC_494X_SLOT_CHANNEL_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) ahc->channel = 'B';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) case AHC_494X_SLOT_CHANNEL_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ahc->channel = 'C';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) case AHC_494X_SLOT_CHANNEL_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ahc->channel = 'D';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) printk("adapter at unexpected slot %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) "unable to map to a channel\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) ahc_get_pci_slot(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ahc->channel = 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ahc->flags |= AHC_LARGE_SEEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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