^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Adaptec AIC7xxx device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1994 John Aycock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The University of Calgary Department of Computer Science.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Free Software Foundation; either version 2, or (at your option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * along with this program; see the file COPYING. If not, write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (c) 2000-2003 Adaptec Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm.h#151 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifndef _AIC7XXX_LINUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define _AIC7XXX_LINUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <scsi/scsi_eh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <scsi/scsi_transport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <scsi/scsi_transport_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Core SCSI definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AIC_LIB_PREFIX ahc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include "cam.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include "queue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include "scsi_message.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include "aiclib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*********************************** Debugging ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef CONFIG_AIC7XXX_DEBUG_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #ifdef CONFIG_AIC7XXX_DEBUG_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AHC_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AHC_DEBUG_OPTS CONFIG_AIC7XXX_DEBUG_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Compile in debugging code, but do not enable any printfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AHC_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* No debugging code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /************************* Forward Declarations *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ahc_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) typedef struct pci_dev *ahc_dev_softc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) typedef struct scsi_cmnd *ahc_io_ctx_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /******************************* Byte Order ***********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ahc_htobe16(x) cpu_to_be16(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ahc_htobe32(x) cpu_to_be32(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ahc_htobe64(x) cpu_to_be64(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ahc_htole16(x) cpu_to_le16(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ahc_htole32(x) cpu_to_le32(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ahc_htole64(x) cpu_to_le64(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ahc_be16toh(x) be16_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ahc_be32toh(x) be32_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ahc_be64toh(x) be64_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ahc_le16toh(x) le16_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ahc_le32toh(x) le32_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ahc_le64toh(x) le64_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /************************* Configuration Data *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern u_int aic7xxx_no_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern u_int aic7xxx_allow_memio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern struct scsi_host_template aic7xxx_driver_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /***************************** Bus Space/DMA **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) typedef uint32_t bus_size_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) BUS_SPACE_MEMIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) BUS_SPACE_PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } bus_space_tag_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u_long ioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) volatile uint8_t __iomem *maddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } bus_space_handle_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) typedef struct bus_dma_segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dma_addr_t ds_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bus_size_t ds_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } bus_dma_segment_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct ahc_linux_dma_tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bus_size_t alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bus_size_t boundary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bus_size_t maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) typedef struct ahc_linux_dma_tag* bus_dma_tag_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) typedef dma_addr_t bus_dmamap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) typedef int bus_dma_filter_t(void*, dma_addr_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BUS_DMA_WAITOK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BUS_DMA_NOWAIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BUS_DMA_ALLOCNOW 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BUS_DMA_LOAD_SEGS 0x4 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Argument is an S/G list not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * a single buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BUS_SPACE_MAXADDR 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ahc_dma_tag_create(struct ahc_softc *, bus_dma_tag_t /*parent*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bus_size_t /*alignment*/, bus_size_t /*boundary*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dma_addr_t /*lowaddr*/, dma_addr_t /*highaddr*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bus_dma_filter_t*/*filter*/, void */*filterarg*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bus_size_t /*maxsize*/, int /*nsegments*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bus_size_t /*maxsegsz*/, int /*flags*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bus_dma_tag_t */*dma_tagp*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void ahc_dma_tag_destroy(struct ahc_softc *, bus_dma_tag_t /*tag*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int ahc_dmamem_alloc(struct ahc_softc *, bus_dma_tag_t /*dmat*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void** /*vaddr*/, int /*flags*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bus_dmamap_t* /*mapp*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void ahc_dmamem_free(struct ahc_softc *, bus_dma_tag_t /*dmat*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void* /*vaddr*/, bus_dmamap_t /*map*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void ahc_dmamap_destroy(struct ahc_softc *, bus_dma_tag_t /*tag*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bus_dmamap_t /*map*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ahc_dmamap_load(struct ahc_softc *ahc, bus_dma_tag_t /*dmat*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bus_dmamap_t /*map*/, void * /*buf*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bus_size_t /*buflen*/, bus_dmamap_callback_t *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void */*callback_arg*/, int /*flags*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ahc_dmamap_unload(struct ahc_softc *, bus_dma_tag_t, bus_dmamap_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Operations performed by ahc_dmamap_sync().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * ahc_dmamap_sync is only used on buffers allocated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * the pci_alloc_consistent() API. Although I'm not sure how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * this works on architectures with a write buffer, Linux does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * not have an API to sync "coherent" memory. Perhaps we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * to do an mb()?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ahc_dmamap_sync(ahc, dma_tag, dmamap, offset, len, op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /********************************** Includes **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_AIC7XXX_REG_PRETTY_PRINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AIC_DEBUG_REGISTERS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AIC_DEBUG_REGISTERS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #include "aic7xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /***************************** Timer Facilities *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ahc_scb_timer_reset(struct scb *scb, u_int usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /***************************** SMP support ************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AIC7XXX_DRIVER_VERSION "7.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*************************** Device Data Structures ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * A per probed device structure used to deal with some error recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * scenarios that the Linux mid-layer code just doesn't know how to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * handle. The structure allocated for a device only becomes persistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * after a successfully completed inquiry command to the target when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * that inquiry data indicates a lun is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AHC_DEV_FREEZE_TIL_EMPTY = 0x02, /* Freeze queue until active == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) AHC_DEV_Q_BASIC = 0x10, /* Allow basic device queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AHC_DEV_Q_TAGGED = 0x20, /* Allow full SCSI2 command queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) AHC_DEV_PERIODIC_OTAG = 0x40, /* Send OTAG to prevent starvation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } ahc_linux_dev_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ahc_linux_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * The number of transactions currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * queued to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * The currently allowed number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * transactions that can be queued to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * the device. Must be signed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * conversion from tagged to untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * mode where the device may have more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * than one outstanding active transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int openings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * A positive count indicates that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * device's queue is halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u_int qfrozen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Cumulative command counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u_long commands_issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * The number of tagged transactions when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * running at our current opening level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * that have been successfully received by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * this device since the last QUEUE FULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u_int tag_success_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define AHC_TAG_SUCCESS_INTERVAL 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ahc_linux_dev_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * The high limit for the tags variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u_int maxtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * The computed number of tags outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * at the time of the last QUEUE FULL event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u_int tags_on_last_queuefull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * How many times we have seen a queue full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * with the same number of tags. This is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * to stop our adaptive queue depth algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * on devices with a fixed number of tags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u_int last_queuefull_same_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define AHC_LOCK_TAGS_COUNT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * How many transactions have been queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * without the device going idle. We use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * this statistic to determine when to issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * an ordered tag to prevent transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * starvation. This statistic is only updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * if the AHC_DEV_PERIODIC_OTAG flag is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * on this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u_int commands_since_idle_or_otag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define AHC_OTAG_THRESH 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /********************* Definitions Required by the Core ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Number of SG segments we require. So long as the S/G segments for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * a particular transaction are allocated in a physically contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * manner and are allocated below 4GB, the number of S/G segments is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * unrestricted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AHC_NSEG 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Per-SCB OSM storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct scb_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct ahc_linux_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dma_addr_t buf_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uint32_t xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) uint32_t sense_resid; /* Auto-Sense residual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Define a structure used for each host adapter. All members are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * aligned on a boundary >= the size of the member to honor the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * alignment restrictions of the various platforms supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct ahc_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Fields accessed from interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct scsi_target *starget[AHC_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spinlock_t spin_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u_int qfrozen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct completion *eh_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct Scsi_Host *host; /* pointer to scsi host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AHC_LINUX_NOIRQ ((uint32_t)~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uint32_t irq; /* IRQ for this adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint32_t bios_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) resource_size_t mem_busaddr; /* Mem Base Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void ahc_delay(long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /***************************** Low Level I/O **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uint8_t ahc_inb(struct ahc_softc * ahc, long port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void ahc_outb(struct ahc_softc * ahc, long port, uint8_t val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void ahc_outsb(struct ahc_softc * ahc, long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uint8_t *, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void ahc_insb(struct ahc_softc * ahc, long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) uint8_t *, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /**************************** Initialization **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ahc_linux_register_host(struct ahc_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct scsi_host_template *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /******************************** Locking *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Lock protecting internal data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ahc_lockinit(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_lock_init(&ahc->platform_data->spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ahc_lock(struct ahc_softc *ahc, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_lock_irqsave(&ahc->platform_data->spin_lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ahc_unlock(struct ahc_softc *ahc, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spin_unlock_irqrestore(&ahc->platform_data->spin_lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /******************************* PCI Definitions ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * PCIM_xxx: mask to locate subfield in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * PCIR_xxx: config register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * PCIC_xxx: device class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * PCIS_xxx: device subclass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * PCIP_xxx: device programming interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * PCID_xxx: device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PCIR_DEVVENDOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PCIR_VENDOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PCIR_DEVICE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PCIR_COMMAND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PCIM_CMD_PORTEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PCIM_CMD_MEMEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PCIM_CMD_BUSMASTEREN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PCIM_CMD_MWRICEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PCIM_CMD_PERRESPEN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PCIM_CMD_SERRESPEN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PCIR_STATUS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PCIR_REVID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PCIR_PROGIF 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PCIR_SUBCLASS 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PCIR_CLASS 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PCIR_CACHELNSZ 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PCIR_LATTIMER 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PCIR_HEADERTYPE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PCIM_MFDEV 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PCIR_BIST 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PCIR_CAP_PTR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* config registers for header type 0 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PCIR_MAPS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PCIR_SUBVEND_0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PCIR_SUBDEV_0 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) typedef enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) AHC_POWER_STATE_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AHC_POWER_STATE_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) AHC_POWER_STATE_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) AHC_POWER_STATE_D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } ahc_power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**************************** VL/EISA Routines ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int ahc_linux_eisa_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void ahc_linux_eisa_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int aic7770_map_registers(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u_int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int aic7770_map_int(struct ahc_softc *ahc, u_int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static inline int ahc_linux_eisa_init(void) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static inline void ahc_linux_eisa_exit(void) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /******************************* PCI Routines *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ahc_linux_pci_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void ahc_linux_pci_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ahc_pci_map_registers(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int ahc_pci_map_int(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint32_t ahc_pci_read_config(ahc_dev_softc_t pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int reg, int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void ahc_pci_write_config(ahc_dev_softc_t pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int reg, uint32_t value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline int ahc_get_pci_function(ahc_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ahc_get_pci_function(ahc_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return (PCI_FUNC(pci->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static inline int ahc_get_pci_slot(ahc_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ahc_get_pci_slot(ahc_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return (PCI_SLOT(pci->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static inline int ahc_get_pci_bus(ahc_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ahc_get_pci_bus(ahc_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return (pci->bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static inline int ahc_linux_pci_init(void) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline void ahc_linux_pci_exit(void) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static inline void ahc_flush_device_writes(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ahc_flush_device_writes(struct ahc_softc *ahc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* XXX Is this sufficient for all architectures??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ahc_inb(ahc, INTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /**************************** Proc FS Support *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int ahc_proc_write_seeprom(struct Scsi_Host *, char *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ahc_linux_show_info(struct seq_file *, struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*************************** Domain Validation ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*********************** Transaction Access Wrappers *************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static inline void ahc_cmd_set_transaction_status(struct scsi_cmnd *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline void ahc_set_transaction_status(struct scb *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static inline void ahc_cmd_set_scsi_status(struct scsi_cmnd *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static inline void ahc_set_scsi_status(struct scb *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline uint32_t ahc_cmd_get_transaction_status(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static inline uint32_t ahc_get_transaction_status(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline uint32_t ahc_cmd_get_scsi_status(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static inline uint32_t ahc_get_scsi_status(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static inline void ahc_set_transaction_tag(struct scb *, int, u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static inline u_long ahc_get_transfer_length(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static inline int ahc_get_transfer_dir(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static inline void ahc_set_residual(struct scb *, u_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static inline void ahc_set_sense_residual(struct scb *scb, u_long resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline u_long ahc_get_residual(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline u_long ahc_get_sense_residual(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static inline int ahc_perform_autosense(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static inline uint32_t ahc_get_sense_bufsize(struct ahc_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static inline void ahc_notify_xfer_settings_change(struct ahc_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ahc_devinfo *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static inline void ahc_platform_scb_free(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static inline void ahc_freeze_scb(struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void ahc_cmd_set_transaction_status(struct scsi_cmnd *cmd, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cmd->result &= ~(CAM_STATUS_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cmd->result |= status << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) void ahc_set_transaction_status(struct scb *scb, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ahc_cmd_set_transaction_status(scb->io_ctx,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) void ahc_cmd_set_scsi_status(struct scsi_cmnd *cmd, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cmd->result &= ~0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cmd->result |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) void ahc_set_scsi_status(struct scb *scb, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ahc_cmd_set_scsi_status(scb->io_ctx, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uint32_t ahc_cmd_get_transaction_status(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ((cmd->result >> 16) & CAM_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) uint32_t ahc_get_transaction_status(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return (ahc_cmd_get_transaction_status(scb->io_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) uint32_t ahc_cmd_get_scsi_status(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return (cmd->result & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) uint32_t ahc_get_scsi_status(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return (ahc_cmd_get_scsi_status(scb->io_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) void ahc_set_transaction_tag(struct scb *scb, int enabled, u_int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Nothing to do for linux as the incoming transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * has no concept of tag/non tagged, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u_long ahc_get_transfer_length(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return (scb->platform_data->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int ahc_get_transfer_dir(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return (scb->io_ctx->sc_data_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void ahc_set_residual(struct scb *scb, u_long resid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) scsi_set_resid(scb->io_ctx, resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) void ahc_set_sense_residual(struct scb *scb, u_long resid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) scb->platform_data->sense_resid = resid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u_long ahc_get_residual(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return scsi_get_resid(scb->io_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u_long ahc_get_sense_residual(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return (scb->platform_data->sense_resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ahc_perform_autosense(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * We always perform autosense in Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * On other platforms this is set on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * per-transaction basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ahc_get_sense_bufsize(struct ahc_softc *ahc, struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return (sizeof(struct scsi_sense_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ahc_notify_xfer_settings_change(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct ahc_devinfo *devinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Nothing to do here for linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ahc_platform_scb_free(struct ahc_softc *ahc, struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) void ahc_platform_free(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) void ahc_platform_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ahc_freeze_scb(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if ((scb->io_ctx->result & (CAM_DEV_QFRZN << 16)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) scb->io_ctx->result |= CAM_DEV_QFRZN << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) scb->platform_data->dev->qfrozen++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) void ahc_platform_set_tags(struct ahc_softc *ahc, struct scsi_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct ahc_devinfo *devinfo, ahc_queue_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int ahc_platform_abort_scbs(struct ahc_softc *ahc, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) char channel, int lun, u_int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) role_t role, uint32_t status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ahc_linux_isr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) void ahc_platform_flushwork(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) void ahc_done(struct ahc_softc*, struct scb*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) void ahc_send_async(struct ahc_softc *, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u_int target, u_int lun, ac_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) void ahc_print_path(struct ahc_softc *, struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define AHC_PCI_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define AHC_PCI_CONFIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define bootverbose aic7xxx_verbose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) extern u_int aic7xxx_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #endif /* _AIC7XXX_LINUX_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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