^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Interface for the 93C66/56/46/26/06 serial eeprom parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1995, 1996 Daniel M. Eischen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. The name of the author may not be used to endorse or promote products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * derived from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License ("GPL").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The instruction set of the 93C66/56/46/26/06 chips are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Start OP *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Function Bit Code Address** Data Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * -------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * READ 1 10 A5 - A0 Reads data stored in memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * starting at specified address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * EWEN 1 00 11XXXX Write enable must precede
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * all programming modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * WRITE 1 01 A5 - A0 D15 - D0 Writes register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * ERAL 1 00 10XXXX Erase all registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * WRAL 1 00 01XXXX D15 - D0 Writes to all registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * EWDS 1 00 00XXXX Disables all programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * *Note: A value of X for address is a don't care condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * **Note: There are 8 address bits for the 93C56/66 chips unlike
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * the 93C46/26/06 chips which have 6 address bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * The 93C46 has a four wire interface: clock, chip select, data in, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * data out. In order to perform one of the above functions, you need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * to enable the chip select for a clock period (typically a minimum of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 1 usec, with the clock high and low a minimum of 750 and 250 nsec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * respectively). While the chip select remains high, you can clock in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * the instructions (above) starting with the start bit, followed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * OP code, Address, and Data (if needed). For the READ instruction, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * requested 16-bit register contents is read from the data out line but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * is preceded by an initial zero (leading 0, followed by 16-bits, MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * first). The clock cycling from low to high initiates the next data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * bit to be sent from the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "aic7xxx_osm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "aic7xxx_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include "aic7xxx_93cx6.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Right now, we only have to read the SEEPROM. But we make it easier to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * add other 93Cx6 functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct seeprom_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) uint8_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) uint8_t bits[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Short opcodes for the c46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Long opcodes for the C56/C66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Common opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Wait for the SEERDY to go high; about 800 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLOCK_PULSE(sd, rdy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ; /* Do nothing */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (void)SEEPROM_INB(sd); /* Clear clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Send a START condition and the given command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) send_seeprom_cmd(struct seeprom_descriptor *sd, const struct seeprom_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) uint8_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Send chip select for one clock cycle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) temp = sd->sd_MS ^ sd->sd_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (i = 0; i < cmd->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (cmd->bits[i] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (cmd->bits[i] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Clear CS put the chip in the reset state, where it can wait for new commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reset_seeprom(struct seeprom_descriptor *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint8_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) temp = sd->sd_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Read the serial EEPROM and returns 1 if successful and 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * not successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u_int start_addr, u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u_int k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uint16_t v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint8_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Read the requested registers of the seeprom. The loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * will range from 0 to count-1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) for (k = start_addr; k < count + start_addr; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Now we're ready to send the read command followed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * address of the 16-bit register we want to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) send_seeprom_cmd(sd, &seeprom_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Send the 6 or 8 bit address (MSB first, LSB last). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) temp = sd->sd_MS ^ sd->sd_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = (sd->sd_chip - 1); i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if ((k & (1 << i)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if ((k & (1 << i)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Now read the 16 bit register. An initial 0 precedes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * register contents which begins with bit 15 (MSB) and ends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * with bit 0 (LSB). The initial 0 will be shifted off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * top of our word as we let the loop run from 0 to 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 16; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) v <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) v |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) buf[k - start_addr] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Reset the chip select for the next command cycle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) reset_seeprom(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef AHC_DUMP_EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) printk("\nSerial EEPROM:\n\t");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) for (k = 0; k < count; k = k + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (((k % 8) == 0) && (k != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) printk(KERN_CONT "\n\t");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) printk(KERN_CONT " 0x%x", buf[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Write the serial EEPROM and return 1 if successful and 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * not successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u_int start_addr, u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const struct seeprom_cmd *ewen, *ewds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint16_t v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uint8_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int i, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Place the chip into write-enable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (sd->sd_chip == C46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ewen = &seeprom_ewen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ewds = &seeprom_ewds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else if (sd->sd_chip == C56_66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ewen = &seeprom_long_ewen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ewds = &seeprom_long_ewds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) printk("ahc_write_seeprom: unsupported seeprom type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sd->sd_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) send_seeprom_cmd(sd, ewen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reset_seeprom(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Write all requested data out to the seeprom. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) temp = sd->sd_MS ^ sd->sd_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (k = start_addr; k < count + start_addr; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Send the write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) send_seeprom_cmd(sd, &seeprom_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Send the 6 or 8 bit address (MSB first). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = (sd->sd_chip - 1); i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if ((k & (1 << i)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if ((k & (1 << i)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Write the 16 bit value, MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) v = buf[k - start_addr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 15; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if ((v & (1 << i)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if ((v & (1 << i)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) temp ^= sd->sd_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Wait for the chip to complete the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) temp = sd->sd_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) temp = sd->sd_MS ^ sd->sd_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SEEPROM_OUTB(sd, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLOCK_PULSE(sd, sd->sd_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reset_seeprom(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Put the chip back into write-protect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) send_seeprom_cmd(sd, ewds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) reset_seeprom(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ahc_verify_cksum(struct seeprom_config *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int maxaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uint32_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint16_t *scarray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) maxaddr = (sizeof(*sc)/2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) scarray = (uint16_t *)sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < maxaddr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) checksum = checksum + scarray[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (checksum == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) || (checksum & 0xFFFF) != sc->checksum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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