^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Core definitions and data structures shareable across OS platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1994-2001 Justin T. Gibbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000-2001 Adaptec Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * $FreeBSD$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef _AIC7XXX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define _AIC7XXX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Register Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "aic7xxx_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /************************* Forward Declarations *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ahc_platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct scb_platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct seeprom_descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /****************************** Useful Macros *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifndef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifndef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ALL_CHANNELS '\0'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ALL_TARGETS_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INITIATOR_WILDCARD (~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCSIID_TARGET(ahc, scsiid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) >> TID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCSIID_OUR_ID(scsiid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ((scsiid) & OID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCSIID_CHANNEL(ahc, scsiid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((((ahc)->features & AHC_TWIN) != 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) : 'A')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCB_IS_SCSIBUS_B(ahc, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCB_GET_OUR_ID(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SCSIID_OUR_ID((scb)->hscb->scsiid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCB_GET_TARGET(ahc, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCB_GET_CHANNEL(ahc, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCB_GET_LUN(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ((scb)->hscb->lun & LID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCB_GET_TARGET_OFFSET(ahc, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SCB_GET_TARGET_MASK(ahc, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef AHC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCB_IS_SILENT(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) && (((scb)->flags & SCB_SILENT) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCB_IS_SILENT(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (((scb)->flags & SCB_SILENT) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TCL_TARGET_OFFSET(tcl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ((((tcl) >> 4) & TID) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TCL_LUN(tcl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (tcl & (AHC_NUM_LUNS - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BUILD_TCL(scsiid, lun) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ((lun) | (((scsiid) & TID) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifndef AHC_TARGET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #undef AHC_TMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AHC_TMODE_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**************************** Driver Constants ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The maximum number of supported targets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AHC_NUM_TARGETS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The maximum number of supported luns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * The identify message only supports 64 luns in SPI3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * You can have 2^64 luns when information unit transfers are enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * but it is doubtful this driver will ever support IUTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AHC_NUM_LUNS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The maximum transfer per S/G segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * The maximum amount of SCB storage in hardware on a controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * This value represents an upper bound. Controllers vary in the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * they actually support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AHC_SCB_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * The maximum number of concurrent transactions supported per driver instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Sequencer Control Blocks (SCBs) store per-transaction information. Although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * the space for SCBs on the host adapter varies by model, the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * page the SCBs between host and controller memory as needed. We are limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * to 253 because:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * 2) We reserve one value, 255, to represent the invalid element.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 3) Our input queue scheme requires one SCB to always be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * in advance of queuing any SCBs. This takes us down to 254.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 4) To handle our output queue correctly on machines that only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * support 32bit stores, we must clear the array 4 bytes at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * time. To avoid colliding with a DMA write from the sequencer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * we must be sure that 4 slots are empty when we write to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the queue. This reduces us to 253 SCBs: 1 that just completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * and the known three additional empty slots in the queue that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * precede it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AHC_MAX_QUEUE 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The maximum amount of SCB storage we allocate in host memory. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * number should reflect the 1 additional SCB we require to handle our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * qinfifo mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Ring Buffer of incoming target commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * We allocate 256 to simplify the logic in the sequencer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * by using the natural wrap point of an 8bit counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AHC_TMODE_CMDS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Reset line assertion time in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AHC_BUSRESET_DELAY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /******************* Chip Characteristics/Operating Settings *****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Chip Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * The chip order is from least sophisticated to most sophisticated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) AHC_NONE = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AHC_CHIPID_MASK = 0x00FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) AHC_AIC7770 = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) AHC_AIC7850 = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) AHC_AIC7855 = 0x0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) AHC_AIC7859 = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) AHC_AIC7860 = 0x0005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) AHC_AIC7870 = 0x0006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) AHC_AIC7880 = 0x0007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) AHC_AIC7895 = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) AHC_AIC7895C = 0x0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) AHC_AIC7890 = 0x000a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) AHC_AIC7896 = 0x000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) AHC_AIC7892 = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) AHC_AIC7899 = 0x000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) AHC_VL = 0x0100, /* Bus type VL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) AHC_EISA = 0x0200, /* Bus type EISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) AHC_PCI = 0x0400, /* Bus type PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) AHC_BUS_MASK = 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } ahc_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Features available in each chip type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) AHC_FENONE = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) AHC_WIDE = 0x00004, /* Wide Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) AHC_TWIN = 0x00008, /* Twin Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AHC_DT = 0x00800, /* Double Transition transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AHC_HVD = 0x100000, /* HVD rather than SE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) AHC_AIC7770_FE = AHC_FENONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * The real 7850 does not support Ultra modes, but there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * several cards that use the generic 7850 PCI ID even though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * they are using an Ultra capable chip (7859/7860). We start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * out with the AHC_ULTRA feature set and then check the DEVSTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * register to determine if the capability is really present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) AHC_AIC7860_FE = AHC_AIC7850_FE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Although we have space for both the initiator and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * target roles on ULTRA2 chips, we currently disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * the initiator role to allow multi-scsi-id target mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * configurations. We can only respond on the same SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * ID as our initiator role if we allow initiator operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * At some point, we should add a configuration knob to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * allow both roles to be loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) |AHC_TARGETMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } ahc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Bugs in the silicon that we work around in software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) AHC_BUGNONE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * On all chips prior to the U2 product line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * the WIDEODD S/G segment feature does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * work during scsi->HostBus transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) AHC_TMODE_WIDEODD_BUG = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * On the aic7890/91 Rev 0 chips, the autoflush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * feature does not work. A manual flush of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * the DMA FIFO is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) AHC_AUTOFLUSH_BUG = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * On many chips, cacheline streaming does not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) AHC_CACHETHEN_BUG = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * On the aic7896/97 chips, cacheline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * streaming must be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) AHC_CACHETHEN_DIS_BUG = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * PCI 2.1 Retry failure on non-empty data fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) AHC_PCI_2_1_RETRY_BUG = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Controller does not handle cacheline residuals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * properly on S/G segments if PCI MWI instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * are allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) AHC_PCI_MWI_BUG = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * An SCB upload using the SCB channel's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * auto array entry copy feature may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * corrupt data. This appears to only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * occur on 66MHz systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) AHC_SCBCHAN_UPLOAD_BUG = 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } ahc_bug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Configuration specific settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * The driver determines these settings by probing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * chip/controller's configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) AHC_FNONE = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) AHC_PRIMARY_CHANNEL = 0x003, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * The channel that should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * be probed first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) AHC_USEDEFAULTS = 0x004, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * For cards without an seeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * or a BIOS to initialize the chip's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * SRAM, we use the default target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) AHC_SEQUENCER_DEBUG = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) AHC_SHARED_SRAM = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AHC_RESET_BUS_A = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) AHC_RESET_BUS_B = 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) AHC_EXTENDED_TRANS_A = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) AHC_EXTENDED_TRANS_B = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) AHC_TERM_ENB_A = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) AHC_TERM_ENB_B = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) AHC_INITIATORROLE = 0x1000, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Allow initiator operations on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) AHC_TARGETROLE = 0x2000, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Allow target operations on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) AHC_NEWEEPROM_FMT = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) AHC_INT50_SPEEDFLEX = 0x20000, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Internal 50pin connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * sits behind an aic3860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) AHC_SCB_BTT = 0x40000, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * The busy targets table is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * stored in SCB space rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * than SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AHC_BIOS_ENABLED = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) AHC_ALL_INTERRUPTS = 0x100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) AHC_DISABLE_PCI_PERR = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) AHC_HAS_TERM_LOGIC = 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } ahc_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /************************* Hardware SCB Definition ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * consists of a "hardware SCB" mirroring the fields available on the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * and additional information the kernel stores for each transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * To minimize space utilization, a portion of the hardware scb stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * different data during different portions of a SCSI transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * As initialized by the host driver for the initiator role, this area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * the cdb has been presented to the target, this area serves to store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * residual transfer information and the SCSI status byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * For the target role, the contents of this area do not change, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * still serve a different purpose than for the initiator role. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * struct target_data for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Status information embedded in the shared poriton of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * an SCB after passing the cdb to the target. The kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * driver will only read this data for transactions that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * complete abnormally (non-zero status byte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct status_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uint32_t residual_datacnt; /* Residual in the current S/G seg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uint32_t residual_sg_ptr; /* The next S/G for this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint8_t scsi_status; /* Standard SCSI status byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Target mode version of the shared data SCB segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct target_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint32_t residual_datacnt; /* Residual in the current S/G seg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint32_t residual_sg_ptr; /* The next S/G for this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint8_t scsi_status; /* SCSI status to give to initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) uint8_t target_phases; /* Bitmap of phases to execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) uint8_t data_phase; /* Data-In or Data-Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint8_t initiator_tag; /* Initiator's transaction tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct hardware_scb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*0*/ union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * If the cdb is 12 bytes or less, we embed it directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * in the SCB. For longer cdbs, we embed the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * of the cdb payload as seen by the chip and a DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * is used to pull it in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) uint8_t cdb[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uint32_t cdb_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct status_pkt status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct target_data tdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } shared_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * A word about residuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * The scb is presented to the sequencer with the dataptr and datacnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * fields initialized to the contents of the first S/G element to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * transfer. The sgptr field is initialized to the bus address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * the S/G element that follows the first in the in core S/G array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * S/G entry for this transfer (single S/G element transfer with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * first elements address and length preloaded in the dataptr/datacnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * The SG_FULL_RESID flag ensures that the residual will be correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * noted even if no data transfers occur. Once the data phase is entered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * the residual sgptr and datacnt are loaded from the sgptr and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * datacnt fields. After each S/G element's dataptr and length are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * loaded into the hardware, the residual sgptr is advanced. After
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * each S/G element is expired, its datacnt field is checked to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * residual sg ptr and the transfer is considered complete. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * sequencer determines that there is a residual in the tranfer, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * will set the SG_RESID_VALID flag in sgptr and dma the scb back into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * host memory. To sumarize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Sequencer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * o A residual has occurred if SG_FULL_RESID is set in sgptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * or residual_sgptr does not have SG_LIST_NULL set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * o We are transferring the last segment if residual_datacnt has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * the SG_LAST_SEG flag set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * o A residual has occurred if a completed scb has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * SG_RESID_VALID flag set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * o residual_sgptr and sgptr refer to the "next" sg entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * and so may point beyond the last valid sg entry for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*12*/ uint32_t dataptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*16*/ uint32_t datacnt; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Byte 3 (numbered from 0) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * the datacnt is really the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * 4th byte in that data address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*20*/ uint32_t sgptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SG_PTR_MASK 0xFFFFFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*26*/ uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*27*/ uint8_t tag; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Index into our kernel SCB array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Also used as the tag for tagged I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*28*/ uint8_t cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*31*/ uint8_t next; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Used for threading SCBs in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * "Waiting for Selection" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * "Disconnected SCB" lists down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * in the sequencer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*32*/ uint8_t cdb32[32]; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * CDB storage for cdbs of size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * 13->32. We store them here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * because hardware scbs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * allocated from DMA safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * memory so we are guaranteed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * the controller can access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * this data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /************************ Kernel SCB Definitions ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Some fields of the SCB are OS dependent. Here we collect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * definitions for elements that all OS platforms need to include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * in there SCB definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Definition of a scatter/gather element as transferred to the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * The aic7xxx chips only support a 24bit length. We use the top byte of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * the length to store additional address bits and a flag to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * that a given segment terminates the transfer. This gives us an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * addressable range of 512GB on machines with 64bit PCI or with chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * that can support dual address cycles on 32bit PCI busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct ahc_dma_seg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint32_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define AHC_DMA_LAST_SEG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define AHC_SG_LEN_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct sg_map_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bus_dmamap_t sg_dmamap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dma_addr_t sg_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct ahc_dma_seg* sg_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SLIST_ENTRY(sg_map_node) links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * The current state of this SCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SCB_FREE = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SCB_OTHERTCL_TIMEOUT = 0x0002,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Another device was active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * during the first timeout for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * this SCB so we gave ourselves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * an additional timeout period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * in case it was hogging the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) SCB_DEVICE_RESET = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) SCB_SENSE = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SCB_CDB32_PTR = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SCB_RECOVERY_SCB = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SCB_ABORT = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) SCB_UNTAGGEDQ = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SCB_ACTIVE = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SCB_TARGET_IMMEDIATE = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SCB_TRANSMISSION_ERROR = 0x1000,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * We detected a parity or CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * error that has effected the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * payload of the command. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * flag is checked when normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * status is returned to catch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * the case of a target not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * responding to our attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * to report the error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SCB_TARGET_SCB = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SCB_SILENT = 0x4000 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * Be quiet about transmission type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * errors. They are expected and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * don't want to upset the user. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * flag is typically used during DV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } scb_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct scb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct hardware_scb *hscb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SLIST_ENTRY(scb) sle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TAILQ_ENTRY(scb) tqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) } links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) LIST_ENTRY(scb) pending_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ahc_io_ctx_t io_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct ahc_softc *ahc_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) scb_flag flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct scb_platform_data *platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct sg_map_node *sg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ahc_dma_seg *sg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dma_addr_t sg_list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u_int sg_count;/* How full ahc_dma_seg is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct scb_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SLIST_HEAD(, scb) free_scbs; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * Pool of SCBs ready to be assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * commands to execute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct scb *scbindex[256]; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Mapping from tag to SCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * As tag identifiers are an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * 8bit value, we provide space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * for all possible tag values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Any lookups to entries at or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * above AHC_SCB_MAX_ALLOC will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * always fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct hardware_scb *hscbs; /* Array of hardware SCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct scb *scbarray; /* Array of kernel SCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct scsi_sense_data *sense; /* Per SCB sense data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * "Bus" addresses of our data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bus_dmamap_t hscb_dmamap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dma_addr_t hscb_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) bus_dma_tag_t sense_dmat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) bus_dmamap_t sense_dmamap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dma_addr_t sense_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SLIST_HEAD(, sg_map_node) sg_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) uint8_t numscbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) uint8_t maxhscbs; /* Number of SCBs on the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) uint8_t init_level; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * How far we've initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /************************ Target Mode Definitions *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Connection descriptor for select-in requests in target mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct target_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uint8_t scsiid; /* Our ID and the initiator's ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) uint8_t identify; /* Identify message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) uint8_t bytes[22]; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Bytes contains any additional message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * bytes terminated by 0xFF. The remainder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * is the cdb to execute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uint8_t cmd_valid; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * When a command is complete, the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * will set cmd_valid to all bits set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * After the host has seen the command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * the bits are cleared. This allows us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * to just peek at host memory to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * if more work is complete. cmd_valid is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * an 8 byte boundary to simplify setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * it on aic7880 hardware which only has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * limited direct access to the DMA FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) uint8_t pad[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * Number of events we can buffer up if we run out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * of immediate notify ccbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define AHC_TMODE_EVENT_BUFFER_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct ahc_tmode_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define EVENT_TYPE_BUS_RESET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) uint8_t event_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Per enabled lun target mode state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * As this state is directly influenced by the host OS'es target mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * environment, we let the OS module define it. Forward declare the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * structure here so we can store arrays of them, etc. in OS neutral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #ifdef AHC_TARGET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct ahc_tmode_lstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct cam_path *path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct ccb_hdr_slist accept_tios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct ccb_hdr_slist immed_notifies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint8_t event_r_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint8_t event_w_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct ahc_tmode_lstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /******************** Transfer Negotiation Datastructures *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define AHC_WIDTH_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define AHC_PERIOD_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define AHC_OFFSET_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define AHC_PPR_OPTS_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * Transfer Negotiation Information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct ahc_transinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) uint8_t protocol_version; /* SCSI Revision level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) uint8_t transport_version; /* SPI Revision level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uint8_t width; /* Bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) uint8_t period; /* Sync rate factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uint8_t offset; /* Sync offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uint8_t ppr_options; /* Parallel Protocol Request options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * Per-initiator current, goal and user transfer negotiation information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct ahc_initiator_tinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint8_t scsirate; /* Computed value for SCSIRATE reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct ahc_transinfo curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct ahc_transinfo goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct ahc_transinfo user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Per enabled target ID state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Pointers to lun target state as well as sync/wide negotiation information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * for each initiator<->target mapping. For the initiator role we pretend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * that we are the target and the targets are the initiators since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * negotiation is the same regardless of role.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct ahc_tmode_tstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Per initiator state bitmasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) uint16_t auto_negotiate;/* Auto Negotiation Required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) uint16_t ultraenb; /* Using ultra sync rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) uint16_t discenable; /* Disconnection allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) uint16_t tagenable; /* Tagged Queuing allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * Data structure for our table of allowed synchronous transfer rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct ahc_syncrate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define ST_SXFR 0x010 /* Rate Single Transition Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define DT_SXFR 0x040 /* Rate Double Transition Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) uint8_t period; /* Period to send to SCSI target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) const char *rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Safe and valid period for async negotiations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define AHC_ASYNC_XFER_PERIOD 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define AHC_ULTRA2_XFER_PERIOD 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Indexes into our table of syncronous transfer rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define AHC_SYNCRATE_DT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define AHC_SYNCRATE_ULTRA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define AHC_SYNCRATE_ULTRA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define AHC_SYNCRATE_FAST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define AHC_SYNCRATE_MIN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /***************************** Lookup Tables **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Phase -> name and message out response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * to parity errors in each phase table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct ahc_phase_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) uint8_t phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint8_t mesg_out; /* Message response to parity errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) char *phasemsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /************************** Serial EEPROM Format ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct seeprom_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Per SCSI ID Configuration Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) uint16_t device_flags[16]; /* words 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define CFXFER 0x0007 /* synchronous transfer rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define CFSYNCH 0x0008 /* enable synchronous transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define CFDISC 0x0010 /* enable disconnection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define CFWIDEB 0x0020 /* wide bus device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define CFSTART 0x0100 /* send start unit SCSI command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define CFINCBIOS 0x0200 /* include in BIOS scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define CFRNFOUND 0x0400 /* report even if not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * BIOS Control Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint16_t bios_control; /* word 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define CFSUPREM 0x0001 /* support all removeable drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define CFSUPREMB 0x0002 /* support removeable boot drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define CFBIOSEN 0x0004 /* BIOS enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define CFSM2DRV 0x0010 /* support more than two drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define CFSTPWLEVEL 0x0010 /* Termination level control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define CFEXTEND 0x0080 /* extended translation enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define CFSCAMEN 0x0100 /* SCAM enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define CFMSG_VERBOSE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define CFMSG_SILENT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define CFMSG_DIAG 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* UNUSED 0xff00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * Host Adapter Control Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) uint16_t adapter_control; /* word 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define CFAUTOTERM 0x0001 /* Perform Auto termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define CFSTERM 0x0004 /* SCSI low byte termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define CFWSTERM 0x0008 /* SCSI high byte termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define CFSPARITY 0x0010 /* SCSI parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define CFMULTILUN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define CFRESETB 0x0040 /* reset SCSI bus at boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define CFCLUSTERENB 0x0080 /* Cluster Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define CFBOOTCHAN 0x0300 /* probe this channel first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define CFBOOTCHANSHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * Bus Release Time, Host Adapter ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) uint16_t brtime_id; /* word 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define CFSCSIID 0x000f /* host adapter SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* UNUSED 0x00f0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define CFBRTIME 0xff00 /* bus release time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * Maximum targets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uint16_t max_targets; /* word 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define CFMAXTARG 0x00ff /* maximum targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define CFBOOTLUN 0x0f00 /* Lun to boot from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define CFBOOTID 0xf000 /* Target to boot from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint16_t res_1[10]; /* words 20-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint16_t signature; /* Signature == 0x250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define CFSIGNATURE 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define CFSIGNATURE2 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) uint16_t checksum; /* word 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /**************************** Message Buffer *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MSG_TYPE_NONE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MSG_TYPE_INITIATOR_MSGOUT = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MSG_TYPE_INITIATOR_MSGIN = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MSG_TYPE_TARGET_MSGOUT = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MSG_TYPE_TARGET_MSGIN = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } ahc_msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MSGLOOP_IN_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) MSGLOOP_MSGCOMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) MSGLOOP_TERMINATED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) } msg_loop_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*********************** Software Configuration Structure *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) TAILQ_HEAD(scb_tailq, scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct ahc_aic7770_softc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * Saved register state used for chip_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) uint8_t busspd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint8_t bustime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct ahc_pci_softc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Saved register state used for chip_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) uint16_t targcrccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint8_t command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint8_t csize_lattime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint8_t optionmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uint8_t crccontrol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uint8_t dscommand0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint8_t dspcistatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) uint8_t scbbaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) uint8_t dff_thrsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) union ahc_bus_softc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct ahc_aic7770_softc aic7770_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct ahc_pci_softc pci_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) typedef int (*ahc_bus_suspend_t)(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) typedef int (*ahc_bus_resume_t)(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) typedef void ahc_callback_t (void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct ahc_softc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) bus_space_tag_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) bus_space_handle_t bsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct scb_data *scb_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct scb *next_queued_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * SCBs that have been sent to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) BSD_LIST_HEAD(, scb) pending_scbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * Counting lock for deferring the release of additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * untagged transactions from the untagged_queues. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * the lock is decremented to 0, all queues in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * untagged_queues array are run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u_int untagged_queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Per-target queue of untagged-transactions. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * transaction at the head of the queue is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * currently pending untagged transaction for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * target. The driver only allows a single untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * transaction per target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Bus attachment specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) union ahc_bus_softc bus_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * Platform specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct ahc_platform_data *platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * Platform specific device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ahc_dev_softc_t dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * Bus specific device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ahc_bus_intr_t bus_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Bus specific initialization required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * after a chip reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ahc_bus_chip_init_t bus_chip_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * Target mode related state kept on a per enabled lun basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * Targets that are not enabled will have null entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * As an initiator, we keep one target entry for our initiator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * ID to store our sync/wide transfer settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * The black hole device responsible for handling requests for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * disabled luns on enabled targets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct ahc_tmode_lstate *black_hole;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * Device instance currently on the bus awaiting a continue TIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * for a command that was not given the disconnect priveledge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct ahc_tmode_lstate *pending_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Card characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ahc_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ahc_feature features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ahc_bug bugs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ahc_flag flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct seeprom_config *seep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* Values to store in the SEQCTL register for pause and unpause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uint8_t unpause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) uint8_t pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Command Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) uint8_t qoutfifonext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uint8_t qinfifonext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) uint8_t *qoutfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint8_t *qinfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Critical Section Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct cs *critical_sections;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u_int num_critical_sections;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Channel Names ('A', 'B', etc.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) char channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) char channel_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Initiator Bus ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint8_t our_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint8_t our_id_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * PCI error detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int unsolicited_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Target incoming command FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct target_cmd *targetcmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) uint8_t tqinfifonext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * Cached copy of the sequencer control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) uint8_t seqctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Incoming and outgoing message handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) uint8_t send_msg_perror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ahc_msg_type msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) uint8_t msgout_buf[12];/* Message we are sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) uint8_t msgin_buf[12];/* Message we are receiving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) u_int msgout_len; /* Length of message to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) u_int msgout_index; /* Current index in msgout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u_int msgin_index; /* Current index in msgin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * Mapping information for data structures shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * between the sequencer and kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) bus_dma_tag_t parent_dmat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) bus_dma_tag_t shared_data_dmat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) bus_dmamap_t shared_data_dmamap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dma_addr_t shared_data_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * Bus address of the one byte buffer used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * work-around a DMA bug for chips <= aic7880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * in target mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dma_addr_t dma_bug_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Number of enabled target mode device on this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u_int enabled_luns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Initialization level of this data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u_int init_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* PCI cacheline size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u_int pci_cachesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * Count of parity errors we have seen as a target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * We auto-disable parity error checking after seeing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * AHC_PCI_TARGET_PERR_THRESH number of errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u_int pci_target_perr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define AHC_PCI_TARGET_PERR_THRESH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Maximum number of sequencer instructions supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u_int instruction_ram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Per-Unit descriptive information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) const char *description;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Selection Timer settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int seltime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int seltime_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) uint16_t user_discenable;/* Disconnection allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) uint16_t user_tagenable;/* Tagged Queuing allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /************************ Active Device Information ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ROLE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ROLE_INITIATOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ROLE_TARGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) } role_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct ahc_devinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int our_scsiid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int target_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) uint16_t target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u_int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u_int lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) char channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) role_t role; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * Only guaranteed to be correct if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * in the busfree state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /****************************** PCI Structures ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) typedef int (ahc_device_setup_t)(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct ahc_pci_identity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) uint64_t full_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) uint64_t id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ahc_device_setup_t *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /***************************** VL/EISA Declarations ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct aic7770_identity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) uint32_t full_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) uint32_t id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ahc_device_setup_t *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) extern struct aic7770_identity aic7770_ident_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) extern const int ahc_num_aic7770_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define AHC_EISA_SLOT_OFFSET 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define AHC_EISA_IOSIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /*************************** Function Declarations ****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /***************************** PCI Front End *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) const struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int ahc_pci_config(struct ahc_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) const struct ahc_pci_identity *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int ahc_pci_test_register_access(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) void ahc_pci_resume(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*************************** EISA/VL Front End ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct aic7770_identity *aic7770_find_device(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int aic7770_config(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct aic7770_identity *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u_int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /************************** SCB and SCB queue management **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int ahc_probe_scbs(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int target, char channel, int lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u_int tag, role_t role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /****************************** Initialization ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct ahc_softc *ahc_alloc(void *platform_arg, char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int ahc_softc_init(struct ahc_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) void ahc_controller_info(struct ahc_softc *ahc, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int ahc_chip_init(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int ahc_init(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) void ahc_intr_enable(struct ahc_softc *ahc, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) void ahc_pause_and_flushwork(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int ahc_suspend(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int ahc_resume(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) void ahc_set_unit(struct ahc_softc *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) void ahc_set_name(struct ahc_softc *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) void ahc_free(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int ahc_reset(struct ahc_softc *ahc, int reinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /***************************** Error Recovery *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) SEARCH_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SEARCH_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SEARCH_REMOVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) } ahc_search_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int ahc_search_qinfifo(struct ahc_softc *ahc, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) char channel, int lun, u_int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) role_t role, uint32_t status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ahc_search_action action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int ahc_search_untagged_queues(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ahc_io_ctx_t ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) int target, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int lun, uint32_t status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ahc_search_action action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int ahc_search_disc_list(struct ahc_softc *ahc, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) char channel, int lun, u_int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int stop_on_first, int remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) int save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int ahc_reset_channel(struct ahc_softc *ahc, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int initiate_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /*************************** Utility Functions ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u_int our_id, u_int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) u_int lun, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) role_t role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /************************** Transfer Negotiation ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) const struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) u_int *ppr_options, u_int maxsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u_int ahc_find_period(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) u_int scsirate, u_int maxsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * Negotiation types. These are used to qualify if we should renegotiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * even if our goal and current transport parameters are identical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) } ahc_neg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int ahc_update_neg_request(struct ahc_softc*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct ahc_devinfo*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct ahc_tmode_tstate*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct ahc_initiator_tinfo*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ahc_neg_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) void ahc_set_width(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct ahc_devinfo *devinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) u_int width, u_int type, int paused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) void ahc_set_syncrate(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct ahc_devinfo *devinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) const struct ahc_syncrate *syncrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) u_int period, u_int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) u_int ppr_options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u_int type, int paused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) AHC_QUEUE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) AHC_QUEUE_BASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) AHC_QUEUE_TAGGED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) } ahc_queue_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /**************************** Target Mode *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #ifdef AHC_TARGET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) void ahc_send_lstate_events(struct ahc_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct ahc_tmode_lstate *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) void ahc_handle_en_lun(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct cam_sim *sim, union ccb *ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) cam_status ahc_find_tmode_devs(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct cam_sim *sim, union ccb *ccb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct ahc_tmode_tstate **tstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct ahc_tmode_lstate **lstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) int notfound_failure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #ifndef AHC_TMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define AHC_TMODE_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /******************************* Debug ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #ifdef AHC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) extern uint32_t ahc_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define AHC_SHOW_MISC 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define AHC_SHOW_SENSE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define AHC_DUMP_SEEPROM 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define AHC_SHOW_TERMCTL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define AHC_SHOW_MEMORY 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define AHC_SHOW_MESSAGES 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define AHC_SHOW_DV 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define AHC_SHOW_SELTO 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define AHC_SHOW_QFULL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define AHC_SHOW_QUEUE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define AHC_SHOW_TQIN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define AHC_SHOW_MASKED_ERRORS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define AHC_DEBUG_SEQUENCER 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) void ahc_print_devinfo(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct ahc_devinfo *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) void ahc_dump_card_state(struct ahc_softc *ahc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int ahc_print_register(const ahc_reg_parse_entry_t *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u_int num_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) u_int address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u_int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u_int *cur_column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u_int wrap_point);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /******************************* SEEPROM *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int ahc_acquire_seeprom(struct ahc_softc *ahc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct seeprom_descriptor *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) void ahc_release_seeprom(struct seeprom_descriptor *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #endif /* _AIC7XXX_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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