^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Product specific probe and attach routines for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * aic7901 and aic7902 SCSI controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 1994-2001 Justin T. Gibbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2000-2002 Adaptec Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "aic79xx_osm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "aic79xx_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "aic79xx_pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline uint64_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint64_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) id = subvendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) | (subdevice << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) | ((uint64_t)vendor << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) | ((uint64_t)device << 48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return (id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ID_AIC7902_PCI_REV_A4 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ID_AIC7902_PCI_REV_B0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SUBID_HP 0x0E11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DEVID_9005_TYPE(id) ((id) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DEVID_9005_MFUNC(id) ((id) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUBID_9005_TYPE(id) ((id) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SUBID_9005_SEEPTYPE_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUBID_9005_SEEPTYPE_4K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static ahd_device_setup_t ahd_aic7901_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static ahd_device_setup_t ahd_aic7901A_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static ahd_device_setup_t ahd_aic7902_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static ahd_device_setup_t ahd_aic790X_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct ahd_pci_identity ahd_pci_ident_table[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* aic7901 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ID_AHA_29320A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "Adaptec 29320A Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ahd_aic7901_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ID_AHA_29320ALP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "Adaptec 29320ALP PCIx Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ahd_aic7901_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ID_AHA_29320LPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "Adaptec 29320LPE PCIe Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ahd_aic7901_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* aic7901A based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ID_AHA_29320LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "Adaptec 29320LP Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ahd_aic7901A_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* aic7902 based controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ID_AHA_29320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "Adaptec 29320 Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ID_AHA_29320B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "Adaptec 29320B Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ID_AHA_39320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "Adaptec 39320 Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ID_AHA_39320_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "Adaptec 39320 Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ID_AHA_39320_B_DELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ID_AHA_39320A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "Adaptec 39320A Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ID_AHA_39320D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "Adaptec 39320D Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ID_AHA_39320D_HP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ID_AHA_39320D_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "Adaptec 39320D Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ID_AHA_39320D_B_HP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ID_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Generic chip probes for devices we don't know 'exactly' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ID_AIC7901 & ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "Adaptec AIC7901 Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ahd_aic7901_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ID_AIC7901A & ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ID_DEV_VENDOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "Adaptec AIC7901A Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ahd_aic7901A_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ID_AIC7902 & ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ID_9005_GENERIC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Adaptec AIC7902 Ultra320 SCSI adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ahd_aic7902_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DEVCONFIG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PCIXINITPAT 0x0000E000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCIXINIT_PCI33_66 0x0000E000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCIXINIT_PCIX50_66 0x0000C000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCIXINIT_PCIX66_100 0x0000A000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCIXINIT_PCIX100_133 0x00008000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCI_BUS_MODES_INDEX(devconfig) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (((devconfig) & PCIXINITPAT) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const char *pci_bus_modes[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "PCI bus mode unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "PCI bus mode unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "PCI bus mode unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "PCI bus mode unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "PCI-X 101-133MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "PCI-X 67-100MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "PCI-X 50-66MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "PCI 33 or 66MHz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TESTMODE 0x00000800ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IRDY_RST 0x00000200ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FRAME_RST 0x00000100ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PCI64BIT 0x00000080ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MRDCEN 0x00000040ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ENDIANSEL 0x00000020ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MIXQWENDIANEN 0x00000008ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DACEN 0x00000004ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define STPWLEVEL 0x00000002ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define QWENDIANSEL 0x00000001ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DEVCONFIG1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PREQDIS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CSIZE_LATTIME 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CACHESIZE 0x000000fful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define LATTIME 0x0000ff00ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int ahd_check_extport(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void ahd_configure_termination(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u_int adapter_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void ahd_pci_intr(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct ahd_pci_identity *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ahd_find_pci_device(ahd_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint64_t full_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint16_t device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) uint16_t vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uint16_t subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uint16_t subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const struct ahd_pci_identity *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u_int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) full_id = ahd_compose_id(device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) subdevice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) subvendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Controllers, mask out the IROC/HostRAID bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) full_id &= ID_ALL_IROC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (i = 0; i < ahd_num_pci_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) entry = &ahd_pci_ident_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (entry->full_id == (full_id & entry->id_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Honor exclusion entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (entry->name == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return (entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u_int command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint16_t subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ahd->description = entry->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Record if this is an HP board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) subvendor = ahd_pci_read_config(ahd->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PCIR_SUBVEND_0, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (subvendor == SUBID_HP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ahd->flags |= AHD_HP_BOARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) error = entry->setup(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ahd->chip |= AHD_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Disable PCIX workarounds when running in PCI mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ahd->bugs &= ~AHD_PCIX_BUG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ahd->chip |= AHD_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) error = ahd_pci_map_registers(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * If we need to support high memory, enable dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * address cycles. This bit must be set to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * high address bit generation even if we are on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 64bit bus (PCI64BIT set in devconfig).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) printk("%s: Enabling 39Bit Addressing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) devconfig = ahd_pci_read_config(ahd->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) devconfig |= DACEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Ensure busmastering is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) command |= PCIM_CMD_BUSMASTEREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) error = ahd_softc_init(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ahd->bus_intr = ahd_pci_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) error = ahd_reset(ahd, /*reinit*/FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return (ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ahd->pci_cachesize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*bytes*/1) & CACHESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ahd->pci_cachesize *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* See if we have a SEEPROM and perform auto-term */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) error = ahd_check_extport(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Core initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) error = ahd_init(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ahd->init_level++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Allow interrupts now that we are completely setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ahd_pci_map_int(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ahd_pci_suspend(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Save chip register configuration data for chip resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * that occur during runtime and resume events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ahd->suspend_state.pci_state.devconfig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ahd->suspend_state.pci_state.command =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ahd->suspend_state.pci_state.csize_lattime =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ahd_pci_resume(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ahd->suspend_state.pci_state.devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ahd->suspend_state.pci_state.command, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ahd_pci_write_config(ahd->dev_softc, CSIZE_LATTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ahd->suspend_state.pci_state.csize_lattime, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Perform some simple tests that should catch situations where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * our registers are invalidly mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ahd_pci_test_register_access(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uint32_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u_int targpcistat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u_int pci_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) uint8_t hcntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) error = EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Enable PCI error interrupt status, but suppress NMIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * generated by SERR raised due to target aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * First a simple test to see if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * registers can be read. Reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * HCNTRL has no side effects and has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * at least one bit that is guaranteed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * be zero so it is a good register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * use for this test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hcntrl = ahd_inb(ahd, HCNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (hcntrl == 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Next create a situation where write combining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * or read prefetching could be initiated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * CPU or host bridge. Our device does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * either, so look for data corruption and/or flaged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * PCI errors. First pause without causing another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * chip reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hcntrl &= ~CHIPRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) while (ahd_is_paused(ahd) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Clear any PCI errors that occurred before our driver attached. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) targpcistat = ahd_inb(ahd, TARGPCISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ahd_outb(ahd, TARGPCISTAT, targpcistat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pci_status1 = ahd_pci_read_config(ahd->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_status1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ahd_outb(ahd, CLRINT, CLRPCIINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ahd_outb(ahd, SEQCTL0, PERRORDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) targpcistat = ahd_inb(ahd, TARGPCISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if ((targpcistat & STA) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) targpcistat = ahd_inb(ahd, TARGPCISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Silently clear any latched errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ahd_outb(ahd, TARGPCISTAT, targpcistat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pci_status1 = ahd_pci_read_config(ahd->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_status1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ahd_outb(ahd, CLRINT, CLRPCIINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Check the external port logic for a serial eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * and termination/cable detection contrls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ahd_check_extport(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct vpd_config vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct seeprom_config *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u_int adapter_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int have_seeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sc = ahd->seep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) have_seeprom = ahd_acquire_seeprom(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u_int start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * Fetch VPD for this function and parse it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) printk("%s: Reading VPD from SEEPROM...",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Address is always in units of 16bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) start_addr = ((2 * sizeof(*sc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) start_addr, sizeof(vpd)/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*bytestream*/TRUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) error = ahd_parse_vpddata(ahd, &vpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) printk("%s: VPD parsing %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ahd_name(ahd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) error == 0 ? "successful" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) printk("%s: Reading SEEPROM...", ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Address is always in units of 16bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) error = ahd_read_seeprom(ahd, (uint16_t *)sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) start_addr, sizeof(*sc)/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*bytestream*/FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (error != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) printk("Unable to read SEEPROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) have_seeprom = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) have_seeprom = ahd_verify_cksum(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (bootverbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (have_seeprom == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) printk ("checksum error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) printk ("done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ahd_release_seeprom(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u_int nvram_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * Pull scratch ram settings and treat them as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * if they are the contents of an seeprom if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * the 'ADPT', 'BIOS', or 'ASPI' signature is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * in SCB 0xFF. We manually compose the data as 16bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * values to avoid endian issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ahd_set_scbptr(ahd, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (nvram_scb != 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uint16_t *sc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ahd_set_scbptr(ahd, nvram_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) sc_data = (uint16_t *)sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) for (i = 0; i < 64; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) have_seeprom = ahd_verify_cksum(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (have_seeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ahd->flags |= AHD_SCB_CONFIG_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #ifdef AHD_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (have_seeprom != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) uint16_t *sc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) printk("%s: Seeprom Contents:", ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sc_data = (uint16_t *)sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) for (i = 0; i < (sizeof(*sc)); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) printk("\n\t0x%.4x", sc_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!have_seeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) printk("%s: No SEEPROM available.\n", ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ahd->flags |= AHD_USEDEFAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) error = ahd_default_config(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) adapter_control = CFAUTOTERM|CFSEAUTOTERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) kfree(ahd->seep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ahd->seep_config = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) error = ahd_parse_cfgdata(ahd, sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) adapter_control = sc->adapter_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (error != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ahd_configure_termination(ahd, adapter_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u_int sxfrctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) uint8_t termctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) devconfig &= ~STPWLEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) devconfig |= STPWLEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) printk("%s: STPWLEVEL is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Make sure current sensing is off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Read to sense. Write to set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if ((adapter_control & CFAUTOTERM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) printk("%s: Manual Primary Termination\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if ((adapter_control & CFSTERM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) termctl |= FLX_TERMCTL_ENPRILOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if ((adapter_control & CFWSTERM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) termctl |= FLX_TERMCTL_ENPRIHIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else if (error != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) printk("%s: Primary Auto-Term Sensing failed! "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "Using Defaults.\n", ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if ((adapter_control & CFSEAUTOTERM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (bootverbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) printk("%s: Manual Secondary Termination\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if ((adapter_control & CFSELOWTERM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) termctl |= FLX_TERMCTL_ENSECLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if ((adapter_control & CFSEHIGHTERM) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) termctl |= FLX_TERMCTL_ENSECHIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else if (error != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) printk("%s: Secondary Auto-Term Sensing failed! "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "Using Defaults.\n", ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Now set the termination based on what we found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ahd->flags &= ~AHD_TERM_ENB_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ahd->flags |= AHD_TERM_ENB_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) sxfrctl1 |= STPWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Must set the latch once in order to be effective. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ahd_outb(ahd, SXFRCTL1, sxfrctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (error != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) printk("%s: Unable to set termination settings!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) } else if (bootverbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) printk("%s: Primary High byte termination %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ahd_name(ahd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) printk("%s: Primary Low byte termination %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ahd_name(ahd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) printk("%s: Secondary High byte termination %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ahd_name(ahd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) printk("%s: Secondary Low byte termination %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ahd_name(ahd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define DPE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SSE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define RMA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define RTA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define STA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define DPR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const char *split_status_source[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "DFF0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "DFF1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "OVLY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "CMC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const char *pci_status_source[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "DFF0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "DFF1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "SG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "CMC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "OVLY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "NONE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "TARG"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const char *split_status_strings[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "%s: Received split response in %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "%s: Received split completion error message in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "%s: Receive overrun in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "%s: Count not complete in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "%s: Split completion data bucket in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "%s: Split completion address error in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "%s: Split completion byte count error in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "%s: Signaled Target-abort to early terminate a split in %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const char *pci_status_strings[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "%s: Data Parity Error has been reported via PERR# in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "%s: Target initial wait state error in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "%s: Split completion read data parity error in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "%s: Split completion address attribute parity error in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "%s: Received a Target Abort in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "%s: Received a Master Abort in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "%s: Signal System Error Detected in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "%s: Address or Write Phase Parity Error Detected in %s.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ahd_pci_intr(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) uint8_t pci_status[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ahd_mode_state saved_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u_int pci_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u_int intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u_int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u_int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) intstat = ahd_inb(ahd, INTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if ((intstat & SPLTINT) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ahd_pci_split_intr(ahd, intstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if ((intstat & PCIINT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) printk("%s: PCI error Interrupt\n", ahd_name(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) saved_modes = ahd_save_modes(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ahd_dump_card_state(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (i == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pci_status[i] = ahd_inb(ahd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Clear latched errors. So our interrupt deasserts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ahd_outb(ahd, reg, pci_status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u_int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (i == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) for (bit = 0; bit < 8; bit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((pci_status[i] & (0x1 << bit)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) const char *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) s = pci_status_strings[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (i == 7/*TARG*/ && bit == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) s = "%s: Signaled Target Abort\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) printk(s, ahd_name(ahd), pci_status_source[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) pci_status1 = ahd_pci_read_config(ahd->dev_softc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PCIR_STATUS + 1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pci_status1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ahd_restore_modes(ahd, saved_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ahd_outb(ahd, CLRINT, CLRPCIINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ahd_unpause(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint8_t split_status[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint8_t split_status1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uint8_t sg_split_status[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) uint8_t sg_split_status1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ahd_mode_state saved_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u_int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uint16_t pcix_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Check for splits in all modes. Modes 0 and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * additionally have SG engine splits to look at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) printk("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ahd_name(ahd), pcix_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) saved_modes = ahd_save_modes(ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ahd_set_modes(ahd, i, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Clear latched errors. So our interrupt deasserts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (i > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Clear latched errors. So our interrupt deasserts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u_int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) for (bit = 0; bit < 8; bit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if ((split_status[i] & (0x1 << bit)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) printk(split_status_strings[bit], ahd_name(ahd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) split_status_source[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (i > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if ((sg_split_status[i] & (0x1 << bit)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) printk(split_status_strings[bit], ahd_name(ahd), "SG");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Clear PCI-X status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pcix_status, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ahd_outb(ahd, CLRINT, CLRSPLTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ahd_restore_modes(ahd, saved_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ahd_aic7901_setup(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ahd->chip = AHD_AIC7901;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ahd->features = AHD_AIC7901_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return (ahd_aic790X_setup(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ahd_aic7901A_setup(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ahd->chip = AHD_AIC7901A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ahd->features = AHD_AIC7901A_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return (ahd_aic790X_setup(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ahd_aic7902_setup(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ahd->chip = AHD_AIC7902;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ahd->features = AHD_AIC7902_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return (ahd_aic790X_setup(ahd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ahd_aic790X_setup(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ahd_dev_softc_t pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u_int rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) pci = ahd->dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (rev < ID_AIC7902_PCI_REV_A4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) printk("%s: Unable to attach to unsupported chip revision %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ahd_name(ahd), rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return (ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ahd->channel = ahd_get_pci_function(pci) + 'A';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (rev < ID_AIC7902_PCI_REV_B0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * Enable A series workarounds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) | AHD_FAINT_LED_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * IO Cell parameter setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if ((ahd->flags & AHD_HP_BOARD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* This is revision B and newer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) extern uint32_t aic79xx_slowcrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u_int devconfig1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) | AHD_BUSFREEREV_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* If the user requested that the SLOWCRC bit to be set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (aic79xx_slowcrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ahd->features |= AHD_AIC79XXB_SLOWCRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * Some issues have been resolved in the 7901B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if ((ahd->features & AHD_MULTI_FUNC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * IO Cell parameter setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * Set the PREQDIS bit for H2B which disables some workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * that doesn't work on regular PCI busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * XXX - Find out exactly what this does from the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * folks!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ahd_pci_write_config(pci, DEVCONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) devconfig1|PREQDIS, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags