^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Adaptec AIC79xx device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2000-2001 Adaptec Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic79xx_osm.h#166 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef _AIC79XX_LINUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define _AIC79XX_LINUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <scsi/scsi_eh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <scsi/scsi_transport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <scsi/scsi_transport_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Core SCSI definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AIC_LIB_PREFIX ahd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "cam.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include "queue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include "scsi_message.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include "scsi_iu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include "aiclib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*********************************** Debugging ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_AIC79XX_DEBUG_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_AIC79XX_DEBUG_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AHD_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AHD_DEBUG_OPTS CONFIG_AIC79XX_DEBUG_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Compile in debugging code, but do not enable any printfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AHD_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AHD_DEBUG_OPTS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* No debugging code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /********************************** Misc Macros *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define powerof2(x) ((((x)-1)&(x))==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /************************* Forward Declarations *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ahd_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) typedef struct pci_dev *ahd_dev_softc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) typedef struct scsi_cmnd *ahd_io_ctx_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /******************************* Byte Order ***********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ahd_htobe16(x) cpu_to_be16(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ahd_htobe32(x) cpu_to_be32(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ahd_htobe64(x) cpu_to_be64(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ahd_htole16(x) cpu_to_le16(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ahd_htole32(x) cpu_to_le32(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ahd_htole64(x) cpu_to_le64(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ahd_be16toh(x) be16_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ahd_be32toh(x) be32_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ahd_be64toh(x) be64_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ahd_le16toh(x) le16_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ahd_le32toh(x) le32_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ahd_le64toh(x) le64_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /************************* Configuration Data *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) extern uint32_t aic79xx_allow_memio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern struct scsi_host_template aic79xx_driver_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /***************************** Bus Space/DMA **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) typedef uint32_t bus_size_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BUS_SPACE_MEMIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) BUS_SPACE_PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } bus_space_tag_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u_long ioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) volatile uint8_t __iomem *maddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } bus_space_handle_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) typedef struct bus_dma_segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dma_addr_t ds_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bus_size_t ds_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } bus_dma_segment_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct ahd_linux_dma_tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bus_size_t alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bus_size_t boundary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bus_size_t maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) typedef struct ahd_linux_dma_tag* bus_dma_tag_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) typedef dma_addr_t bus_dmamap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) typedef int bus_dma_filter_t(void*, dma_addr_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BUS_DMA_WAITOK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BUS_DMA_NOWAIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BUS_DMA_ALLOCNOW 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BUS_DMA_LOAD_SEGS 0x4 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Argument is an S/G list not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * a single buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BUS_SPACE_MAXADDR 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ahd_dma_tag_create(struct ahd_softc *, bus_dma_tag_t /*parent*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bus_size_t /*alignment*/, bus_size_t /*boundary*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dma_addr_t /*lowaddr*/, dma_addr_t /*highaddr*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bus_dma_filter_t*/*filter*/, void */*filterarg*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bus_size_t /*maxsize*/, int /*nsegments*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bus_size_t /*maxsegsz*/, int /*flags*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bus_dma_tag_t */*dma_tagp*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void ahd_dma_tag_destroy(struct ahd_softc *, bus_dma_tag_t /*tag*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ahd_dmamem_alloc(struct ahd_softc *, bus_dma_tag_t /*dmat*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void** /*vaddr*/, int /*flags*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bus_dmamap_t* /*mapp*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void ahd_dmamem_free(struct ahd_softc *, bus_dma_tag_t /*dmat*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void* /*vaddr*/, bus_dmamap_t /*map*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void ahd_dmamap_destroy(struct ahd_softc *, bus_dma_tag_t /*tag*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bus_dmamap_t /*map*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ahd_dmamap_load(struct ahd_softc *ahd, bus_dma_tag_t /*dmat*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bus_dmamap_t /*map*/, void * /*buf*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bus_size_t /*buflen*/, bus_dmamap_callback_t *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void */*callback_arg*/, int /*flags*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ahd_dmamap_unload(struct ahd_softc *, bus_dma_tag_t, bus_dmamap_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Operations performed by ahd_dmamap_sync().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * ahd_dmamap_sync is only used on buffers allocated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * the pci_alloc_consistent() API. Although I'm not sure how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * this works on architectures with a write buffer, Linux does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * not have an API to sync "coherent" memory. Perhaps we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * to do an mb()?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ahd_dmamap_sync(ahd, dma_tag, dmamap, offset, len, op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /********************************** Includes **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifdef CONFIG_AIC79XX_REG_PRETTY_PRINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AIC_DEBUG_REGISTERS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AIC_DEBUG_REGISTERS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #include "aic79xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /***************************** SMP support ************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AIC79XX_DRIVER_VERSION "3.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*************************** Device Data Structures ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * A per probed device structure used to deal with some error recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * scenarios that the Linux mid-layer code just doesn't know how to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * handle. The structure allocated for a device only becomes persistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * after a successfully completed inquiry command to the target when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * that inquiry data indicates a lun is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) AHD_DEV_FREEZE_TIL_EMPTY = 0x02, /* Freeze queue until active == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) AHD_DEV_Q_BASIC = 0x10, /* Allow basic device queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) AHD_DEV_Q_TAGGED = 0x20, /* Allow full SCSI2 command queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) AHD_DEV_PERIODIC_OTAG = 0x40, /* Send OTAG to prevent starvation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } ahd_linux_dev_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct ahd_linux_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TAILQ_ENTRY(ahd_linux_device) links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * The number of transactions currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * queued to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * The currently allowed number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * transactions that can be queued to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * the device. Must be signed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * conversion from tagged to untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * mode where the device may have more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * than one outstanding active transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int openings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * A positive count indicates that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * device's queue is halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u_int qfrozen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Cumulative command counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u_long commands_issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * The number of tagged transactions when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * running at our current opening level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * that have been successfully received by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * this device since the last QUEUE FULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u_int tag_success_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AHD_TAG_SUCCESS_INTERVAL 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ahd_linux_dev_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Per device timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * The high limit for the tags variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u_int maxtags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * The computed number of tags outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * at the time of the last QUEUE FULL event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u_int tags_on_last_queuefull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * How many times we have seen a queue full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * with the same number of tags. This is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * to stop our adaptive queue depth algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * on devices with a fixed number of tags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u_int last_queuefull_same_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AHD_LOCK_TAGS_COUNT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * How many transactions have been queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * without the device going idle. We use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * this statistic to determine when to issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * an ordered tag to prevent transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * starvation. This statistic is only updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * if the AHD_DEV_PERIODIC_OTAG flag is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * on this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u_int commands_since_idle_or_otag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AHD_OTAG_THRESH 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /********************* Definitions Required by the Core ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Number of SG segments we require. So long as the S/G segments for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * a particular transaction are allocated in a physically contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * manner and are allocated below 4GB, the number of S/G segments is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * unrestricted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AHD_NSEG 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Per-SCB OSM storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct scb_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ahd_linux_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dma_addr_t buf_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uint32_t xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uint32_t sense_resid; /* Auto-Sense residual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Define a structure used for each host adapter. All members are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * aligned on a boundary >= the size of the member to honor the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * alignment restrictions of the various platforms supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct ahd_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Fields accessed from interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct scsi_target *starget[AHD_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) spinlock_t spin_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct completion *eh_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct Scsi_Host *host; /* pointer to scsi host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AHD_LINUX_NOIRQ ((uint32_t)~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint32_t irq; /* IRQ for this adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint32_t bios_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) resource_size_t mem_busaddr; /* Mem Base Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) void ahd_delay(long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /***************************** Low Level I/O **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uint8_t ahd_inb(struct ahd_softc * ahd, long port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void ahd_outw_atomic(struct ahd_softc * ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) long port, uint16_t val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void ahd_outsb(struct ahd_softc * ahd, long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint8_t *, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void ahd_insb(struct ahd_softc * ahd, long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) uint8_t *, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /**************************** Initialization **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int ahd_linux_register_host(struct ahd_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct scsi_host_template *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /******************************** Locking *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ahd_lockinit(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_lock_init(&ahd->platform_data->spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ahd_lock(struct ahd_softc *ahd, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_lock_irqsave(&ahd->platform_data->spin_lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ahd_unlock(struct ahd_softc *ahd, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) spin_unlock_irqrestore(&ahd->platform_data->spin_lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /******************************* PCI Definitions ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * PCIM_xxx: mask to locate subfield in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * PCIR_xxx: config register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * PCIC_xxx: device class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * PCIS_xxx: device subclass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * PCIP_xxx: device programming interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * PCID_xxx: device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PCIR_DEVVENDOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PCIR_VENDOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PCIR_DEVICE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PCIR_COMMAND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PCIM_CMD_PORTEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PCIM_CMD_MEMEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PCIM_CMD_BUSMASTEREN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PCIM_CMD_MWRICEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PCIM_CMD_PERRESPEN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PCIM_CMD_SERRESPEN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PCIR_STATUS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PCIR_REVID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PCIR_PROGIF 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PCIR_SUBCLASS 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PCIR_CLASS 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PCIR_CACHELNSZ 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PCIR_LATTIMER 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PCIR_HEADERTYPE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PCIM_MFDEV 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PCIR_BIST 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PCIR_CAP_PTR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* config registers for header type 0 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PCIR_MAPS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PCIR_SUBVEND_0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PCIR_SUBDEV_0 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /****************************** PCI-X definitions *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PCIXR_COMMAND 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PCIXR_DEVADDR 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PCIXR_STATUS 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) typedef enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) AHD_POWER_STATE_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) AHD_POWER_STATE_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) AHD_POWER_STATE_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) AHD_POWER_STATE_D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } ahd_power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) void ahd_power_state_change(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ahd_power_state new_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /******************************* PCI Routines *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int ahd_linux_pci_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void ahd_linux_pci_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ahd_pci_map_registers(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ahd_pci_map_int(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uint32_t ahd_pci_read_config(ahd_dev_softc_t pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int reg, int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) void ahd_pci_write_config(ahd_dev_softc_t pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int reg, uint32_t value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline int ahd_get_pci_function(ahd_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ahd_get_pci_function(ahd_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return (PCI_FUNC(pci->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline int ahd_get_pci_slot(ahd_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ahd_get_pci_slot(ahd_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return (PCI_SLOT(pci->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline int ahd_get_pci_bus(ahd_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ahd_get_pci_bus(ahd_dev_softc_t pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return (pci->bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static inline void ahd_flush_device_writes(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ahd_flush_device_writes(struct ahd_softc *ahd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* XXX Is this sufficient for all architectures??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ahd_inb(ahd, INTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /**************************** Proc FS Support *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ahd_proc_write_seeprom(struct Scsi_Host *, char *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ahd_linux_show_info(struct seq_file *,struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*********************** Transaction Access Wrappers **************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline void ahd_cmd_set_transaction_status(struct scsi_cmnd *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static inline void ahd_set_transaction_status(struct scb *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static inline void ahd_cmd_set_scsi_status(struct scsi_cmnd *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline void ahd_set_scsi_status(struct scb *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static inline uint32_t ahd_cmd_get_transaction_status(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline uint32_t ahd_get_transaction_status(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static inline uint32_t ahd_cmd_get_scsi_status(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static inline uint32_t ahd_get_scsi_status(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static inline void ahd_set_transaction_tag(struct scb *, int, u_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static inline u_long ahd_get_transfer_length(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline int ahd_get_transfer_dir(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static inline void ahd_set_residual(struct scb *, u_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline void ahd_set_sense_residual(struct scb *scb, u_long resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static inline u_long ahd_get_residual(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static inline u_long ahd_get_sense_residual(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static inline int ahd_perform_autosense(struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline uint32_t ahd_get_sense_bufsize(struct ahd_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static inline void ahd_notify_xfer_settings_change(struct ahd_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct ahd_devinfo *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static inline void ahd_platform_scb_free(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline void ahd_freeze_scb(struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) void ahd_cmd_set_transaction_status(struct scsi_cmnd *cmd, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cmd->result &= ~(CAM_STATUS_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cmd->result |= status << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void ahd_set_transaction_status(struct scb *scb, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ahd_cmd_set_transaction_status(scb->io_ctx,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) void ahd_cmd_set_scsi_status(struct scsi_cmnd *cmd, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cmd->result &= ~0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cmd->result |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) void ahd_set_scsi_status(struct scb *scb, uint32_t status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ahd_cmd_set_scsi_status(scb->io_ctx, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) uint32_t ahd_cmd_get_transaction_status(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ((cmd->result >> 16) & CAM_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) uint32_t ahd_get_transaction_status(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return (ahd_cmd_get_transaction_status(scb->io_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint32_t ahd_cmd_get_scsi_status(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return (cmd->result & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uint32_t ahd_get_scsi_status(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return (ahd_cmd_get_scsi_status(scb->io_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void ahd_set_transaction_tag(struct scb *scb, int enabled, u_int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Nothing to do for linux as the incoming transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * has no concept of tag/non tagged, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u_long ahd_get_transfer_length(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return (scb->platform_data->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ahd_get_transfer_dir(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return (scb->io_ctx->sc_data_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) void ahd_set_residual(struct scb *scb, u_long resid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) scsi_set_resid(scb->io_ctx, resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void ahd_set_sense_residual(struct scb *scb, u_long resid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) scb->platform_data->sense_resid = resid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u_long ahd_get_residual(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return scsi_get_resid(scb->io_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u_long ahd_get_sense_residual(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return (scb->platform_data->sense_resid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int ahd_perform_autosense(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * We always perform autosense in Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * On other platforms this is set on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * per-transaction basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ahd_get_sense_bufsize(struct ahd_softc *ahd, struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return (sizeof(struct scsi_sense_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ahd_notify_xfer_settings_change(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct ahd_devinfo *devinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Nothing to do here for linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ahd_platform_scb_free(struct ahd_softc *ahd, struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ahd->flags &= ~AHD_RESOURCE_SHORTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int ahd_platform_alloc(struct ahd_softc *ahd, void *platform_arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void ahd_platform_free(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) void ahd_platform_init(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void ahd_platform_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ahd_freeze_scb(struct scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if ((scb->io_ctx->result & (CAM_DEV_QFRZN << 16)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) scb->io_ctx->result |= CAM_DEV_QFRZN << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) scb->platform_data->dev->qfrozen++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void ahd_platform_set_tags(struct ahd_softc *ahd, struct scsi_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct ahd_devinfo *devinfo, ahd_queue_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ahd_platform_abort_scbs(struct ahd_softc *ahd, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) char channel, int lun, u_int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) role_t role, uint32_t status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ahd_linux_isr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void ahd_done(struct ahd_softc*, struct scb*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void ahd_send_async(struct ahd_softc *, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u_int target, u_int lun, ac_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) void ahd_print_path(struct ahd_softc *, struct scb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define AHD_PCI_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define AHD_PCI_CONFIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define bootverbose aic79xx_verbose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) extern uint32_t aic79xx_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #endif /* _AIC79XX_LINUX_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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