^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Core definitions and data structures shareable across OS platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1994-2002 Justin T. Gibbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000-2002 Adaptec Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 2. Redistributions in binary form must reproduce at minimum a disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * substantially similar to the "NO WARRANTY" disclaimer below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ("Disclaimer") and any redistribution must be conditioned upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * including a substantially similar Disclaimer requirement for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * binary redistribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 3. Neither the names of the above-listed copyright holders nor the names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * of any contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * POSSIBILITY OF SUCH DAMAGES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#109 $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * $FreeBSD$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef _AIC79XX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define _AIC79XX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Register Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "aic79xx_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /************************* Forward Declarations *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ahd_platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct scb_platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /****************************** Useful Macros *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifndef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifndef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ALL_CHANNELS '\0'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ALL_TARGETS_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define INITIATOR_WILDCARD (~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCB_LIST_NULL 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QOUTFIFO_ENTRY_VALID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCSIID_TARGET(ahd, scsiid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (((scsiid) & TID) >> TID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCSIID_OUR_ID(scsiid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((scsiid) & OID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCSIID_CHANNEL(ahd, scsiid) ('A')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCB_GET_OUR_ID(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SCSIID_OUR_ID((scb)->hscb->scsiid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCB_GET_TARGET(ahd, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCB_GET_CHANNEL(ahd, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCB_GET_LUN(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ((scb)->hscb->lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCB_GET_TARGET_OFFSET(ahd, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SCB_GET_TARGET(ahd, scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCB_GET_TARGET_MASK(ahd, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef AHD_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCB_IS_SILENT(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) && (((scb)->flags & SCB_SILENT) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCB_IS_SILENT(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (((scb)->flags & SCB_SILENT) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * TCLs have the following format: TTTTLLLLLLLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TCL_TARGET_OFFSET(tcl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ((((tcl) >> 4) & TID) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TCL_LUN(tcl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (tcl & (AHD_NUM_LUNS - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BUILD_TCL(scsiid, lun) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ((lun) | (((scsiid) & TID) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BUILD_TCL_RAW(target, channel, lun) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ((lun) | ((target) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCB_GET_TAG(scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ahd_le16toh(scb->hscb->tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifndef AHD_TARGET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #undef AHD_TMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AHD_TMODE_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AHD_BUILD_COL_IDX(target, lun) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ((((u8)lun) << 4) | target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AHD_GET_SCB_COL_IDX(ahd, scb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AHD_COPY_SCB_COL_IDX(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dst->hscb->scsiid = src->hscb->scsiid; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dst->hscb->lun = src->hscb->lun; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AHD_NEVER_COL_IDX 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**************************** Driver Constants ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The maximum number of supported targets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AHD_NUM_TARGETS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * The maximum number of supported luns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * The identify message only supports 64 luns in non-packetized transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * You can have 2^64 luns when information unit transfers are enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * but until we see a need to support that many, we support 256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AHD_NUM_LUNS_NONPKT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AHD_NUM_LUNS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * The maximum transfer per S/G segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The maximum amount of SCB storage in hardware on a controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * This value represents an upper bound. Due to software design,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * we may not be able to use this number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AHD_SCB_MAX 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * The maximum number of concurrent transactions supported per driver instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Sequencer Control Blocks (SCBs) store per-transaction information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AHD_MAX_QUEUE AHD_SCB_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * in size and accommodate as many transactions as can be queued concurrently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AHD_QIN_SIZE AHD_MAX_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AHD_QOUT_SIZE AHD_MAX_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * The maximum amount of SCB storage we allocate in host memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Ring Buffer of incoming target commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * We allocate 256 to simplify the logic in the sequencer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * by using the natural wrap point of an 8bit counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AHD_TMODE_CMDS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Reset line assertion time in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AHD_BUSRESET_DELAY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /******************* Chip Characteristics/Operating Settings *****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Chip Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * The chip order is from least sophisticated to most sophisticated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) AHD_NONE = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) AHD_CHIPID_MASK = 0x00FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) AHD_AIC7901 = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) AHD_AIC7902 = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) AHD_AIC7901A = 0x0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) AHD_PCI = 0x0100, /* Bus type PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) AHD_PCIX = 0x0200, /* Bus type PCIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) AHD_BUS_MASK = 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } ahd_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Features available in each chip type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) AHD_FENONE = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) AHD_WIDE = 0x00001,/* Wide Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) AHD_AIC79XXB_SLOWCRC = 0x00002,/* SLOWCRC bit should be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) AHD_RTI = 0x04000,/* Retained Training Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AHD_AIC7901_FE = AHD_FENONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) AHD_AIC7901A_FE = AHD_FENONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AHD_AIC7902_FE = AHD_MULTI_FUNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } ahd_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Bugs in the silicon that we work around in software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) AHD_BUGNONE = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Rev A hardware fails to update LAST/CURR/NEXTSCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * correctly in certain packetized selection cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) AHD_SENT_SCB_UPDATE_BUG = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* The wrong SCB is accessed to check the abort pending bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) AHD_ABORT_LQI_BUG = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Packetized bitbucket crosses packet boundaries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) AHD_PKT_BITBUCKET_BUG = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* The selection timer runs twice as long as its setting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) AHD_LONG_SETIMO_BUG = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* The Non-LQ CRC error status is delayed until phase change. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) AHD_NLQICRC_DELAYED_BUG = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* The chip must be reset for all outgoing bus resets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) AHD_SCSIRST_BUG = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Some PCIX fields must be saved and restored across chip reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) AHD_PCIX_CHIPRST_BUG = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* MMAPIO is not functional in PCI-X mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) AHD_PCIX_MMAPIO_BUG = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Reads to SCBRAM fail to reset the discard timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Bug workarounds that can be disabled on non-PCIX busses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) | AHD_PCIX_MMAPIO_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) | AHD_PCIX_SCBRAM_RD_BUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * LQOSTOP0 status set even for forced selections with ATN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * to perform non-packetized message delivery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AHD_LQO_ATNO_BUG = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* FIFO auto-flush does not always trigger. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AHD_AUTOFLUSH_BUG = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* The CLRLQO registers are not self-clearing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* The PACKETIZED status bit refers to the previous connection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AHD_PKTIZED_STATUS_BUG = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* "Short Luns" are not placed into outgoing LQ packets correctly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AHD_PKT_LUN_BUG = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Only the FIFO allocated to the non-packetized connection may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * be in use during a non-packetzied connection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) AHD_NONPACKFIFO_BUG = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Writing to a DFF SCBPTR register may fail if concurent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * a hardware write to the other DFF SCBPTR register. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * not currently a concern in our sequencer since all chips with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * occur in non-packetized connections.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) AHD_MDFF_WSCBPTR_BUG = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* SGHADDR updates are slow. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) AHD_REG_SLOW_SETTLE_BUG = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Changing the MODE_PTR coincident with an interrupt that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * switches to a different mode will cause the interrupt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * be in the mode written outside of interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) AHD_SET_MODE_BUG = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Non-packetized busfree revision does not work. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) AHD_BUSFREEREV_BUG = 0x40000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Paced transfers are indicated with a non-standard PPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * option bit in the neg table, 160MHz is indicated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * sync factor 0x7, and the offset if off by a factor of 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) AHD_PACED_NEGTABLE_BUG = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* LQOOVERRUN false positives. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) AHD_LQOOVERRUN_BUG = 0x100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Controller write to INTSTAT will lose to a host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * write to CLRINT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) AHD_INTCOLLISION_BUG = 0x200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * The GEM318 violates the SCSI spec by not waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * the mandated bus settle delay between phase changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * in some situations. Some aic79xx chip revs. are more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * strict in this regard and will treat REQ assertions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * that fall within the bus settle delay window as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * glitches. This flag tells the firmware to tolerate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * early REQ assertions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) AHD_EARLY_REQ_BUG = 0x400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * The LED does not stay on long enough in packetized modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AHD_FAINT_LED_BUG = 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } ahd_bug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Configuration specific settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * The driver determines these settings by probing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * chip/controller's configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) AHD_FNONE = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) AHD_USEDEFAULTS = 0x00004,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * For cards without an seeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * or a BIOS to initialize the chip's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * SRAM, we use the default target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) AHD_SEQUENCER_DEBUG = 0x00008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) AHD_RESET_BUS_A = 0x00010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) AHD_EXTENDED_TRANS_A = 0x00020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) AHD_TERM_ENB_A = 0x00040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) AHD_SPCHK_ENB_A = 0x00080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) AHD_STPWLEVEL_A = 0x00100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AHD_INITIATORROLE = 0x00200,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Allow initiator operations on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) AHD_TARGETROLE = 0x00400,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Allow target operations on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) AHD_RESOURCE_SHORTAGE = 0x00800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AHD_INT50_SPEEDFLEX = 0x02000,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Internal 50pin connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * sits behind an aic3860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) AHD_BIOS_ENABLED = 0x04000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) AHD_ALL_INTERRUPTS = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) AHD_CURRENT_SENSING = 0x40000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) AHD_HP_BOARD = 0x100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) AHD_BUS_RESET_ACTIVE = 0x200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) AHD_UPDATE_PEND_CMDS = 0x400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) AHD_RUNNING_QOUTFIFO = 0x800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) AHD_HAD_FIRST_SEL = 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } ahd_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /************************* Hardware SCB Definition ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * consists of a "hardware SCB" mirroring the fields available on the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * and additional information the kernel stores for each transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * To minimize space utilization, a portion of the hardware scb stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * different data during different portions of a SCSI transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * As initialized by the host driver for the initiator role, this area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * the cdb has been presented to the target, this area serves to store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * residual transfer information and the SCSI status byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * For the target role, the contents of this area do not change, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * still serve a different purpose than for the initiator role. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * struct target_data for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Status information embedded in the shared poriton of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * an SCB after passing the cdb to the target. The kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * driver will only read this data for transactions that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * complete abnormally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct initiator_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint32_t residual_datacnt; /* Residual in the current S/G seg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint32_t residual_sgptr; /* The next S/G for this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint8_t scsi_status; /* Standard SCSI status byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct target_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint32_t residual_datacnt; /* Residual in the current S/G seg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint32_t residual_sgptr; /* The next S/G for this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) uint8_t scsi_status; /* SCSI status to give to initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint8_t target_phases; /* Bitmap of phases to execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint8_t data_phase; /* Data-In or Data-Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint8_t initiator_tag; /* Initiator's transaction tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Initiator mode SCB shared data area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * If the embedded CDB is 12 bytes or less, we embed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * the sense buffer address in the SCB. This allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * us to retrieve sense information without interrupting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * the host in packetized mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) typedef uint32_t sense_addr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) union initiator_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) uint64_t cdbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint8_t cdblen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } cdb_from_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint8_t cdb[MAX_CDB_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sense_addr_t sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } cdb_plus_saddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Target mode version of the shared data SCB segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct target_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uint32_t spare[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) uint8_t scsi_status; /* SCSI status to give to initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint8_t target_phases; /* Bitmap of phases to execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uint8_t data_phase; /* Data-In or Data-Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint8_t initiator_tag; /* Initiator's transaction tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct hardware_scb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*0*/ union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) union initiator_data idata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct target_data tdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct initiator_status istatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct target_status tstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } shared_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * A word about residuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * The scb is presented to the sequencer with the dataptr and datacnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * fields initialized to the contents of the first S/G element to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * transfer. The sgptr field is initialized to the bus address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * the S/G element that follows the first in the in core S/G array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * S/G entry for this transfer (single S/G element transfer with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * first elements address and length preloaded in the dataptr/datacnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * The SG_FULL_RESID flag ensures that the residual will be correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * noted even if no data transfers occur. Once the data phase is entered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * the residual sgptr and datacnt are loaded from the sgptr and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * datacnt fields. After each S/G element's dataptr and length are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * loaded into the hardware, the residual sgptr is advanced. After
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * each S/G element is expired, its datacnt field is checked to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * residual sg ptr and the transfer is considered complete. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * sequencer determines that there is a residual in the tranfer, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * there is non-zero status, it will set the SG_STATUS_VALID flag in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * sgptr and dma the scb back into host memory. To sumarize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Sequencer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * o A residual has occurred if SG_FULL_RESID is set in sgptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * or residual_sgptr does not have SG_LIST_NULL set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * o We are transferring the last segment if residual_datacnt has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * the SG_LAST_SEG flag set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * o A residual can only have occurred if a completed scb has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * the residual_datacnt, and the residual_sgptr field will tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * for sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * o residual_sgptr and sgptr refer to the "next" sg entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * and so may point beyond the last valid sg entry for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SG_PTR_MASK 0xFFFFFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*16*/ uint16_t tag; /* Reused by Sequencer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*19*/ uint8_t scsiid; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Selection out Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Our Id (bits 0-3) Their ID (bits 4-7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*20*/ uint8_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*21*/ uint8_t task_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*22*/ uint8_t cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*23*/ uint8_t task_management;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*24*/ uint64_t dataptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*36*/ uint32_t sgptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*40*/ uint32_t hscb_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*44*/ uint32_t next_hscb_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /********** Long lun field only downloaded for full 8 byte lun support ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*48*/ uint8_t pkt_long_lun[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*56*/ uint8_t spare[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /************************ Kernel SCB Definitions ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * Some fields of the SCB are OS dependent. Here we collect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * definitions for elements that all OS platforms need to include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * in there SCB definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Definition of a scatter/gather element as transferred to the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * The aic7xxx chips only support a 24bit length. We use the top byte of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * the length to store additional address bits and a flag to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * that a given segment terminates the transfer. This gives us an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * addressable range of 512GB on machines with 64bit PCI or with chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * that can support dual address cycles on 32bit PCI busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct ahd_dma_seg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint32_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define AHD_DMA_LAST_SEG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define AHD_SG_LEN_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ahd_dma64_seg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) uint64_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) uint32_t pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct map_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bus_dmamap_t dmamap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dma_addr_t physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) uint8_t *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) SLIST_ENTRY(map_node) links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * The current state of this SCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SCB_FLAG_NONE = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SCB_TRANSMISSION_ERROR = 0x00001,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * We detected a parity or CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * error that has effected the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * payload of the command. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * flag is checked when normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * status is returned to catch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * the case of a target not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * responding to our attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * to report the error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SCB_OTHERTCL_TIMEOUT = 0x00002,/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Another device was active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * during the first timeout for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * this SCB so we gave ourselves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * an additional timeout period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * in case it was hogging the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SCB_DEVICE_RESET = 0x00004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SCB_SENSE = 0x00008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SCB_CDB32_PTR = 0x00010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SCB_RECOVERY_SCB = 0x00020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SCB_ABORT = 0x00100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SCB_ACTIVE = 0x00200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SCB_TARGET_IMMEDIATE = 0x00400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SCB_PACKETIZED = 0x00800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SCB_EXPECT_PPR_BUSFREE = 0x01000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SCB_PKT_SENSE = 0x02000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SCB_EXTERNAL_RESET = 0x04000,/* Device was reset externally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SCB_ON_COL_LIST = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) SCB_SILENT = 0x10000 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * Be quiet about transmission type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * errors. They are expected and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * don't want to upset the user. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * flag is typically used during DV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } scb_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct scb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct hardware_scb *hscb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SLIST_ENTRY(scb) sle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) LIST_ENTRY(scb) le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) TAILQ_ENTRY(scb) tqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SLIST_ENTRY(scb) sle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) LIST_ENTRY(scb) le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) TAILQ_ENTRY(scb) tqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } links2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define pending_links links2.le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define collision_links links2.le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct scb *col_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ahd_io_ctx_t io_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct ahd_softc *ahd_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) scb_flag flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct scb_platform_data *platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct map_node *hscb_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct map_node *sg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct map_node *sense_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void *sg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) uint8_t *sense_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dma_addr_t sg_list_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dma_addr_t sense_busaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u_int sg_count;/* How full ahd_dma_seg is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define AHD_MAX_LQ_CRC_ERRORS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u_int crc_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) TAILQ_HEAD(scb_tailq, scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) BSD_LIST_HEAD(scb_list, scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct scb_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * TAILQ of lists of free SCBs grouped by device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * collision domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct scb_tailq free_scbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Per-device lists of SCBs whose tag ID would collide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * with an already active tag on the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * SCBs that will not collide with any active device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct scb_list any_dev_free_scb_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Mapping from tag to SCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct scb *scbindex[AHD_SCB_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * "Bus" addresses of our data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SLIST_HEAD(, map_node) hscb_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SLIST_HEAD(, map_node) sg_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SLIST_HEAD(, map_node) sense_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int scbs_left; /* unallocated scbs in head map_node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int sgs_left; /* unallocated sgs in head map_node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int sense_left; /* unallocated sense in head map_node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) uint16_t numscbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint16_t maxhscbs; /* Number of SCBs on the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) uint8_t init_level; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * How far we've initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /************************ Target Mode Definitions *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Connection descriptor for select-in requests in target mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct target_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint8_t scsiid; /* Our ID and the initiator's ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uint8_t identify; /* Identify message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) uint8_t bytes[22]; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * Bytes contains any additional message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * bytes terminated by 0xFF. The remainder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * is the cdb to execute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uint8_t cmd_valid; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * When a command is complete, the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * will set cmd_valid to all bits set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * After the host has seen the command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * the bits are cleared. This allows us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * to just peek at host memory to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * if more work is complete. cmd_valid is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * an 8 byte boundary to simplify setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * it on aic7880 hardware which only has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * limited direct access to the DMA FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uint8_t pad[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Number of events we can buffer up if we run out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * of immediate notify ccbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define AHD_TMODE_EVENT_BUFFER_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct ahd_tmode_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint8_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define EVENT_TYPE_BUS_RESET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) uint8_t event_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Per enabled lun target mode state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * As this state is directly influenced by the host OS'es target mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * environment, we let the OS module define it. Forward declare the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * structure here so we can store arrays of them, etc. in OS neutral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #ifdef AHD_TARGET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct ahd_tmode_lstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct cam_path *path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct ccb_hdr_slist accept_tios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct ccb_hdr_slist immed_notifies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) uint8_t event_r_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) uint8_t event_w_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct ahd_tmode_lstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /******************** Transfer Negotiation Datastructures *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define AHD_PERIOD_10MHz 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define AHD_WIDTH_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define AHD_PERIOD_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define AHD_OFFSET_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define AHD_PPR_OPTS_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * Transfer Negotiation Information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct ahd_transinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) uint8_t protocol_version; /* SCSI Revision level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uint8_t transport_version; /* SPI Revision level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uint8_t width; /* Bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uint8_t period; /* Sync rate factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) uint8_t offset; /* Sync offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint8_t ppr_options; /* Parallel Protocol Request options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * Per-initiator current, goal and user transfer negotiation information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct ahd_initiator_tinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct ahd_transinfo curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct ahd_transinfo goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct ahd_transinfo user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Per enabled target ID state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Pointers to lun target state as well as sync/wide negotiation information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * for each initiator<->target mapping. For the initiator role we pretend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * that we are the target and the targets are the initiators since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * negotiation is the same regardless of role.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct ahd_tmode_tstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Per initiator state bitmasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint16_t auto_negotiate;/* Auto Negotiation Required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint16_t discenable; /* Disconnection allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint16_t tagenable; /* Tagged Queuing allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Points of interest along the negotiated transfer scale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define AHD_SYNCRATE_160 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define AHD_SYNCRATE_PACED 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define AHD_SYNCRATE_DT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define AHD_SYNCRATE_ULTRA2 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define AHD_SYNCRATE_ULTRA 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define AHD_SYNCRATE_FAST 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define AHD_SYNCRATE_SYNC 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define AHD_SYNCRATE_MIN 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define AHD_SYNCRATE_ASYNC 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Safe and valid period for async negotiations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define AHD_ASYNC_XFER_PERIOD 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * In RevA, the synctable uses a 120MHz rate for the period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * factor 8 and 160MHz for the period factor 7. The 120MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * rate never made it into the official SCSI spec, so we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * compensate when setting the negotiation table for Rev A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define AHD_SYNCRATE_REVA_120 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define AHD_SYNCRATE_REVA_160 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /***************************** Lookup Tables **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * Phase -> name and message out response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * to parity errors in each phase table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct ahd_phase_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) uint8_t phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) uint8_t mesg_out; /* Message response to parity errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) const char *phasemsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /************************** Serial EEPROM Format ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct seeprom_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Per SCSI ID Configuration Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) uint16_t device_flags[16]; /* words 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define CFXFER 0x003F /* synchronous transfer rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define CFXFER_ASYNC 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define CFQAS 0x0040 /* Negotiate QAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define CFSTART 0x0100 /* send start unit SCSI command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define CFINCBIOS 0x0200 /* include in BIOS scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define CFDISC 0x0400 /* enable disconnection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define CFWIDEB 0x1000 /* wide bus device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * BIOS Control Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uint16_t bios_control; /* word 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define CFSUPREM 0x0001 /* support all removeable drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define CFSUPREMB 0x0002 /* support removeable boot drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define CFBIOSSTATE 0x000C /* BIOS Action State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define CFBS_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define CFBS_ENABLED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define CFBS_DISABLED_SCAN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define CFENABLEDV 0x0010 /* Perform Domain Validation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define CFSPARITY 0x0040 /* SCSI parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define CFEXTEND 0x0080 /* extended translation enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define CFMSG_VERBOSE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define CFMSG_SILENT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define CFMSG_DIAG 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define CFRESETB 0x0800 /* reset SCSI bus at boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* UNUSED 0xf000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * Host Adapter Control Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uint16_t adapter_control; /* word 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define CFAUTOTERM 0x0001 /* Perform Auto termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define CFSTERM 0x0002 /* SCSI low byte termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define CFWSTERM 0x0004 /* SCSI high byte termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define CFSTPWLEVEL 0x0040 /* Termination level control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define CFCLUSTERENB 0x8000 /* Cluster Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Bus Release Time, Host Adapter ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) uint16_t brtime_id; /* word 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define CFSCSIID 0x000f /* host adapter SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* UNUSED 0x00f0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * Maximum targets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint16_t max_targets; /* word 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define CFMAXTARG 0x00ff /* maximum targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define CFBOOTLUN 0x0f00 /* Lun to boot from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define CFBOOTID 0xf000 /* Target to boot from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) uint16_t res_1[10]; /* words 20-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) uint16_t signature; /* BIOS Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define CFSIGNATURE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) uint16_t checksum; /* word 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * Vital Product Data used during POST and by the BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct vpd_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) uint8_t bios_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define VPDMASTERBIOS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define VPDBOOTHOST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) uint8_t reserved_1[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) uint8_t resource_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) uint8_t resource_len[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) uint8_t resource_data[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uint8_t vpd_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) uint16_t vpd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) uint8_t vpd_keyword[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) uint8_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) uint8_t revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uint8_t device_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) uint8_t termination_menus[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uint8_t fifo_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint8_t end_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) uint8_t vpd_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uint16_t default_target_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uint16_t default_bios_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint16_t default_ctrl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) uint8_t default_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) uint8_t pci_lattime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) uint8_t max_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) uint8_t boot_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) uint16_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) uint8_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) uint8_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) uint8_t reserved_3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /****************************** Flexport Logic ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define FLXADDR_TERMCTL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define FLX_TERMCTL_ENSECHIGH 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define FLX_TERMCTL_ENSECLOW 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define FLX_TERMCTL_ENPRIHIGH 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define FLX_TERMCTL_ENPRILOW 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define FLX_ROMSTAT_SEECFG 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define FLX_ROMSTAT_EECFG 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define FLX_ROMSTAT_SEE_93C66 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define FLX_ROMSTAT_SEE_NONE 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define FLX_ROMSTAT_EE_512x8 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define FLX_ROMSTAT_EE_1MBx8 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define FLX_ROMSTAT_EE_2MBx8 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define FLX_ROMSTAT_EE_4MBx8 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define FLX_ROMSTAT_EE_16MBx8 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define CURSENSE_ENB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define FLXADDR_FLEXSTAT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define FLX_FSTAT_BUSY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define FLXADDR_CURRENT_STAT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define FLX_CSTAT_SEC_HIGH 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define FLX_CSTAT_SEC_LOW 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define FLX_CSTAT_PRI_HIGH 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define FLX_CSTAT_PRI_LOW 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define FLX_CSTAT_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define FLX_CSTAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define FLX_CSTAT_OKAY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define FLX_CSTAT_OVER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define FLX_CSTAT_UNDER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define FLX_CSTAT_INVALID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u_int start_addr, u_int count, int bstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u_int start_addr, u_int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int ahd_verify_cksum(struct seeprom_config *sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int ahd_acquire_seeprom(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) void ahd_release_seeprom(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /**************************** Message Buffer *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) MSG_FLAG_NONE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MSG_FLAG_IU_REQ_CHANGED = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MSG_FLAG_PACKETIZED = 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } ahd_msg_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MSG_TYPE_NONE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MSG_TYPE_INITIATOR_MSGOUT = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) MSG_TYPE_INITIATOR_MSGIN = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MSG_TYPE_TARGET_MSGOUT = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MSG_TYPE_TARGET_MSGIN = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } ahd_msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MSGLOOP_IN_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) MSGLOOP_MSGCOMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) MSGLOOP_TERMINATED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) } msg_loop_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /*********************** Software Configuration Structure *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct ahd_suspend_channel_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uint8_t scsiseq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) uint8_t sxfrctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint8_t sxfrctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) uint8_t simode0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) uint8_t simode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) uint8_t seltimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) uint8_t seqctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct ahd_suspend_pci_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uint32_t devconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) uint8_t command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint8_t csize_lattime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct ahd_suspend_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct ahd_suspend_channel_state channel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct ahd_suspend_pci_state pci_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) uint8_t optionmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint8_t dscommand0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uint8_t dspcistatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* hsmailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uint8_t crccontrol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) uint8_t scbbaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Host and sequencer SCB counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) uint8_t dff_thrsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) uint8_t *scratch_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) uint8_t *btt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) AHD_MODE_DFF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) AHD_MODE_DFF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) AHD_MODE_CCHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) AHD_MODE_SCSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) AHD_MODE_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) AHD_MODE_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } ahd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define AHD_MK_MSK(x) (0x01 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define AHD_MODE_ANY_MSK (~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) typedef uint8_t ahd_mode_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct ahd_completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) uint16_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) uint8_t sg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) uint8_t valid_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct ahd_softc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bus_space_tag_t tags[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) bus_space_handle_t bshs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct scb_data scb_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct hardware_scb *next_queued_hscb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct map_node *next_queued_hscb_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * SCBs that have been sent to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) BSD_LIST_HEAD(, scb) pending_scbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * Current register window mode information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ahd_mode dst_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ahd_mode src_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * Saved register window mode information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * used for restore on next unpause.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ahd_mode saved_dst_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ahd_mode saved_src_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * Platform specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct ahd_platform_data *platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Platform specific device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ahd_dev_softc_t dev_softc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * Bus specific device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ahd_bus_intr_t bus_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * Target mode related state kept on a per enabled lun basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * Targets that are not enabled will have null entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * As an initiator, we keep one target entry for our initiator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * ID to store our sync/wide transfer settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * The black hole device responsible for handling requests for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * disabled luns on enabled targets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct ahd_tmode_lstate *black_hole;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * Device instance currently on the bus awaiting a continue TIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * for a command that was not given the disconnect priveledge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct ahd_tmode_lstate *pending_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Timer handles for timer driven callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct timer_list stat_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * Statistics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define AHD_STAT_UPDATE_US 250000 /* 250ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define AHD_STAT_BUCKETS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) u_int cmdcmplt_bucket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) uint32_t cmdcmplt_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * Card characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ahd_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ahd_feature features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ahd_bug bugs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ahd_flag flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct seeprom_config *seep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Command Queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct ahd_completion *qoutfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) uint16_t qoutfifonext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) uint16_t qoutfifonext_valid_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) uint16_t qinfifonext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) uint16_t qinfifo[AHD_SCB_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Our qfreeze count. The sequencer compares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * this value with its own counter to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * whether to allow selections to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) uint16_t qfreeze_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Values to store in the SEQCTL register for pause and unpause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) uint8_t unpause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) uint8_t pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Critical Section Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct cs *critical_sections;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u_int num_critical_sections;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Buffer for handling packetized bitbucket. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) uint8_t *overrun_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Links for chaining softcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) TAILQ_ENTRY(ahd_softc) links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Channel Names ('A', 'B', etc.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) char channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* Initiator Bus ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) uint8_t our_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * Target incoming command FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct target_cmd *targetcmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) uint8_t tqinfifonext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * Cached verson of the hs_mailbox so we can avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * pausing the sequencer during mailbox updates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) uint8_t hs_mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * Incoming and outgoing message handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) uint8_t send_msg_perror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ahd_msg_flags msg_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ahd_msg_type msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) uint8_t msgout_buf[12];/* Message we are sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) uint8_t msgin_buf[12];/* Message we are receiving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) u_int msgout_len; /* Length of message to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u_int msgout_index; /* Current index in msgout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u_int msgin_index; /* Current index in msgin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * Mapping information for data structures shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * between the sequencer and kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) bus_dma_tag_t parent_dmat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) bus_dma_tag_t shared_data_dmat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct map_node shared_data_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Information saved through suspend/resume cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct ahd_suspend_state suspend_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Number of enabled target mode device on this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u_int enabled_luns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Initialization level of this data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u_int init_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* PCI cacheline size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u_int pci_cachesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* IO Cell Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u_int stack_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) uint16_t *saved_stack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* Per-Unit descriptive information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) const char *description;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) const char *bus_description;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) int unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Selection Timer settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) int seltime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Interrupt coalescing settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define AHD_INT_COALESCING_MAXCMDS_MAX 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define AHD_INT_COALESCING_MINCMDS_MAX 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) u_int int_coalescing_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u_int int_coalescing_maxcmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) u_int int_coalescing_mincmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) u_int int_coalescing_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u_int int_coalescing_stop_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) uint16_t user_discenable;/* Disconnection allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) uint16_t user_tagenable;/* Tagged Queuing allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /*************************** IO Cell Configuration ****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define AHD_PRECOMP_SLEW_INDEX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define AHD_AMPLITUDE_INDEX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define AHD_SET_SLEWRATE(ahd, new_slew) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define AHD_SET_PRECOMP(ahd, new_pcomp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define AHD_SET_AMPLITUDE(ahd, new_amp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /************************ Active Device Information ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ROLE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ROLE_INITIATOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ROLE_TARGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) } role_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct ahd_devinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) int our_scsiid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int target_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) uint16_t target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u_int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u_int lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) char channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) role_t role; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * Only guaranteed to be correct if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * in the busfree state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /****************************** PCI Structures ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) typedef int (ahd_device_setup_t)(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct ahd_pci_identity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) uint64_t full_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) uint64_t id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ahd_device_setup_t *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /***************************** VL/EISA Declarations ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct aic7770_identity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) uint32_t full_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) uint32_t id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ahd_device_setup_t *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) extern struct aic7770_identity aic7770_ident_table [];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) extern const int ahd_num_aic7770_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define AHD_EISA_SLOT_OFFSET 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define AHD_EISA_IOSIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /*************************** Function Declarations ****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /***************************** PCI Front End *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) const struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) int ahd_pci_config(struct ahd_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) const struct ahd_pci_identity *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) int ahd_pci_test_register_access(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) void ahd_pci_suspend(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) void ahd_pci_resume(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /************************** SCB and SCB queue management **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /****************************** Initialization ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) int ahd_softc_init(struct ahd_softc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) void ahd_controller_info(struct ahd_softc *ahd, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int ahd_init(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int ahd_suspend(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) void ahd_resume(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int ahd_default_config(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int ahd_parse_vpddata(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct vpd_config *vpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) int ahd_parse_cfgdata(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct seeprom_config *sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) void ahd_intr_enable(struct ahd_softc *ahd, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) void ahd_pause_and_flushwork(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) void ahd_set_unit(struct ahd_softc *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) void ahd_set_name(struct ahd_softc *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) void ahd_free(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int ahd_reset(struct ahd_softc *ahd, int reinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int ahd_write_flexport(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u_int addr, u_int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) uint8_t *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /***************************** Error Recovery *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SEARCH_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) SEARCH_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) SEARCH_REMOVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) SEARCH_PRINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) } ahd_search_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) char channel, int lun, u_int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) role_t role, uint32_t status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ahd_search_action action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int ahd_search_disc_list(struct ahd_softc *ahd, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) char channel, int lun, u_int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) int stop_on_first, int remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) int save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int ahd_reset_channel(struct ahd_softc *ahd, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) int initiate_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /*************************** Utility Functions ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) u_int our_id, u_int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) u_int lun, char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) role_t role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /************************** Transfer Negotiation ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u_int *ppr_options, u_int maxsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * Negotiation types. These are used to qualify if we should renegotiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * even if our goal and current transport parameters are identical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) } ahd_neg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int ahd_update_neg_request(struct ahd_softc*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct ahd_devinfo*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct ahd_tmode_tstate*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct ahd_initiator_tinfo*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) ahd_neg_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) void ahd_set_width(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct ahd_devinfo *devinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u_int width, u_int type, int paused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) void ahd_set_syncrate(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct ahd_devinfo *devinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u_int period, u_int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) u_int ppr_options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u_int type, int paused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) AHD_QUEUE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) AHD_QUEUE_BASIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) AHD_QUEUE_TAGGED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) } ahd_queue_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /**************************** Target Mode *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #ifdef AHD_TARGET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) void ahd_send_lstate_events(struct ahd_softc *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct ahd_tmode_lstate *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) void ahd_handle_en_lun(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct cam_sim *sim, union ccb *ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct cam_sim *sim, union ccb *ccb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct ahd_tmode_tstate **tstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct ahd_tmode_lstate **lstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int notfound_failure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #ifndef AHD_TMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define AHD_TMODE_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /******************************* Debug ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #ifdef AHD_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) extern uint32_t ahd_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define AHD_SHOW_MISC 0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define AHD_SHOW_SENSE 0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define AHD_SHOW_RECOVERY 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define AHD_DUMP_SEEPROM 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define AHD_SHOW_TERMCTL 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define AHD_SHOW_MEMORY 0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define AHD_SHOW_MESSAGES 0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define AHD_SHOW_MODEPTR 0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define AHD_SHOW_SELTO 0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define AHD_SHOW_FIFOS 0x00200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define AHD_SHOW_QFULL 0x00400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define AHD_SHOW_DV 0x00800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define AHD_SHOW_MASKED_ERRORS 0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define AHD_SHOW_QUEUE 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define AHD_SHOW_TQIN 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define AHD_SHOW_SG 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define AHD_SHOW_INT_COALESCING 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define AHD_DEBUG_SEQUENCER 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) void ahd_print_devinfo(struct ahd_softc *ahd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct ahd_devinfo *devinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) void ahd_dump_card_state(struct ahd_softc *ahd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int ahd_print_register(const ahd_reg_parse_entry_t *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) u_int num_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) u_int address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) u_int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) u_int *cur_column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) u_int wrap_point);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #endif /* _AIC79XX_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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