Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _AHA1740_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /* $Id$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Header file for the adaptec 1740 driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * With minor revisions 3/31/93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Written and (C) 1992,1993 Brad McLean.  See aha1740.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * for more info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SLOTSIZE	0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* EISA configuration registers & values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define	HID0(base)	(base + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define	HID1(base)	(base + 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HID2(base)	(base + 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define	HID3(base)	(base + 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	EBCNTRL(base)	(base + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	PORTADR(base)	(base + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define BIOSADR(base)	(base + 0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define INTDEF(base)	(base + 0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCSIDEF(base)	(base + 0x43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define BUSDEF(base)	(base + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	RESV0(base)	(base + 0x45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RESV1(base)	(base + 0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	RESV2(base)	(base + 0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	HID_MFG	"ADP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	HID_PRD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HID_REV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EBCNTRL_VALUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PORTADDR_ENH 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* READ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	G2INTST(base)	(base + 0x56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define G2STAT(base)	(base + 0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	MBOXIN0(base)	(base + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	MBOXIN1(base)	(base + 0x59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	MBOXIN2(base)	(base + 0x5a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	MBOXIN3(base)	(base + 0x5b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define G2STAT2(base)	(base + 0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define G2INTST_MASK		0xf0	/* isolate the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	G2INTST_CCBGOOD		0x10	/* CCB Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	G2INTST_CCBRETRY	0x50	/* CCB Completed with a retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	G2INTST_HARDFAIL	0x70	/* Adapter Hardware Failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	G2INTST_CMDGOOD		0xa0	/* Immediate command success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define G2INTST_CCBERROR	0xc0	/* CCB Completed with error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	G2INTST_ASNEVENT	0xd0	/* Asynchronous Event Notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	G2INTST_CMDERROR	0xe0	/* Immediate command error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define G2STAT_MBXOUT	4	/* Mailbox Out Empty Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	G2STAT_INTPEND	2	/* Interrupt Pending Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	G2STAT_BUSY	1	/* Busy Bit (attention pending) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define G2STAT2_READY	0	/* Host Ready Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* WRITE (and ReadBack) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	MBOXOUT0(base)	(base + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define	MBOXOUT1(base)	(base + 0x51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	MBOXOUT2(base)	(base + 0x52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	MBOXOUT3(base)	(base + 0x53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	ATTN(base)	(base + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define G2CNTRL(base)	(base + 0x55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define	ATTN_IMMED	0x10	/* Immediate Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	ATTN_START	0x40	/* Start CCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define	ATTN_ABORT	0x50	/* Abort CCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define G2CNTRL_HRST	0x80	/* Hard Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define G2CNTRL_IRST	0x40	/* Clear EISA Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define G2CNTRL_HRDY	0x20	/* Sets HOST ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* This is used with scatter-gather */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct aha1740_chain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 dataptr;		/* Location of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 datalen;		/* Size of this part of chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* These belong in scsi.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define any2scsi(up, p)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) (up)[0] = (((unsigned long)(p)) >> 16)  ;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) (up)[1] = (((unsigned long)(p)) >> 8);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) (up)[2] = ((unsigned long)(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define scsi2int(up) ( (((long)*(up)) << 16) + (((long)(up)[1]) << 8) + ((long)(up)[2]) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define xany2scsi(up, p)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) (up)[0] = ((long)(p)) >> 24;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) (up)[1] = ((long)(p)) >> 16;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) (up)[2] = ((long)(p)) >> 8;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) (up)[3] = ((long)(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define xscsi2int(up) ( (((long)(up)[0]) << 24) + (((long)(up)[1]) << 16) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		      + (((long)(up)[2]) <<  8) +  ((long)(up)[3]) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX_CDB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX_SENSE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAX_STATUS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ecb {			/* Enhanced Control Block 6.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u16 cmdw;		/* Command Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Flag Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u16 cne:1,		/* Control Block Chaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	:6, di:1,		/* Disable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	:2, ses:1,		/* Suppress Underrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	:1, sg:1,		/* Scatter/Gather */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	:1, dsb:1,		/* Disable Status Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 ars:1;			/* Automatic Request Sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* Flag Word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u16 lun:3,		/* Logical Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 tag:1,			/* Tagged Queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 tt:2,			/* Tag Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 nd:1,			/* No Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	:1, dat:1,		/* Data transfer - check direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 dir:1,			/* Direction of transfer 1 = datain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 st:1,			/* Suppress Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 chk:1,			/* Calculate Checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	:2, rec:1,:1;		/* Error Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u16 nil0;		/* nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 dataptr;		/* Data or Scatter List ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 datalen;		/* Data or Scatter List len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 statusptr;		/* Status Block ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 linkptr;		/* Chain Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 nil1;		/* nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 senseptr;		/* Sense Info Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u8 senselen;		/* Sense Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 cdblen;		/* CDB Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u16 datacheck;		/* Data checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u8 cdb[MAX_CDB];	/* CDB area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Hardware defined portion ends here, rest is driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u8 sense[MAX_SENSE];	/* Sense area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u8 status[MAX_STATUS];	/* Status area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct scsi_cmnd *SCpnt;	/* Link to the SCSI Command Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	void (*done) (struct scsi_cmnd *);	/* Completion Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	AHA1740CMD_NOP	 0x00	/* No OP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AHA1740CMD_INIT	 0x01	/* Initiator SCSI Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AHA1740CMD_DIAG	 0x05	/* Run Diagnostic Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AHA1740CMD_SCSI	 0x06	/* Initialize SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AHA1740CMD_SENSE 0x08	/* Read Sense Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AHA1740CMD_DOWN  0x09	/* Download Firmware (yeah, I bet!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AHA1740CMD_RINQ  0x0a	/* Read Host Adapter Inquiry Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AHA1740CMD_TARG  0x10	/* Target SCSI Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AHA1740_ECBS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AHA1740_SCATTER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif