^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _AHA152X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _AHA152X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * $Id: aha152x.h,v 2.7 2004/01/24 11:39:03 fischer Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* number of queueable commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) (unless we support more than 1 cmd_per_lun this should do) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AHA152X_MAXQUEUE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 2.7 $"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* port addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SCSISEQ (HOSTIOPORT0+0x00) /* SCSI sequence control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SCSISIG (HOSTIOPORT0+0x03) /* SCSI signal in/out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCSIRATE (HOSTIOPORT0+0x04) /* SCSI rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SELID (HOSTIOPORT0+0x05) /* selection/reselection ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCSIID SELID /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCSIDAT (HOSTIOPORT0+0x06) /* SCSI latched data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCSIBUS (HOSTIOPORT0+0x07) /* SCSI data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STCNT0 (HOSTIOPORT0+0x08) /* SCSI transfer count 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STCNT1 (HOSTIOPORT0+0x09) /* SCSI transfer count 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STCNT2 (HOSTIOPORT0+0x0a) /* SCSI transfer count 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SSTAT0 (HOSTIOPORT0+0x0b) /* SCSI interrupt status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSTAT1 (HOSTIOPORT0+0x0c) /* SCSI interrupt status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSTAT2 (HOSTIOPORT0+0x0d) /* SCSI interrupt status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCSITEST (HOSTIOPORT0+0x0e) /* SCSI test control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSTAT3 SCSITEST /* SCSI interrupt status 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSTAT4 (HOSTIOPORT0+0x0f) /* SCSI status 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIMODE0 (HOSTIOPORT1+0x10) /* SCSI interrupt mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIMODE1 (HOSTIOPORT1+0x11) /* SCSI interrupt mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMACNTRL0 (HOSTIOPORT1+0x12) /* DMA control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMACNTRL1 (HOSTIOPORT1+0x13) /* DMA control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMASTAT (HOSTIOPORT1+0x14) /* DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FIFOSTAT (HOSTIOPORT1+0x15) /* FIFO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DATAPORT (HOSTIOPORT1+0x16) /* DATA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BRSTCNTRL (HOSTIOPORT1+0x18) /* burst control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PORTA (HOSTIOPORT1+0x1a) /* PORT A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PORTB (HOSTIOPORT1+0x1b) /* PORT B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REV (HOSTIOPORT1+0x1c) /* revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STACK (HOSTIOPORT1+0x1d) /* stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEST (HOSTIOPORT1+0x1e) /* test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IO_RANGE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* used in aha152x_porttest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define O_PORTA 0x1a /* PORT A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define O_PORTB 0x1b /* PORT B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define O_DMACNTRL1 0x13 /* DMA control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define O_STACK 0x1d /* stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* used in tc1550_porttest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define O_TC_PORTA 0x0a /* PORT A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define O_TC_PORTB 0x0b /* PORT B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define O_TC_DMACNTRL1 0x03 /* DMA control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define O_TC_STACK 0x0d /* stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* bits and bitmasks to ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* SCSI sequence control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEMODEO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ENSELO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ENSELI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ENRESELI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ENAUTOATNO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ENAUTOATNI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ENAUTOATNP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCSIRSTO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* SCSI transfer control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCSIEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DMAEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CH1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLRSTCNT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPIOEN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLRCH1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* SCSI transfer control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BITBUCKET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SWRAPEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ENSPCHK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STIMESEL 0x18 /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STIMESEL_ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ENSTIMER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BYTEALIGN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* SCSI signal IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SIG_CDI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SIG_IOI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SIG_MSGI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SIG_ATNI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SIG_SELI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SIG_BSYI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SIG_REQI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SIG_ACKI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* SCSI Phases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define P_MASK (SIG_MSGI|SIG_CDI|SIG_IOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define P_DATAO (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define P_DATAI (SIG_IOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define P_CMD (SIG_CDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define P_STATUS (SIG_CDI|SIG_IOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define P_MSGO (SIG_MSGI|SIG_CDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define P_MSGI (SIG_MSGI|SIG_CDI|SIG_IOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* SCSI signal OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SIG_CDO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SIG_IOO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SIG_MSGO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SIG_ATNO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SIG_SELO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SIG_BSYO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SIG_REQO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SIG_ACKO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* SCSI rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SXFR 0x70 /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SXFR_ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SOFS 0x0f /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OID 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OID_ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* SCSI transfer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GETSTCNT() ( (GETPORT(STCNT2)<<16) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) + (GETPORT(STCNT1)<< 8) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) + GETPORT(STCNT0) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SETSTCNT(X) { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SETPORT(STCNT1, ((X) & 0x00FF00) >> 8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SETPORT(STCNT0, ((X) & 0x0000FF) ); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* SCSI interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TARGET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SELDO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SELDI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SELINGO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SWRAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SDONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPIORDY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DMADONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SETSDONE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLRSELDO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLRSELDI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLRSELINGO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLRSWRAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLRSDONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLRSPIORDY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLRDMADONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* SCSI status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SELTO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ATNTARG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SCSIRSTI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PHASEMIS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BUSFREE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SCSIPERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PHASECHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define REQINIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLRSELTIMO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLRATNO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLRSCSIRSTI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLRBUSFREE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLRSCSIPERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLRPHASECHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLRREQINIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* SCSI status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SOFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SEMPTY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SFULL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SFCNT 0x07 /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* SCSI status 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SCSICNT 0xf0 /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SCSICNT_ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OFFCNT 0x0f /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SCSI TEST control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SCTESTU 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SCTESTD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define STCTEST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* SCSI status 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SYNCERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FWERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FRERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLRSYNCERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLRFWERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLRFRERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* SCSI interrupt mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ENSELDO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ENSELDI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ENSELINGO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ENSWRAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ENSDONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ENSPIORDY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ENDMADONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* SCSI interrupt mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ENSELTIMO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ENATNTARG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ENSCSIRST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ENPHASEMIS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ENBUSFREE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ENSCSIPERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ENPHASECHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ENREQINIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* DMA control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ENDMA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define _8BIT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DMA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define WRITE_READ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define INTEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RSTFIFO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SWINT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* DMA control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PWRDWN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define STK 0x07 /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ATDONE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define WORDRDY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define INTSTAT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DFIFOFULL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DFIFOEMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* BURST control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BON 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define BOFF 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* TEST REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BOFFTMR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define BONTMR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define STCNTH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STCNTM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STCNTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SCSIBLK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DMABLK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* On the AHA-152x board PORTA and PORTB contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) some information about the board's configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned reserved:2; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned tardisc:1; /* Target disconnect: 0=disabled, 1=enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned syncneg:1; /* Initial sync neg: 0=disabled, 1=enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned msgclasses:2; /* Message classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0=#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 1=#0, #1, #2, #3, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 2=#0, #3, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 3=#0, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned boot:1; /* boot: 0=disabled, 1=enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned dma:1; /* Transfer mode: 0=PIO; 1=DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned id:3; /* SCSI-id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned irq:2; /* IRQ-Channel: 0,3=12, 1=10, 2=11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned dmachan:2; /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned parity:1; /* SCSI-parity: 1=enabled 0=disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned short port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } aha152x_config ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define cf_parity fields.parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define cf_dmachan fields.dmachan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define cf_irq fields.irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define cf_id fields.id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define cf_dma fields.dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define cf_boot fields.boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define cf_msgclasses fields.msgclasses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define cf_syncneg fields.syncneg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define cf_tardisc fields.tardisc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define cf_port port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Some macros to manipulate ports and their bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GETPORT(PORT) inb( PORT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SETBITS(PORT, BITS) outb( (inb(PORT) | (BITS)), (PORT) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLRBITS(PORT, BITS) outb( (inb(PORT) & ~(BITS)), (PORT) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TESTHI(PORT, BITS) ((inb(PORT) & (BITS)) == (BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TESTLO(PORT, BITS) ((inb(PORT) & (BITS)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SETRATE(RATE) SETPORT(SCSIRATE,(RATE) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #if defined(AHA152X_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) debug_procinfo = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) debug_queue = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) debug_locking = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) debug_intr = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) debug_selection = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) debug_msgo = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) debug_msgi = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) debug_status = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) debug_cmd = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) debug_datai = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) debug_datao = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) debug_eh = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) debug_done = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) debug_phases = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* for the pcmcia stub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct aha152x_setup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int scsiid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int reconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int synchronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ext_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int tc1550;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #if defined(AHA152X_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) char *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct Scsi_Host *aha152x_probe_one(struct aha152x_setup *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void aha152x_release(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int aha152x_host_reset_host(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif /* _AHA152X_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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