^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 1995-2000 Advanced System Products, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2014 Hannes Reinecke <hare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * changed its name to ConnectCom Solutions, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/eisa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRV_NAME "advansys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ASC_VERSION "3.5" /* AdvanSys Driver Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 1. Use scsi_transport_spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 2. advansys_info is not safe against multiple simultaneous callers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 3. Add module_param to override ISA/VLB ioport array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Enable driver /proc statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADVANSYS_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Enable driver tracing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #undef ADVANSYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) typedef unsigned char uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_VENDOR_ID_ASP 0x10cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_ASP_1200A 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_DEVICE_ID_ASP_ABP940 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_38C0800_REV1 0x2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_DEVICE_ID_38C1600_REV1 0x2700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PortAddr unsigned int /* port address size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define inp(port) inb(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define outp(port, byte) outb((byte), (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define inpw(port) inw(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define outpw(port, word) outw((word), (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ASC_MAX_SG_QUEUE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ASC_MAX_SG_LIST 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ASC_CS_TYPE unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ASC_IS_ISA (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASC_IS_ISAPNP (0x0081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ASC_IS_EISA (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ASC_IS_PCI (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ASC_IS_PCI_ULTRA (0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ASC_IS_PCMCIA (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ASC_IS_MCA (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ASC_IS_VL (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ASC_IS_WIDESCSI_16 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ASC_IS_WIDESCSI_32 (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ASC_IS_BIG_ENDIAN (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ASC_CHIP_MIN_VER_VL (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ASC_CHIP_MAX_VER_VL (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ASC_CHIP_MIN_VER_PCI (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ASC_CHIP_MAX_VER_PCI (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ASC_CHIP_VER_PCI_BIT (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ASC_CHIP_MIN_VER_ISA (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ASC_CHIP_MAX_VER_ISA (0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ASC_CHIP_VER_ISA_BIT (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ASC_CHIP_VER_ASYN_BUG (0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ASC_CHIP_VER_PCI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ASC_CHIP_MIN_VER_EISA (0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ASC_CHIP_MAX_VER_EISA (0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ASC_CHIP_VER_EISA_BIT (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ASC_SCSI_ID_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ASC_SCSI_TIX_TYPE uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ASC_ALL_DEVICE_BIT_SET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ASC_SCSI_BIT_ID_TYPE uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ASC_MAX_TID 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ASC_MAX_LUN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ASC_SCSI_WIDTH_BIT_SET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ASC_MAX_SENSE_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ASC_MIN_SENSE_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ASC_SCSI_RESET_HOLD_TIME_US 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Narrow boards only support 12-byte commands, while wide boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * extend to 16-byte commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ASC_MAX_CDB_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ADV_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MS_SDTR_LEN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MS_WDTR_LEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ASC_SG_LIST_PER_Q 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QS_FREE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QS_READY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QS_DISC1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QS_DISC2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QS_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QS_ABORTED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QS_DONE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QC_NO_CALLBACK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QC_SG_SWAP_QUEUE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define QC_SG_HEAD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define QC_DATA_IN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QC_DATA_OUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define QC_URGENT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define QC_MSG_OUT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define QC_REQ_SENSE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QCSG_SG_XFER_LIST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QCSG_SG_XFER_MORE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QCSG_SG_XFER_END 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QD_IN_PROGRESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QD_NO_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define QD_ABORTED_BY_HOST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QD_WITH_ERROR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define QD_INVALID_REQUEST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define QD_INVALID_HOST_NUM 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define QD_INVALID_DEVICE 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QD_ERR_INTERNAL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define QHSTA_NO_ERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QHSTA_M_SEL_TIMEOUT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define QHSTA_M_DATA_OVER_RUN 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QHSTA_M_DATA_UNDER_RUN 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QHSTA_D_HOST_ABORT_FAILED 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QHSTA_M_WTM_TIMEOUT 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QHSTA_M_TARGET_STATUS_BUSY 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QHSTA_M_BAD_TAG_CODE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QHSTA_D_LRAM_CMP_ERROR 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ASC_FLAG_SCSIQ_REQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ASC_FLAG_BIOS_ASYNC_IO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ASC_FLAG_WIN16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ASC_FLAG_WIN32 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ASC_FLAG_ISA_OVER_16MB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ASC_FLAG_DOS_VM_CALLBACK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ASC_SCSIQ_CPY_BEG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ASC_SCSIQ_SGHD_CPY_BEG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ASC_SCSIQ_B_FWD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ASC_SCSIQ_B_BWD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ASC_SCSIQ_B_STATUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ASC_SCSIQ_B_QNO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ASC_SCSIQ_B_CNTL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ASC_SCSIQ_D_DATA_ADDR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ASC_SCSIQ_D_DATA_CNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ASC_SCSIQ_B_SENSE_LEN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ASC_SCSIQ_DONE_INFO_BEG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ASC_SCSIQ_D_SRBPTR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ASC_SCSIQ_B_TARGET_IX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ASC_SCSIQ_B_CDB_LEN 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ASC_SCSIQ_B_TAG_CODE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ASC_SCSIQ_W_VM_ID 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ASC_SCSIQ_DONE_STATUS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ASC_SCSIQ_HOST_STATUS 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ASC_SCSIQ_SCSI_STATUS 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ASC_SCSIQ_CDB_BEG 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ASC_SCSIQ_B_SG_WK_QP 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ASC_SCSIQ_B_SG_WK_IX 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ASC_SCSIQ_W_ALT_DC1 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ASC_SCSIQ_B_LIST_CNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ASC_SCSIQ_B_CUR_LIST_CNT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ASC_SGQ_B_SG_CNTL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ASC_SGQ_B_SG_HEAD_QP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ASC_SGQ_B_SG_LIST_CNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ASC_SGQ_LIST_BEG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ASC_DEF_SCSI1_QNG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ASC_MAX_SCSI1_QNG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ASC_DEF_SCSI2_QNG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ASC_MAX_SCSI2_QNG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ASC_TAG_CODE_MASK 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ASC_STOP_REQ_RISC_STOP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ASC_STOP_ACK_RISC_STOP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) typedef struct asc_scsiq_1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uchar status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uchar q_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uchar cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) uchar sg_queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) uchar target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uchar target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __le32 data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __le32 data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le32 sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uchar sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) uchar extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } ASC_SCSIQ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) typedef struct asc_scsiq_2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 srb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uchar target_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uchar flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uchar cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uchar tag_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ushort vm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } ASC_SCSIQ_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) typedef struct asc_scsiq_3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uchar done_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uchar host_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) uchar scsi_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) uchar scsi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } ASC_SCSIQ_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) typedef struct asc_scsiq_4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uchar cdb[ASC_MAX_CDB_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uchar y_first_sg_list_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uchar y_working_sg_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uchar y_working_sg_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uchar y_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ushort x_req_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ushort x_reconnect_rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __le32 x_saved_data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __le32 x_saved_data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } ASC_SCSIQ_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) typedef struct asc_q_done_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ASC_SCSIQ_2 d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ASC_SCSIQ_3 d3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uchar q_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uchar q_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uchar cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uchar sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uchar extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uchar res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 remain_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } ASC_QDONE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) typedef struct asc_sg_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __le32 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } ASC_SG_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) typedef struct asc_sg_head {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ushort entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ushort queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ushort entry_to_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ushort res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ASC_SG_LIST sg_list[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } ASC_SG_HEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) typedef struct asc_scsi_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ASC_SCSIQ_1 q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ASC_SCSIQ_2 q2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) uchar *cdbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ASC_SG_HEAD *sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ushort remain_sg_entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ushort next_sg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } ASC_SCSI_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) typedef struct asc_scsi_bios_req_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ASC_SCSIQ_1 r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ASC_SCSIQ_2 r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uchar *cdbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ASC_SG_HEAD *sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uchar *sense_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ASC_SCSIQ_3 r3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uchar cdb[ASC_MAX_CDB_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uchar sense[ASC_MIN_SENSE_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } ASC_SCSI_BIOS_REQ_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) typedef struct asc_risc_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uchar fwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) uchar bwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ASC_SCSIQ_1 i1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ASC_SCSIQ_2 i2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ASC_SCSIQ_3 i3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ASC_SCSIQ_4 i4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } ASC_RISC_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) typedef struct asc_sg_list_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) uchar seq_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) uchar q_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) uchar cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) uchar sg_head_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) uchar sg_list_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uchar sg_cur_list_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } ASC_SG_LIST_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) typedef struct asc_risc_sg_list_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uchar fwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uchar bwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ASC_SG_LIST_Q sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ASC_SG_LIST sg_list[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } ASC_RISC_SG_LIST_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define ASCQ_ERR_Q_STATUS 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ASCQ_ERR_CUR_QNG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ASCQ_ERR_SG_Q_LINKS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Warning code values are set in ASC_DVC_VAR 'warn_code'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ASC_WARN_NO_ERROR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ASC_WARN_IO_PORT_ROTATE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ASC_WARN_EEPROM_CHKSUM 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ASC_WARN_IRQ_MODIFIED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ASC_WARN_AUTO_CONFIG 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ASC_WARN_EEPROM_RECOVER 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ASC_WARN_CFG_MSW_RECOVER 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ASC_IERR_SET_PC_ADDR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ASC_IERR_NO_BUS_TYPE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define ASC_MIN_TAG_Q_PER_DVC (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ASC_MIN_FREE_Q (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ASC_MAX_TOTAL_QNG 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define ASC_MAX_INRAM_TAG_QNG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ASC_IOADR_GAP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define ASC_SYN_MAX_OFFSET 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define ASC_DEF_SDTR_OFFSET 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* The narrow chip only supports a limited selection of transfer rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * These are encoded in the range 0..7 or 0..15 depending whether the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * is Ultra-capable or not. These tables let us convert from one to the other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const unsigned char asc_syn_xfer_period[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 25, 30, 35, 40, 50, 60, 70, 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const unsigned char asc_syn_ultra_xfer_period[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) typedef struct ext_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uchar msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uchar msg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uchar msg_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) uchar sdtr_xfer_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uchar sdtr_req_ack_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) uchar wdtr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } wdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) uchar mdp_b3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) uchar mdp_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) uchar mdp_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uchar mdp_b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } mdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } u_ext_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uchar res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } EXT_MSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define wdtr_width u_ext_msg.wdtr.wdtr_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define mdp_b3 u_ext_msg.mdp_b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define mdp_b2 u_ext_msg.mdp_b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define mdp_b1 u_ext_msg.mdp_b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define mdp_b0 u_ext_msg.mdp_b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) typedef struct asc_dvc_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ASC_SCSI_BIT_ID_TYPE disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ASC_SCSI_BIT_ID_TYPE sdtr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uchar chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uchar isa_dma_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uchar isa_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uchar chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ushort mcode_date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ushort mcode_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uchar max_tag_qng[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uchar sdtr_period_offset[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uchar adapter_info[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } ASC_DVC_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define ASC_DEF_DVC_CNTL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ASC_DEF_CHIP_SCSI_ID 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define ASC_DEF_ISA_DMA_SPEED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define ASC_INIT_STATE_END_GET_CFG 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ASC_INIT_STATE_END_SET_CFG 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ASC_INIT_STATE_END_LOAD_MC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define ASC_INIT_STATE_END_INQUIRY 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define ASC_INIT_RESET_SCSI_DONE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define ASC_MIN_TAGGED_CMD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define ASC_MAX_SCSI_RESET_WAIT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define ASC_OVERRUN_BSIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct asc_dvc_var; /* Forward Declaration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) typedef struct asc_dvc_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ushort err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ushort dvc_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ushort bug_fix_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ushort bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ASC_SCSI_BIT_ID_TYPE init_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ASC_SCSI_BIT_ID_TYPE sdtr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ASC_SCSI_BIT_ID_TYPE unit_not_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ASC_SCSI_BIT_ID_TYPE start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) uchar *overrun_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dma_addr_t overrun_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uchar scsi_reset_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) uchar chip_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bool is_in_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uchar max_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) uchar cur_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) uchar in_critical_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uchar last_q_shortage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ushort init_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uchar cur_dvc_qng[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) uchar max_dvc_qng[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) const uchar *sdtr_period_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ASC_DVC_CFG *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) char redo_scam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ushort res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) uchar dos_int13_table[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned int max_dma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ASC_SCSI_BIT_ID_TYPE no_scam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) uchar min_sdtr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) uchar max_sdtr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct asc_board *drv_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int uc_break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } ASC_DVC_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) typedef struct asc_dvc_inq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } ASC_DVC_INQ_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) typedef struct asc_cap_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 blk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } ASC_CAP_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) typedef struct asc_cap_info_array {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } ASC_CAP_INFO_ARRAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define ASC_CNTL_INITIATOR (ushort)0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define ASC_CNTL_NO_SCAM (ushort)0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define ASC_CNTL_RESET_SCSI (ushort)0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define ASC_CNTL_BURST_MODE (ushort)0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define ASC_EEP_DVC_CFG_BEG_VL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define ASC_EEP_MAX_DVC_ADDR_VL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define ASC_EEP_DVC_CFG_BEG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define ASC_EEP_MAX_DVC_ADDR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define ASC_EEP_MAX_RETRY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * These macros keep the chip SCSI id and ISA DMA speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * bitfields in board order. C bitfields aren't portable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * between big and little-endian platforms so they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) typedef struct asceep_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ushort cfg_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ushort cfg_msw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uchar init_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uchar disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) uchar use_cmd_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uchar start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) uchar max_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uchar max_tag_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uchar bios_scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uchar power_up_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) uchar no_scam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uchar id_speed; /* low order 4 bits is chip scsi id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* high order 4 bits is isa dma speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uchar dos_int13_table[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) uchar adapter_info[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ushort cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ushort chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } ASCEEP_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define ASC_EEP_CMD_READ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define ASC_EEP_CMD_WRITE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define ASC_EEP_CMD_WRITE_ABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define ASC_EEP_CMD_WRITE_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define ASCV_MSGOUT_BEG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define ASCV_BREAK_ADDR (ushort)0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define ASCV_BREAK_CONTROL (ushort)0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define ASCV_MCODE_SIZE_W (ushort)0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define ASCV_STOP_CODE_B (ushort)0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ASCV_HALTCODE_W (ushort)0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define ASCV_CHKSUM_W (ushort)0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define ASCV_MC_DATE_W (ushort)0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define ASCV_MC_VER_W (ushort)0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define ASCV_NEXTRDY_B (ushort)0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define ASCV_DONENEXT_B (ushort)0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define ASCV_SCSIBUSY_B (ushort)0x004B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define ASCV_CURCDB_B (ushort)0x004D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define ASCV_RCLUN_B (ushort)0x004E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define ASCV_BUSY_QHEAD_B (ushort)0x004F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define ASCV_DISC1_QHEAD_B (ushort)0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define ASCV_DISC_ENABLE_B (ushort)0x0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define ASCV_MCODE_CNTL_B (ushort)0x0056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define ASCV_NULL_TARGET_B (ushort)0x0057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define ASCV_HOST_FLAG_B (ushort)0x005D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define ASCV_VER_SERIAL_B (ushort)0x0065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define ASCV_WTM_FLAG_B (ushort)0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define ASCV_RISC_FLAG_B (ushort)0x006A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define ASC_HOST_FLAG_IN_ISR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define ASC_HOST_FLAG_ACK_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define ASC_RISC_FLAG_GEN_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define IOP_CTRL (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define IOP_STATUS (0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define IOP_INT_ACK IOP_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define IOP_REG_IFC (0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define IOP_SYN_OFFSET (0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define IOP_EXTRA_CONTROL (0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define IOP_REG_PC (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define IOP_RAM_ADDR (0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define IOP_RAM_DATA (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define IOP_EEP_DATA (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define IOP_EEP_CMD (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define IOP_VERSION (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define IOP_CONFIG_HIGH (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define IOP_CONFIG_LOW (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define IOP_SIG_BYTE (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define IOP_SIG_WORD (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define IOP_REG_DC1 (0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define IOP_REG_DC0 (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define IOP_REG_SB (0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define IOP_REG_DA1 (0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define IOP_REG_DA0 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define IOP_REG_SC (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define IOP_DMA_SPEED (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define IOP_REG_FLAG (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define IOP_FIFO_H (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define IOP_FIFO_L (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define IOP_REG_ID (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define IOP_REG_QP (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define IOP_REG_IH (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define IOP_REG_IX (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define IOP_REG_AX (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define IFC_REG_LOCK (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define IFC_REG_UNLOCK (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define IFC_WR_EN_FILTER (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define IFC_RD_NO_EEPROM (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define IFC_SLEW_RATE (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define IFC_ACT_NEG (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define IFC_INP_FILTER (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define SC_SEL (uchar)(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define SC_BSY (uchar)(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define SC_ACK (uchar)(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define SC_REQ (uchar)(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define SC_ATN (uchar)(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define SC_IO (uchar)(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define SC_CD (uchar)(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define SC_MSG (uchar)(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define SEC_SCSI_CTL (uchar)(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define SEC_ACTIVE_NEGATE (uchar)(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define SEC_SLEW_RATE (uchar)(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define SEC_ENABLE_FILTER (uchar)(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define ASC_HALT_EXTMSG_IN (ushort)0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define ASC_HALT_CHK_CONDITION (ushort)0x8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define ASC_MAX_QNO 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define ASC_DATA_SEC_BEG (ushort)0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define ASC_DATA_SEC_END (ushort)0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define ASC_CODE_SEC_BEG (ushort)0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define ASC_CODE_SEC_END (ushort)0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ASC_QADR_BEG (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define ASC_QADR_END (ushort)0x7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define ASC_QLAST_ADR (ushort)0x7FC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define ASC_QBLK_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define ASC_BIOS_DATA_QBEG 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define ASC_MIN_ACTIVE_QNO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define ASC_QLINK_END 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define ASC_EEPROM_WORDS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define ASC_MAX_MGS_LEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define ASC_BIOS_ADDR_DEF 0xDC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define ASC_BIOS_SIZE 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define ASC_BIOS_RAM_OFF 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define ASC_BIOS_RAM_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define ASC_BIOS_MIN_ADDR 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define ASC_BIOS_MAX_ADDR 0xEC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define ASC_BIOS_BANK_SIZE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define ASC_MCODE_START_ADDR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define ASC_CFG0_HOST_INT_ON 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define ASC_CFG0_BIOS_ON 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define ASC_CFG0_VERA_BURST_ON 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define ASC_CFG0_SCSI_PARITY_ON 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define ASC_CFG1_SCSI_TARGET_ON 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define ASC_CFG1_LRAM_8BITS_ON 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define ASC_CFG_MSW_CLR_MASK 0x3080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define CSW_TEST1 (ASC_CS_TYPE)0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define CSW_TEST2 (ASC_CS_TYPE)0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define CSW_TEST3 (ASC_CS_TYPE)0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define CSW_HALTED (ASC_CS_TYPE)0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define CIW_TEST1 (ASC_CS_TYPE)0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define CIW_TEST2 (ASC_CS_TYPE)0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define CC_CHIP_RESET (uchar)0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define CC_SCSI_RESET (uchar)0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define CC_HALT (uchar)0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define CC_SINGLE_STEP (uchar)0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define CC_DMA_ABLE (uchar)0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define CC_TEST (uchar)0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define CC_BANK_ONE (uchar)0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define CC_DIAG (uchar)0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define ASC_1000_ID0W 0x04C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define ASC_1000_ID0W_FIX 0x00C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define ASC_1000_ID1B 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define ASC_EISA_REV_IOP_MASK (0x0C83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define ASC_EISA_CFG_IOP_MASK (0x0C86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define INS_HALTINT (ushort)0x6281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define INS_HALT (ushort)0x6280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define INS_SINT (ushort)0x6200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define INS_RFLAG_WTM (ushort)0x7380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define ASC_MC_SAVE_CODE_WSIZE 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define ASC_MC_SAVE_DATA_WSIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) typedef struct asc_mc_saved {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ushort data[ASC_MC_SAVE_DATA_WSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ushort code[ASC_MC_SAVE_CODE_WSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } ASC_MC_SAVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define AdvPortAddr void __iomem * /* Virtual memory address size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Define Adv Library required memory access macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define ADV_MEM_READB(addr) readb(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define ADV_MEM_READW(addr) readw(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * Define total number of simultaneous maximum element scatter-gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * maximum number of outstanding commands per wide host adapter. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * structures or 255 scatter-gather elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Define maximum number of scatter-gather elements per request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define ADV_MAX_SG_LIST 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define NO_OF_SG_PER_BLOCK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define ADV_EEP_DVC_CFG_BEGIN (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define ADV_EEP_DVC_CFG_END (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define ADV_EEP_MAX_WORD_ADDR (0x1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define ADV_EEP_DELAY_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * For the ASC3550 Bit 13 is Termination Polarity control bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * For later ICs Bit 13 controls whether the CIS (Card Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * Service Section) is loaded from EEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * ASC38C1600 Bit 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * Function 0 will specify INT B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Function 1 will specify INT A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) typedef struct adveep_3550_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Word Offset, Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ushort cfg_lsw; /* 00 power up initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* bit 13 set - Term Polarity Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* bit 14 set - BIOS Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* bit 15 set - Big Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ushort cfg_msw; /* 01 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ushort disc_enable; /* 02 disconnect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ushort wdtr_able; /* 03 Wide DTR able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ushort sdtr_able; /* 04 Synchronous DTR able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ushort start_motor; /* 05 send start up motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ushort tagqng_able; /* 06 tag queuing able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ushort bios_scan; /* 07 BIOS device control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ushort scam_tolerant; /* 08 no scam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) uchar adapter_scsi_id; /* 09 Host Adapter ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) uchar bios_boot_delay; /* power up wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) uchar scsi_reset_delay; /* 10 reset delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uchar bios_id_lun; /* first boot device scsi id & lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* high nibble is lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* low nibble is scsi id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) uchar termination; /* 11 0 - automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* 1 - low off / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* 2 - low off / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* 3 - low on / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* There is no low on / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) uchar reserved1; /* reserved byte (not used) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ushort bios_ctrl; /* 12 BIOS control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* bit 0 BIOS don't act as initiator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* bit 1 BIOS > 1 GB support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* bit 2 BIOS > 2 Disk Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* bit 3 BIOS don't support removables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* bit 4 BIOS support bootable CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* bit 5 BIOS scan enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* bit 6 BIOS support multiple LUNs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* bit 7 BIOS display of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* bit 8 SCAM disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* bit 9 Reset SCSI bus during init. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* bit 11 No verbose initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* bit 12 SCSI parity enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ushort ultra_able; /* 13 ULTRA speed able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ushort reserved2; /* 14 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) uchar max_host_qng; /* 15 maximum host queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) uchar max_dvc_qng; /* maximum per device queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ushort dvc_cntl; /* 16 control bit for driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ushort bug_fix; /* 17 control bit for bug fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ushort serial_number_word1; /* 18 Board serial number word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ushort serial_number_word2; /* 19 Board serial number word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ushort serial_number_word3; /* 20 Board serial number word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ushort check_sum; /* 21 EEP check sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) uchar oem_name[16]; /* 22 OEM name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ushort dvc_err_code; /* 30 last device driver error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ushort adv_err_code; /* 31 last uc and Adv Lib error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ushort adv_err_addr; /* 32 last uc error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ushort saved_adv_err_addr; /* 35 saved last uc error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ushort num_of_err; /* 36 number of error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } ADVEEP_3550_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) typedef struct adveep_38C0800_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Word Offset, Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ushort cfg_lsw; /* 00 power up initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* bit 13 set - Load CIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* bit 14 set - BIOS Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* bit 15 set - Big Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ushort cfg_msw; /* 01 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ushort disc_enable; /* 02 disconnect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ushort wdtr_able; /* 03 Wide DTR able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ushort start_motor; /* 05 send start up motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ushort tagqng_able; /* 06 tag queuing able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ushort bios_scan; /* 07 BIOS device control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ushort scam_tolerant; /* 08 no scam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uchar adapter_scsi_id; /* 09 Host Adapter ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uchar bios_boot_delay; /* power up wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uchar scsi_reset_delay; /* 10 reset delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) uchar bios_id_lun; /* first boot device scsi id & lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* high nibble is lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* low nibble is scsi id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) uchar termination_se; /* 11 0 - automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* 1 - low off / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* 2 - low off / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* 3 - low on / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* There is no low on / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) uchar termination_lvd; /* 11 0 - automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* 1 - low off / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* 2 - low off / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* 3 - low on / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* There is no low on / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ushort bios_ctrl; /* 12 BIOS control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* bit 0 BIOS don't act as initiator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* bit 1 BIOS > 1 GB support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* bit 2 BIOS > 2 Disk Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* bit 3 BIOS don't support removables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* bit 4 BIOS support bootable CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* bit 5 BIOS scan enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* bit 6 BIOS support multiple LUNs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* bit 7 BIOS display of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* bit 8 SCAM disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* bit 9 Reset SCSI bus during init. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* bit 11 No verbose initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* bit 12 SCSI parity enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* bit 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) uchar max_host_qng; /* 15 maximum host queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) uchar max_dvc_qng; /* maximum per device queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ushort dvc_cntl; /* 16 control bit for driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ushort serial_number_word1; /* 18 Board serial number word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ushort serial_number_word2; /* 19 Board serial number word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ushort serial_number_word3; /* 20 Board serial number word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ushort check_sum; /* 21 EEP check sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) uchar oem_name[16]; /* 22 OEM name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ushort dvc_err_code; /* 30 last device driver error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ushort adv_err_code; /* 31 last uc and Adv Lib error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ushort adv_err_addr; /* 32 last uc error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ushort saved_adv_err_addr; /* 35 saved last uc error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ushort reserved36; /* 36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ushort reserved37; /* 37 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ushort reserved38; /* 38 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ushort reserved39; /* 39 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ushort reserved40; /* 40 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ushort reserved41; /* 41 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ushort reserved42; /* 42 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ushort reserved43; /* 43 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ushort reserved44; /* 44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ushort reserved45; /* 45 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ushort reserved46; /* 46 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ushort reserved47; /* 47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ushort reserved48; /* 48 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ushort reserved49; /* 49 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ushort reserved50; /* 50 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ushort reserved51; /* 51 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ushort reserved52; /* 52 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ushort reserved53; /* 53 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ushort reserved54; /* 54 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ushort reserved55; /* 55 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ushort cisptr_lsw; /* 56 CIS PTR LSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ushort cisprt_msw; /* 57 CIS PTR MSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ushort subsysvid; /* 58 SubSystem Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ushort subsysid; /* 59 SubSystem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ushort reserved60; /* 60 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ushort reserved61; /* 61 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ushort reserved62; /* 62 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ushort reserved63; /* 63 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) } ADVEEP_38C0800_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) typedef struct adveep_38C1600_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Word Offset, Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ushort cfg_lsw; /* 00 power up initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* clear - Func. 0 INTA, Func. 1 INTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* bit 13 set - Load CIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* bit 14 set - BIOS Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* bit 15 set - Big Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ushort cfg_msw; /* 01 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ushort disc_enable; /* 02 disconnect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ushort wdtr_able; /* 03 Wide DTR able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ushort start_motor; /* 05 send start up motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ushort tagqng_able; /* 06 tag queuing able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ushort bios_scan; /* 07 BIOS device control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ushort scam_tolerant; /* 08 no scam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) uchar adapter_scsi_id; /* 09 Host Adapter ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) uchar bios_boot_delay; /* power up wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) uchar scsi_reset_delay; /* 10 reset delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) uchar bios_id_lun; /* first boot device scsi id & lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* high nibble is lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* low nibble is scsi id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) uchar termination_se; /* 11 0 - automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* 1 - low off / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* 2 - low off / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* 3 - low on / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* There is no low on / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) uchar termination_lvd; /* 11 0 - automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* 1 - low off / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* 2 - low off / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* 3 - low on / high on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* There is no low on / high off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ushort bios_ctrl; /* 12 BIOS control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* bit 0 BIOS don't act as initiator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* bit 1 BIOS > 1 GB support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* bit 2 BIOS > 2 Disk Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* bit 3 BIOS don't support removables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* bit 4 BIOS support bootable CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* bit 5 BIOS scan enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* bit 6 BIOS support multiple LUNs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* bit 7 BIOS display of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* bit 8 SCAM disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* bit 9 Reset SCSI bus during init. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* bit 10 Basic Integrity Checking disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* bit 11 No verbose initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* bit 12 SCSI parity enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* bit 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) uchar max_host_qng; /* 15 maximum host queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) uchar max_dvc_qng; /* maximum per device queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ushort dvc_cntl; /* 16 control bit for driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ushort serial_number_word1; /* 18 Board serial number word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ushort serial_number_word2; /* 19 Board serial number word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ushort serial_number_word3; /* 20 Board serial number word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ushort check_sum; /* 21 EEP check sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) uchar oem_name[16]; /* 22 OEM name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ushort dvc_err_code; /* 30 last device driver error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ushort adv_err_code; /* 31 last uc and Adv Lib error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ushort adv_err_addr; /* 32 last uc error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ushort saved_adv_err_addr; /* 35 saved last uc error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ushort reserved36; /* 36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ushort reserved37; /* 37 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ushort reserved38; /* 38 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ushort reserved39; /* 39 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ushort reserved40; /* 40 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ushort reserved41; /* 41 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ushort reserved42; /* 42 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ushort reserved43; /* 43 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ushort reserved44; /* 44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ushort reserved45; /* 45 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ushort reserved46; /* 46 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ushort reserved47; /* 47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ushort reserved48; /* 48 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ushort reserved49; /* 49 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ushort reserved50; /* 50 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ushort reserved51; /* 51 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ushort reserved52; /* 52 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ushort reserved53; /* 53 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ushort reserved54; /* 54 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ushort reserved55; /* 55 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ushort cisptr_lsw; /* 56 CIS PTR LSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ushort cisprt_msw; /* 57 CIS PTR MSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ushort subsysvid; /* 58 SubSystem Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ushort subsysid; /* 59 SubSystem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ushort reserved60; /* 60 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ushort reserved61; /* 61 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ushort reserved62; /* 62 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ushort reserved63; /* 63 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } ADVEEP_38C1600_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * EEPROM Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define ASC_EEP_CMD_DONE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define BIOS_CTRL_BIOS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define BIOS_CTRL_EXTENDED_XLAT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define BIOS_CTRL_GT_2_DISK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define BIOS_CTRL_BOOTABLE_CD 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define BIOS_CTRL_MULTIPLE_LUN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define BIOS_CTRL_DISPLAY_MSG 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define BIOS_CTRL_NO_SCAM 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define BIOS_CTRL_INIT_VERBOSE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define BIOS_CTRL_SCSI_PARITY 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define BIOS_CTRL_AIPP_DIS 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * a special 16K Adv Library and Microcode version. After the issue is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * resolved, should restore 32K support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * Byte I/O register address from base of 'iop_base'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define IOPB_INTR_STATUS_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define IOPB_CHIP_ID_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define IOPB_INTR_ENABLES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define IOPB_CHIP_TYPE_REV 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define IOPB_RES_ADDR_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define IOPB_RES_ADDR_5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define IOPB_RAM_DATA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define IOPB_RES_ADDR_7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define IOPB_FLAG_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define IOPB_RES_ADDR_9 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define IOPB_RISC_CSR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define IOPB_RES_ADDR_B 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define IOPB_RES_ADDR_C 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define IOPB_RES_ADDR_D 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define IOPB_SOFT_OVER_WR 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define IOPB_RES_ADDR_F 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define IOPB_MEM_CFG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define IOPB_RES_ADDR_11 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define IOPB_GPIO_DATA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define IOPB_RES_ADDR_13 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define IOPB_FLASH_PAGE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define IOPB_RES_ADDR_15 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define IOPB_GPIO_CNTL 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define IOPB_RES_ADDR_17 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define IOPB_FLASH_DATA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define IOPB_RES_ADDR_19 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define IOPB_RES_ADDR_1A 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define IOPB_RES_ADDR_1B 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define IOPB_RES_ADDR_1C 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define IOPB_RES_ADDR_1D 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define IOPB_RES_ADDR_1E 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define IOPB_RES_ADDR_1F 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define IOPB_DMA_CFG0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define IOPB_DMA_CFG1 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define IOPB_TICKLE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define IOPB_DMA_REG_WR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define IOPB_SDMA_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define IOPB_SCSI_BYTE_CNT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define IOPB_HOST_BYTE_CNT 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define IOPB_BYTE_LEFT_TO_XFER 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define IOPB_BYTE_TO_XFER_0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define IOPB_BYTE_TO_XFER_1 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define IOPB_BYTE_TO_XFER_2 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define IOPB_BYTE_TO_XFER_3 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define IOPB_ACC_GRP 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define IOPB_RES_ADDR_2D 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define IOPB_DEV_ID 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define IOPB_RES_ADDR_2F 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define IOPB_SCSI_DATA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define IOPB_RES_ADDR_31 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define IOPB_RES_ADDR_32 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define IOPB_SCSI_DATA_HSHK 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define IOPB_SCSI_CTRL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define IOPB_RES_ADDR_35 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define IOPB_RES_ADDR_36 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define IOPB_RES_ADDR_37 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define IOPB_RAM_BIST 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define IOPB_PLL_TEST 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define IOPB_PCI_INT_CFG 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define IOPB_RES_ADDR_3B 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define IOPB_RFIFO_CNT 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define IOPB_RES_ADDR_3D 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define IOPB_RES_ADDR_3E 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define IOPB_RES_ADDR_3F 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * Word I/O register address from base of 'iop_base'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define IOPW_CHIP_ID_0 0x00 /* CID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define IOPW_CTRL_REG 0x02 /* CC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define IOPW_RAM_ADDR 0x04 /* LA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define IOPW_RAM_DATA 0x06 /* LD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define IOPW_RES_ADDR_08 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define IOPW_RISC_CSR 0x0A /* CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define IOPW_RES_ADDR_10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define IOPW_SEL_MASK 0x12 /* SM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define IOPW_RES_ADDR_14 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define IOPW_FLASH_ADDR 0x16 /* FA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define IOPW_RES_ADDR_18 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define IOPW_EE_CMD 0x1A /* EC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define IOPW_EE_DATA 0x1C /* ED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define IOPW_SFIFO_CNT 0x1E /* SFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define IOPW_RES_ADDR_20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define IOPW_Q_BASE 0x22 /* QB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define IOPW_QP 0x24 /* QP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define IOPW_IX 0x26 /* IX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define IOPW_SP 0x28 /* SP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define IOPW_PC 0x2A /* PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define IOPW_RES_ADDR_2C 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define IOPW_RES_ADDR_2E 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define IOPW_SCSI_DATA 0x30 /* SD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define IOPW_SCSI_CTRL 0x34 /* SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define IOPW_HSHK_CFG 0x36 /* HCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define IOPW_SXFR_STATUS 0x36 /* SXS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define IOPW_SXFR_CNTL 0x38 /* SXL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define IOPW_SXFR_CNTH 0x3A /* SXH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define IOPW_RES_ADDR_3C 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define IOPW_RFIFO_DATA 0x3E /* RFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * Doubleword I/O register address from base of 'iop_base'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define IOPDW_RES_ADDR_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define IOPDW_RAM_DATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define IOPDW_RES_ADDR_8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define IOPDW_RES_ADDR_C 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define IOPDW_RES_ADDR_10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define IOPDW_COMMA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define IOPDW_COMMB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define IOPDW_RES_ADDR_1C 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define IOPDW_SDMA_ADDR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define IOPDW_SDMA_ADDR1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define IOPDW_SDMA_COUNT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define IOPDW_SDMA_ERROR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define IOPDW_RDMA_ADDR0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define IOPDW_RDMA_ADDR1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define IOPDW_RDMA_COUNT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define IOPDW_RDMA_ERROR 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define ADV_CHIP_ID_BYTE 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define ADV_CHIP_ID_WORD 0x04C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define ADV_INTR_ENABLE_HOST_INTR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define ADV_INTR_ENABLE_SEL_INTR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define ADV_INTR_ENABLE_DPR_INTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define ADV_INTR_ENABLE_RTA_INTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define ADV_INTR_ENABLE_RMA_INTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define ADV_INTR_ENABLE_RST_INTR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define ADV_INTR_ENABLE_DPE_INTR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define ADV_INTR_STATUS_INTRA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define ADV_INTR_STATUS_INTRB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define ADV_INTR_STATUS_INTRC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define ADV_RISC_CSR_STOP (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define ADV_RISC_TEST_COND (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define ADV_RISC_CSR_RUN (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define ADV_CTRL_REG_HOST_INTR 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define ADV_CTRL_REG_SEL_INTR 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define ADV_CTRL_REG_DPR_INTR 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define ADV_CTRL_REG_RTA_INTR 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define ADV_CTRL_REG_RMA_INTR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define ADV_CTRL_REG_RES_BIT14 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define ADV_CTRL_REG_DPE_INTR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define ADV_CTRL_REG_POWER_DONE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define ADV_CTRL_REG_ANY_INTR 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define ADV_CTRL_REG_CMD_RESET 0x00C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define ADV_TICKLE_NOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define ADV_TICKLE_A 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define ADV_TICKLE_B 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define ADV_TICKLE_C 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define AdvIsIntPending(port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * SCSI_CFG0 Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define EVEN_PARITY 0x1000 /* Select Even Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define SCAM_EN 0x0080 /* Enable SCAM selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define OUR_ID 0x000F /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * SCSI_CFG1 Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define FILTER_SEL 0x0C00 /* Filter Period Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * Addendum for ASC-38C0800 Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * The ASC-38C1600 Chip uses the same definitions except that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * bus mode override bits [12:10] have been moved to byte register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * and [1:0]. Bits [14], [7:6], [3:2] are unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define HVD 0x1000 /* HVD Device Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define LVD 0x0800 /* LVD Device Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define SE 0x0400 /* SE Device Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define TERM_LVD 0x00C0 /* LVD Termination Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define TERM_SE 0x0030 /* SE Termination Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define CABLE_ILLEGAL_A 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define CABLE_ILLEGAL_B 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * MEM_CFG Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define RAM_SZ_2KB 0x00 /* 2 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define RAM_SZ_4KB 0x04 /* 4 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define RAM_SZ_8KB 0x08 /* 8 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define RAM_SZ_16KB 0x0C /* 16 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define RAM_SZ_32KB 0x10 /* 32 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define RAM_SZ_64KB 0x14 /* 64 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * DMA_CFG0 Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * This register is only accessible to the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define FIFO_THRESH_16B 0x00 /* 16 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define FIFO_THRESH_32B 0x20 /* 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define FIFO_THRESH_48B 0x30 /* 48 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define FIFO_THRESH_64B 0x40 /* 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define FIFO_THRESH_96B 0x60 /* 96 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define FIFO_THRESH_112B 0x70 /* 112 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define START_CTL 0x0C /* DMA start conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define START_CTL_TH 0x00 /* Wait threshold level (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define READ_CMD 0x03 /* Memory Read Method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define READ_CMD_MR 0x00 /* Memory Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define READ_CMD_MRL 0x02 /* Memory Read Long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * ASC-38C0800 RAM BIST Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define RAM_TEST_MODE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define PRE_TEST_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define NORMAL_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define RAM_TEST_DONE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define RAM_TEST_STATUS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define RAM_TEST_HOST_ERROR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define RAM_TEST_INTRAM_ERROR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define RAM_TEST_RISC_ERROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define RAM_TEST_SCSI_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define RAM_TEST_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define PRE_TEST_VALUE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define NORMAL_VALUE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * ASC38C1600 Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * IOPB_PCI_INT_CFG Bit Field Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * Bit 1 can be set to change the interrupt for the Function to operate in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * mode, otherwise the operating mode is undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define TOTEMPOLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * Bit 0 can be used to change the Int Pin for the Function. The value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * 0 by default for both Functions with Function 0 using INT A and Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * INT A is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * value specified in the PCI Configuration Space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define INTAB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * Adv Library Status Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define ADV_TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define ADV_FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define ADV_SUCCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define ADV_BUSY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define ADV_ERROR (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * ADV_DVC_VAR 'warn_code' values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define ADV_MAX_TID 15 /* max. target identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define ADV_MAX_LUN 7 /* max. logical unit number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * Fixed locations of microcode operating variables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define ASC_MC_CHIP_TYPE 0x009A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define ASC_MC_INTRB_CODE 0x009B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define ASC_MC_WDTR_ABLE 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define ASC_MC_SDTR_ABLE 0x009E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define ASC_MC_TAGQNG_ABLE 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define ASC_MC_DISC_ENABLE 0x00A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define ASC_MC_IDLE_CMD_STATUS 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define ASC_MC_IDLE_CMD 0x00A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define ASC_MC_SDTR_DONE 0x00B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define ASC_MC_WDTR_DONE 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define ASC_MC_ICQ 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define ASC_MC_IRQ 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define ASC_MC_PPR_ABLE 0x017A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * BIOS LRAM variable absolute offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define BIOS_CODESEG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define BIOS_CODELEN 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define BIOS_SIGNATURE 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define BIOS_VERSION 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * Microcode Control Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * and handled by the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define HSHK_CFG_WIDE_XFR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define HSHK_CFG_RATE 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define HSHK_CFG_OFFSET 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * All fields here are accessed by the board microcode and need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * little-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) typedef struct adv_carr_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) __le32 carr_va; /* Carrier Virtual Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) __le32 carr_pa; /* Carrier Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * next_vpa [3:1] Reserved Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * next_vpa [0] Done Flag set in Response Queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) __le32 next_vpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) } ADV_CARR_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define ADV_NEXT_VPA_MASK 0xFFFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define ADV_RQ_DONE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define ADV_RQ_GOOD 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define ADV_CQ_STOPPER 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * Each carrier is 64 bytes, and we need three additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * carrier for icq, irq, and the termination carrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define ADV_CARRIER_BUFSIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * Adapter temporary configuration structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * This structure can be discarded after initialization. Don't add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * fields here needed after initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * Field naming convention:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * *_enable indicates the field enables or disables a feature. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * value of the field is never reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) typedef struct adv_dvc_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ushort disc_enable; /* enable disconnection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) uchar chip_version; /* chip version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ushort control_flag; /* Microcode Control Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ushort mcode_date; /* Microcode date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ushort mcode_version; /* Microcode version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ushort serial1; /* EEPROM serial number word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ushort serial2; /* EEPROM serial number word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ushort serial3; /* EEPROM serial number word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) } ADV_DVC_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) struct adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct adv_scsi_req_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) typedef struct adv_sg_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) uchar reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) uchar reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) uchar reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) uchar sg_cnt; /* Valid entries in block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) __le32 sg_ptr; /* Pointer to next sg block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) __le32 sg_addr; /* SG element address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) __le32 sg_count; /* SG element count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) } sg_list[NO_OF_SG_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) } ADV_SG_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * ADV_SCSI_REQ_Q - microcode request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * All fields in this structure up to byte 60 are used by the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * The microcode makes assumptions about the size and ordering of fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * in this structure. Do not change the structure definition here without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * coordinating the change with the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * All fields accessed by microcode must be maintained in little_endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) typedef struct adv_scsi_req_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) uchar target_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) uchar target_id; /* Device target identifier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) uchar target_lun; /* Device target logical unit number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) __le32 data_addr; /* Data buffer physical address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) __le32 data_cnt; /* Data count. Ucode sets to residual. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) __le32 sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) __le32 carr_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) uchar mflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) uchar sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) uchar scsi_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) uchar done_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) uchar scsi_status; /* SCSI status byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) uchar host_status; /* Ucode host status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) uchar sg_working_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) uchar cdb[12]; /* SCSI CDB bytes 0-11. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) __le32 sg_real_addr; /* SG list physical address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) __le32 scsiq_rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) __le32 scsiq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) __le32 carr_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * End of microcode structure - 60 bytes. The rest of the structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * is used by the Adv Library and ignored by the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) u32 srb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) } ADV_SCSI_REQ_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) * The following two structures are used to process Wide Board requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * to the Mid-Level SCSI request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * up to 255 scatter-gather elements may be used per request or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * ADV_SCSI_REQ_Q.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * Both structures must be 32 byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) typedef struct adv_sgblk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ADV_SG_BLOCK sg_block; /* Sgblock structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dma_addr_t sg_addr; /* Physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } adv_sgblk_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) typedef struct adv_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) uchar align[24]; /* Request structure padding. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) dma_addr_t req_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) } adv_req_t __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * Adapter operation variable structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * One structure is required per host adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * Field naming convention:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * *_able indicates both whether a feature should be enabled or disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * and whether a device isi capable of the feature. At initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * this field may be set, but later if a device is found to be incapable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * of the feature, the field is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) typedef struct adv_dvc_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) AdvPortAddr iop_base; /* I/O port address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ushort err_code; /* fatal error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ushort wdtr_able; /* try WDTR for a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ushort sdtr_able; /* try SDTR for a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ushort ultra_able; /* try SDTR Ultra speed for a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) ushort tagqng_able; /* try tagged queuing with a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ushort ppr_able; /* PPR message capable per TID bitmask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) uchar max_dvc_qng; /* maximum number of tagged commands per device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ushort start_motor; /* start motor command allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) uchar chip_no; /* should be assigned by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) uchar max_host_qng; /* maximum number of Q'ed command allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ushort no_scam; /* scam_tolerant of EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) struct asc_board *drv_ptr; /* driver pointer to private structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) uchar chip_scsi_id; /* chip SCSI target ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) uchar chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) uchar bist_err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ADV_CARR_T *carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ADV_CARR_T *carr_freelist; /* Carrier free list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) dma_addr_t carrier_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ushort carr_pending_cnt; /* Count of pending carriers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * Note: The following fields will not be used after initialization. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * driver may discard the buffer after initialization is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) ADV_DVC_CFG *cfg; /* temporary configuration structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) } ADV_DVC_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) * Microcode idle loop commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define IDLE_CMD_COMPLETED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define IDLE_CMD_STOP_CHIP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define IDLE_CMD_SEND_INT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define IDLE_CMD_ABORT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define IDLE_CMD_DEVICE_RESET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define IDLE_CMD_SCSIREQ 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define IDLE_CMD_STATUS_SUCCESS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define IDLE_CMD_STATUS_FAILURE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * AdvSendIdleCmd() flag definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define ADV_NOWAIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) * Wait loop time out values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define SCSI_MAX_RETRY 10 /* retry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /* Read byte from a register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define AdvReadByteRegister(iop_base, reg_off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) (ADV_MEM_READB((iop_base) + (reg_off)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* Write byte to a register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define AdvWriteByteRegister(iop_base, reg_off, byte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /* Read word (2 bytes) from a register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define AdvReadWordRegister(iop_base, reg_off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) (ADV_MEM_READW((iop_base) + (reg_off)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* Write word (2 bytes) to a register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define AdvWriteWordRegister(iop_base, reg_off, word) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Write dword (4 bytes) to a register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* Read byte from LRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define AdvReadByteLram(iop_base, addr, byte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* Write byte to LRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define AdvWriteByteLram(iop_base, addr, byte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /* Read word (2 bytes) from LRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define AdvReadWordLram(iop_base, addr, word) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* Write word (2 bytes) to LRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define AdvWriteWordLram(iop_base, addr, word) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* Write little-endian double word (4 bytes) to LRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* Because of unspecified C language ordering don't use auto-increment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /* Read word (2 bytes) from LRAM assuming that the address is already set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define AdvReadWordAutoIncLram(iop_base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* Write word (2 bytes) to LRAM assuming that the address is already set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define AdvWriteWordAutoIncLram(iop_base, word) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * Define macro to check for Condor signature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * Evaluate to ADV_TRUE if a Condor chip is found the specified port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * address 'iop_base'. Otherwise evalue to ADV_FALSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define AdvFindSignature(iop_base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ADV_CHIP_ID_BYTE) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * Define macro to Return the version number of the chip at 'iop_base'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * The second parameter 'bus_type' is currently unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define AdvGetChipVersion(iop_base, bus_type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) * match the ADV_SCSI_REQ_Q 'srb_tag' field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * If the request has not yet been sent to the device it will simply be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * aborted from RISC memory. If the request is disconnected it will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * aborted on reselection by sending an Abort Message to the target ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * ADV_TRUE(1) - Queue was successfully aborted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * ADV_FALSE(0) - Queue was not found on the active queue list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define AdvAbortQueue(asc_dvc, srb_tag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) (ADV_DCNT) (srb_tag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * Send a Bus Device Reset Message to the specified target ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * All outstanding commands will be purged if sending the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * Bus Device Reset Message is successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) * ADV_TRUE(1) - All requests on the target are purged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * are not purged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define AdvResetDevice(asc_dvc, target_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) (ADV_DCNT) (target_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * SCSI Wide Type definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #define ADV_SCSI_BIT_ID_TYPE ushort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * AdvInitScsiTarget() 'cntl_flag' options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define ADV_SCAN_LUN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define ADV_CAPINFO_NOLUN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) * Convert target id to target id bit mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define QD_NO_STATUS 0x00 /* Request not completed yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) #define QD_NO_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #define QD_ABORTED_BY_HOST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define QD_WITH_ERROR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define QHSTA_NO_ERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define QHSTA_M_SEL_TIMEOUT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define QHSTA_M_DATA_OVER_RUN 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define QHSTA_M_QUEUE_ABORTED 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define QHSTA_M_WTM_TIMEOUT 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* Return the address that is aligned at the next doubleword >= to 'addr'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) * Total contiguous memory needed for driver SG blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * number of scatter-gather elements the driver supports in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * single request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define ADV_SG_LIST_MAX_BYTE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) (sizeof(ADV_SG_BLOCK) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /* struct asc_board flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define ASC_INFO_SIZE 128 /* advansys_info() line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) /* Asc Library return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define ASC_TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define ASC_FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define ASC_NOERROR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define ASC_BUSY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define ASC_ERROR (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* struct scsi_cmnd function return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define STATUS_BYTE(byte) (byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define MSG_BYTE(byte) ((byte) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define HOST_BYTE(byte) ((byte) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define DRIVER_BYTE(byte) ((byte) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #ifndef ADVANSYS_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define ASC_STATS_ADD(shost, counter, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) #else /* ADVANSYS_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define ASC_STATS_ADD(shost, counter, count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #endif /* ADVANSYS_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* If the result wraps when calculating tenths, return 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define ASC_TENTHS(num, den) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * Display a message to the console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define ASC_PRINT(s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) printk("advansys: "); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) printk(s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define ASC_PRINT1(s, a1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) printk("advansys: "); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) printk((s), (a1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define ASC_PRINT2(s, a1, a2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) printk("advansys: "); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) printk((s), (a1), (a2)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define ASC_PRINT3(s, a1, a2, a3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) printk("advansys: "); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) printk((s), (a1), (a2), (a3)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #define ASC_PRINT4(s, a1, a2, a3, a4) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) printk("advansys: "); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) printk((s), (a1), (a2), (a3), (a4)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #ifndef ADVANSYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #define ASC_DBG(lvl, s...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define ASC_DBG_PRT_HEX(lvl, name, start, length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define ASC_DBG_PRT_CDB(lvl, cdb, len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define ASC_DBG_PRT_SENSE(lvl, sense, len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #else /* ADVANSYS_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) * Debugging Message Levels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) * 0: Errors Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * 1: High-Level Tracing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * 2-N: Verbose Tracing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define ASC_DBG(lvl, format, arg...) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (asc_dbglvl >= (lvl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) __func__ , ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (asc_dbglvl >= (lvl)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) asc_prt_scsi_host(s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (asc_dbglvl >= (lvl)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) asc_prt_asc_scsi_q(scsiqp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (asc_dbglvl >= (lvl)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) asc_prt_asc_qdone_info(qdone); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (asc_dbglvl >= (lvl)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) asc_prt_adv_scsi_req_q(scsiqp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (asc_dbglvl >= (lvl)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) asc_prt_hex((name), (start), (length)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #endif /* ADVANSYS_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #ifdef ADVANSYS_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) /* Per board statistics structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) struct asc_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* Driver Entrypoint Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) unsigned int queuecommand; /* # calls to advansys_queuecommand() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) unsigned int reset; /* # calls to advansys_eh_bus_reset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) unsigned int biosparam; /* # calls to advansys_biosparam() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) unsigned int interrupt; /* # advansys_interrupt() calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) unsigned int callback; /* # calls to asc/adv_isr_callback() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) unsigned int done; /* # calls to request's scsi_done function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) unsigned int exe_noerror; /* # ASC_NOERROR returns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) unsigned int exe_busy; /* # ASC_BUSY returns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) unsigned int exe_error; /* # ASC_ERROR returns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) unsigned int exe_unknown; /* # unknown returns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* Data Transfer Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) unsigned int xfer_cnt; /* # I/O requests received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) unsigned int xfer_elem; /* # scatter-gather elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) unsigned int xfer_sect; /* # 512-byte blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #endif /* ADVANSYS_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) * Structure allocated for each board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) * This structure is allocated by scsi_host_alloc() at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) * of the 'Scsi_Host' structure starting at the 'hostdata'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) * field. It is guaranteed to be allocated from DMA-able memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct asc_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) uint flags; /* Board flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ASC_DVC_VAR asc_dvc_var; /* Narrow board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) ADV_DVC_VAR adv_dvc_var; /* Wide board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) } dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) } dvc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ushort asc_n_io_port; /* Number I/O ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) } eep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* /proc/scsi/advansys/[0...] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #ifdef ADVANSYS_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct asc_stats asc_stats; /* Board statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #endif /* ADVANSYS_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * The following fields are used only for Narrow Boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * The following fields are used only for Wide Boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) void __iomem *ioremap_addr; /* I/O Memory remap address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ushort ioport; /* I/O Port address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) adv_req_t *adv_reqp; /* Request structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) dma_addr_t adv_reqp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) size_t adv_reqp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ushort bios_signature; /* BIOS Signature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ushort bios_version; /* BIOS Version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ushort bios_codeseg; /* BIOS Code Segment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ushort bios_codelen; /* BIOS Code Segment Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) dvc_var.asc_dvc_var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) dvc_var.adv_dvc_var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #ifdef ADVANSYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) static int asc_dbglvl = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) * asc_prt_asc_dvc_var()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) (unsigned)h->init_sdtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) (unsigned)h->chip_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) "%u,\n", (unsigned)h->queue_full_or_busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) (unsigned)h->in_critical_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) (unsigned)h->init_state, (unsigned)h->no_scam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) (unsigned)h->pci_fix_asyn_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) printk(" cfg 0x%lx\n", (ulong)h->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) * asc_prt_asc_dvc_cfg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) h->can_tagged_qng, h->cmd_qng_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) h->disc_enable, h->sdtr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) h->isa_dma_channel, h->chip_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) printk(" mcode_date 0x%x, mcode_version %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) h->mcode_date, h->mcode_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) * asc_prt_adv_dvc_var()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) * Display an ADV_DVC_VAR structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) h->carr_freelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) printk(" no_scam 0x%x, tagqng_able 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) (unsigned)h->no_scam, (unsigned)h->tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) (unsigned)h->chip_scsi_id, (ulong)h->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * asc_prt_adv_dvc_cfg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * Display an ADV_DVC_CFG structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) printk(" disc_enable 0x%x, termination 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) h->disc_enable, h->termination);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) printk(" chip_version 0x%x, mcode_date 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) h->chip_version, h->mcode_date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) printk(" mcode_version 0x%x, control_flag 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) h->mcode_version, h->control_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) * asc_prt_scsi_host()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) static void asc_prt_scsi_host(struct Scsi_Host *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) struct asc_board *boardp = shost_priv(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) printk(" host_busy %d, host_no %d,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) scsi_host_busy(s), s->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) (ulong)s->base, (ulong)s->io_port, boardp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) printk(" dma_channel %d, this_id %d, can_queue %d,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) s->dma_channel, s->this_id, s->can_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) * asc_prt_hex()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) * Print hexadecimal output in 4 byte groupings 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) * or 8 double-words per line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static void asc_prt_hex(char *f, uchar *s, int l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) printk("%s: (%d bytes)\n", f, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) for (i = 0; i < l; i += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) /* Display a maximum of 8 double-words per line. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if ((k = (l - i) / 4) >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) k = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) m = (l - i) % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) for (j = 0; j < k; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) printk(" %2.2X%2.2X%2.2X%2.2X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) (unsigned)s[i + (j * 4)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) (unsigned)s[i + (j * 4) + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) (unsigned)s[i + (j * 4) + 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) (unsigned)s[i + (j * 4) + 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) printk(" %2.2X", (unsigned)s[i + (j * 4)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) printk(" %2.2X%2.2X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) (unsigned)s[i + (j * 4)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) (unsigned)s[i + (j * 4) + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) printk(" %2.2X%2.2X%2.2X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) (unsigned)s[i + (j * 4) + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) (unsigned)s[i + (j * 4) + 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) (unsigned)s[i + (j * 4) + 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) * asc_prt_asc_scsi_q()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) ASC_SG_HEAD *sgp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) q->q2.tag_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) (ulong)le32_to_cpu(q->q1.data_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) (ulong)le32_to_cpu(q->q1.data_cnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) (ulong)q->cdbptr, q->q2.cdb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) (ulong)q->sg_head, q->q1.sg_queue_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if (q->sg_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) sgp = q->sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) sgp->queue_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) for (i = 0; i < sgp->entry_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) printk(" [%u]: addr 0x%lx, bytes %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) * asc_prt_asc_qdone_info()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) q->d2.tag_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * asc_prt_adv_sgblock()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * Display an ADV_SG_BLOCK structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) (ulong)b, sgblockno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) printk(" sg_cnt %u, sg_ptr 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (b->sg_ptr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) for (i = 0; i < b->sg_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) (u32)le32_to_cpu(b->sg_list[i].sg_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) * asc_prt_adv_scsi_req_q()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) * Display an ADV_SCSI_REQ_Q structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) int sg_blk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) struct adv_sg_block *sg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) adv_sgblk_t *sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) printk(" target_id %u, target_lun %u, srb_tag 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) q->target_id, q->target_lun, q->srb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) printk(" cntl 0x%x, data_addr 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) q->cntl, (ulong)le32_to_cpu(q->data_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) (ulong)le32_to_cpu(q->data_cnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) q->cdb_len, q->done_status, q->host_status, q->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) printk(" sg_working_ix 0x%x, target_cmd %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) q->sg_working_ix, q->target_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) (ulong)le32_to_cpu(q->scsiq_rptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) /* Display the request's ADV_SG_BLOCK structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (q->sg_list_ptr != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) sg_blk_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) while (sgblkp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) sg_ptr = &sgblkp->sg_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (sg_ptr->sg_ptr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) sgblkp = sgblkp->next_sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) sg_blk_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) #endif /* ADVANSYS_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * advansys_info()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) * Return suitable for printing on the console with the argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) * adapter's configuration information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) * Note: The information line should not exceed ASC_INFO_SIZE bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) * otherwise the static 'info' array will be overrun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static const char *advansys_info(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static char info[ASC_INFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) ASC_DVC_VAR *asc_dvc_varp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) ADV_DVC_VAR *adv_dvc_varp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) char *busname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) char *widename = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) ASC_DBG(1, "begin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) ASC_IS_ISAPNP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) busname = "ISA PnP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) busname = "ISA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) sprintf(info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) ASC_VERSION, busname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) (ulong)shost->io_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) (ulong)shost->io_port + ASC_IOADR_GAP - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) boardp->irq, shost->dma_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (asc_dvc_varp->bus_type & ASC_IS_VL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) busname = "VL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) busname = "EISA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) == ASC_IS_PCI_ULTRA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) busname = "PCI Ultra";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) busname = "PCI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) busname = "?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) shost_printk(KERN_ERR, shost, "unknown bus "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) "type %d\n", asc_dvc_varp->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) sprintf(info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) ASC_VERSION, busname, (ulong)shost->io_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) (ulong)shost->io_port + ASC_IOADR_GAP - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) boardp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) * Wide Adapter Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) * Memory-mapped I/O is used instead of I/O space to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) * the adapter, but display the I/O Port range. The Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) * I/O address is displayed through the driver /proc file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) widename = "Ultra-Wide";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) widename = "Ultra2-Wide";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) widename = "Ultra3-Wide";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) sprintf(info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) BUG_ON(strlen(info) >= ASC_INFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) ASC_DBG(1, "end\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) * asc_prt_board_devices()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) * Print driver information for devices attached to the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) int chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) "\nDevice Information for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) seq_puts(m, "Target IDs Detected:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) seq_printf(m, " %X,", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * Display Wide Board BIOS Information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) ushort major, minor, letter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) seq_puts(m, "\nROM BIOS Version: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) * If the BIOS saved a valid signature, then fill in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) * the BIOS code segment base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (boardp->bios_signature != 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) seq_puts(m, "Disabled or Pre-3.1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) major = (boardp->bios_version >> 12) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) minor = (boardp->bios_version >> 8) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) letter = (boardp->bios_version & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) seq_printf(m, "%d.%d%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) major, minor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) letter >= 26 ? '?' : letter + 'A');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) * Current available ROM BIOS release is 3.1I for UW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) * and 3.2I for U2W. This code doesn't differentiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) * UW and U2W boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) if (major < 3 || (major <= 3 && minor < 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) "ftp://ftp.connectcom.net/pub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) * Add serial number to information bar if signature AAh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) * is found in at bit 15-9 (7 bits) of word 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) * Serial Number consists fo 12 alpha-numeric digits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) * 5 - Product revision (A-J) Word0: " "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) * Signature Word1: 15-9 (7 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) * Note 1: Only production cards will have a serial number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) * Note 2: Signature is most significant 7 bits (0xFE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) ushort w, num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) return ASC_FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) * First word - 6 digits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) w = serialnum[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) /* Product type - 1st digit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /* Product type is P=Prototype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) *cp += 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) cp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) /* Manufacturing location - 2nd digit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) *cp++ = 'A' + ((w & 0x1C00) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* Product ID - 3rd, 4th digits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) num = w & 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) *cp++ = '0' + (num / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) num %= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) *cp++ = '0' + (num / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) /* Product revision - 5th digit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) *cp++ = 'A' + (num % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) * Second word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) w = serialnum[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) * Year - 6th digit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) * If bit 15 of third word is set, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) * last digit of the year is greater than 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (serialnum[2] & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) *cp++ = '8' + ((w & 0x1C0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) *cp++ = '0' + ((w & 0x1C0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) /* Week of year - 7th, 8th digits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) num = w & 0x003F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) *cp++ = '0' + num / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) num %= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) *cp++ = '0' + num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) * Third word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) w = serialnum[2] & 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) /* Serial number - 9th digit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) *cp++ = 'A' + (w / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /* 10th, 11th, 12th digits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) num = w % 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) *cp++ = '0' + num / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) num %= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) *cp++ = '0' + num / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) num %= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) *cp++ = '0' + num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) *cp = '\0'; /* Null Terminate the string. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) return ASC_TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) * asc_prt_asc_board_eeprom()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) * Print board EEPROM configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) ASC_DVC_VAR *asc_dvc_varp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) ASCEEP_CONFIG *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) uchar serialstr[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) ep = &boardp->eep_config.asc_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) == ASC_TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) seq_printf(m, " Serial Number: %s\n", serialstr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) else if (ep->adapter_info[5] == 0xBB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) seq_puts(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) " Default Settings Used for EEPROM-less Adapter.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) seq_puts(m, " Serial Number Signature Not Present.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) ep->max_tag_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) seq_puts(m, " Target ID: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) for (i = 0; i <= ASC_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) seq_printf(m, " %d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) seq_puts(m, "\n Disconnects: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) for (i = 0; i <= ASC_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) seq_puts(m, "\n Command Queuing: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) for (i = 0; i <= ASC_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) seq_puts(m, "\n Start Motor: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) for (i = 0; i <= ASC_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) seq_puts(m, "\n Synchronous Transfer:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) for (i = 0; i <= ASC_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) " Host ISA DMA speed: %d MB/S\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) * asc_prt_adv_board_eeprom()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) * Print board EEPROM configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) ADV_DVC_VAR *adv_dvc_varp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) char *termstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) uchar serialstr[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) ADVEEP_3550_CONFIG *ep_3550 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) ushort *wordp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) ushort sdtr_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) ep_3550 = &boardp->eep_config.adv_3550_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) wordp = &ep_3550->serial_number_word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) wordp = &ep_38C0800->serial_number_word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) wordp = &ep_38C1600->serial_number_word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) seq_printf(m, " Serial Number: %s\n", serialstr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) seq_puts(m, " Serial Number Signature Not Present.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) ep_3550->adapter_scsi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) ep_3550->max_host_qng, ep_3550->max_dvc_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) ep_38C0800->adapter_scsi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) ep_38C0800->max_host_qng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) ep_38C0800->max_dvc_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) ep_38C1600->adapter_scsi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) ep_38C1600->max_host_qng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) ep_38C1600->max_dvc_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) word = ep_3550->termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) word = ep_38C0800->termination_lvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) word = ep_38C1600->termination_lvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) switch (word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) termstr = "Low Off/High Off";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) termstr = "Low Off/High On";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) termstr = "Low On/High On";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) termstr = "Automatic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) " termination: %u (%s), bios_ctrl: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) ep_3550->termination, termstr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) ep_3550->bios_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) " termination: %u (%s), bios_ctrl: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) ep_38C0800->termination_lvd, termstr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) ep_38C0800->bios_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) " termination: %u (%s), bios_ctrl: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) ep_38C1600->termination_lvd, termstr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) ep_38C1600->bios_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) seq_puts(m, " Target ID: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) seq_printf(m, " %X", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) word = ep_3550->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) word = ep_38C0800->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) word = ep_38C1600->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) seq_puts(m, " Disconnects: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) word = ep_3550->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) word = ep_38C0800->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) word = ep_38C1600->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) seq_puts(m, " Command Queuing: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) word = ep_3550->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) word = ep_38C0800->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) word = ep_38C1600->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) seq_puts(m, " Start Motor: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) seq_puts(m, " Synchronous Transfer:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) seq_puts(m, " Ultra Transfer: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) word = ep_3550->wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) word = ep_38C0800->wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) word = ep_38C1600->wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) seq_puts(m, " Wide Transfer: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) for (i = 0; i <= ADV_MAX_TID; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) seq_printf(m, " %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) char *speed_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) sdtr_speed = adv_dvc_varp->sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) } else if (i == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) sdtr_speed = adv_dvc_varp->sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) } else if (i == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) sdtr_speed = adv_dvc_varp->sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) } else if (i == 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) sdtr_speed = adv_dvc_varp->sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) switch (sdtr_speed & ADV_MAX_TID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) speed_str = "Off";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) speed_str = " 5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) speed_str = " 10";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) speed_str = " 20";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) speed_str = " 40";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) speed_str = " 80";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) speed_str = "Unk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) seq_printf(m, "%X:%s ", i, speed_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) if (i == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) seq_puts(m, "\n ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) sdtr_speed >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) * asc_prt_driver_conf()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) int chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) " host_busy %d, max_id %u, max_lun %llu, max_channel %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) scsi_host_busy(shost), shost->max_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) shost->max_lun, shost->max_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) shost->unique_id, shost->can_queue, shost->this_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) shost->sg_tablesize, shost->cmd_per_lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) " unchecked_isa_dma %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) shost->unchecked_isa_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) boardp->flags, shost->last_reset, jiffies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) boardp->asc_n_io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) seq_printf(m, " io_port 0x%lx\n", shost->io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) * asc_prt_asc_board_info()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) * Print dynamic board configuration information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) int chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) ASC_DVC_VAR *v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) ASC_DVC_CFG *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) int renegotiate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) v = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) c = &boardp->dvc_cfg.asc_dvc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) chip_scsi_id = c->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) seq_printf(m, " chip_version %u, mcode_date 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) "mcode_version 0x%x, err_code %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) c->chip_version, c->mcode_date, c->mcode_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) v->err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /* Current number of commands waiting for the host. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) " Total Command Pending: %d\n", v->cur_total_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) seq_puts(m, " Command Queuing:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) seq_printf(m, " %X:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* Current number of commands waiting for a device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) seq_puts(m, "\n Command Queue Pending:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) /* Current limit on number of commands that can be sent to a device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) seq_puts(m, "\n Command Queue Limit:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) /* Indicate whether the device has returned queue full status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) seq_puts(m, "\n Command Queue Full:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) seq_printf(m, " %X:Y-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) i, boardp->queue_full_cnt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) seq_printf(m, " %X:N", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) seq_puts(m, "\n Synchronous Transfer:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) seq_printf(m, " %X:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) uchar syn_period_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) seq_printf(m, " %X:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) seq_puts(m, " Asynchronous");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) syn_period_ix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) " Transfer Period Factor: %d (%d.%d Mhz),",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) v->sdtr_period_tbl[syn_period_ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) 250 / v->sdtr_period_tbl[syn_period_ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) ASC_TENTHS(250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) v->sdtr_period_tbl[syn_period_ix]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) seq_printf(m, " REQ/ACK Offset: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) seq_puts(m, "*\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) renegotiate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) if (renegotiate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) seq_puts(m, " * = Re-negotiation pending before next command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) * asc_prt_adv_board_info()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) * Print dynamic board configuration information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) ADV_DVC_VAR *v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) ADV_DVC_CFG *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) ushort chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) ushort lramword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) uchar lrambyte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) ushort tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) ushort sdtr_able, wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) ushort wdtr_done, sdtr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) ushort period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) int renegotiate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) v = &boardp->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) c = &boardp->dvc_cfg.adv_dvc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) iop_base = v->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) chip_scsi_id = v->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) " iop_base 0x%p, cable_detect: %X, err_code %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) v->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) v->err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) seq_printf(m, " chip_version %u, mcode_date 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) "mcode_version 0x%x\n", c->chip_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) c->mcode_date, c->mcode_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) seq_puts(m, " Queuing Enabled:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) seq_printf(m, " %X:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) seq_puts(m, "\n Queue Limit:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) lrambyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) seq_printf(m, " %X:%d", i, lrambyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) seq_puts(m, "\n Command Pending:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) lrambyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) seq_printf(m, " %X:%d", i, lrambyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) seq_puts(m, " Wide Enabled:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) seq_printf(m, " %X:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) seq_puts(m, " Transfer Bit Width:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) AdvReadWordLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) lramword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) seq_printf(m, " %X:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) i, (lramword & 0x8000) ? 16 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) seq_putc(m, '*');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) renegotiate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) seq_puts(m, " Synchronous Enabled:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) seq_printf(m, " %X:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) for (i = 0; i <= ADV_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) AdvReadWordLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) lramword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) lramword &= ~0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) if ((chip_scsi_id == i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) seq_printf(m, " %X:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) seq_puts(m, " Asynchronous");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) seq_puts(m, " Transfer Period Factor: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) seq_puts(m, "9 (80.0 Mhz),");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) seq_puts(m, "10 (40.0 Mhz),");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) } else { /* 20 Mhz or below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) period = (((lramword >> 8) * 25) + 50) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) if (period == 0) { /* Should never happen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) seq_printf(m, "%d (? Mhz), ", period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) "%d (%d.%d Mhz),",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) period, 250 / period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) ASC_TENTHS(250, period));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) seq_printf(m, " REQ/ACK Offset: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) lramword & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) seq_puts(m, "*\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) renegotiate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) if (renegotiate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) seq_puts(m, " * = Re-negotiation pending before next command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) #ifdef ADVANSYS_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) * asc_prt_board_stats()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) struct asc_stats *s = &boardp->asc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) shost->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) s->queuecommand, s->reset, s->biosparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) s->interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) s->callback, s->done, s->build_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) s->adv_build_noreq, s->adv_build_nosg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) s->exe_noerror, s->exe_busy, s->exe_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) s->exe_unknown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) * Display data transfer statistics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) if (s->xfer_cnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) s->xfer_cnt, s->xfer_elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) seq_printf(m, "xfer_bytes %u.%01u kb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) /* Scatter gather transfer statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) seq_printf(m, " avg_num_elem %u.%01u, ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) s->xfer_elem / s->xfer_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) seq_printf(m, "avg_elem_size %u.%01u kb, ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) (s->xfer_sect / 2) / s->xfer_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) seq_printf(m, "avg_xfer_size %u.%01u kb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) (s->xfer_sect / 2) / s->xfer_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) #endif /* ADVANSYS_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) * m: seq_file to print into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) * shost: Scsi_Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) * Return the number of bytes read from or written to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) * /proc/scsi/advansys/[0...] file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) ASC_DBG(1, "begin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) * User read of /proc/scsi/advansys/[0...] file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) * Get board configuration information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) * advansys_info() returns the board string from its own static buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) /* Copy board information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) seq_printf(m, "%s\n", (char *)advansys_info(shost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) * Display Wide Board BIOS Information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) if (!ASC_NARROW_BOARD(boardp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) asc_prt_adv_bios(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) * Display driver information for each device attached to the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) asc_prt_board_devices(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) * Display EEPROM configuration for the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) if (ASC_NARROW_BOARD(boardp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) asc_prt_asc_board_eeprom(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) asc_prt_adv_board_eeprom(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) * Display driver configuration and information for the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) asc_prt_driver_conf(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) #ifdef ADVANSYS_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) * Display driver statistics for the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) asc_prt_board_stats(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) #endif /* ADVANSYS_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) * Display Asc Library dynamic configuration information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) * for the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) if (ASC_NARROW_BOARD(boardp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) asc_prt_asc_board_info(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) asc_prt_adv_board_info(m, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) #endif /* CONFIG_PROC_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) static void asc_scsi_done(struct scsi_cmnd *scp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) scsi_dma_unmap(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) ASC_STATS(scp->device->host, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) scp->scsi_done(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) static void AscSetBank(PortAddr iop_base, uchar bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) uchar val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) val = AscGetChipControl(iop_base) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) (~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) CC_CHIP_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) if (bank == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) val |= CC_BANK_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) } else if (bank == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) val |= CC_DIAG | CC_BANK_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) val &= ~CC_BANK_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) AscSetChipControl(iop_base, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) AscSetBank(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) AscWriteChipIH(iop_base, ins_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) AscSetBank(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) static int AscStartChip(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) AscSetChipControl(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) static bool AscStopChip(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) uchar cc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) cc_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) AscGetChipControl(iop_base) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) AscSetChipIH(iop_base, INS_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) AscSetChipIH(iop_base, INS_RFLAG_WTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) static bool AscIsChipHalted(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) int i = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) && (i-- > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) AscStopChip(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) udelay(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) AscSetChipIH(iop_base, INS_RFLAG_WTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) AscSetChipIH(iop_base, INS_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) AscSetChipControl(iop_base, CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) mdelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) AscSetChipStatus(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) return (AscIsChipHalted(iop_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) static int AscFindSignature(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) ushort sig_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) iop_base, AscGetChipSignatureByte(iop_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) iop_base, AscGetChipSignatureWord(iop_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) sig_word = AscGetChipSignatureWord(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) if ((sig_word == (ushort)ASC_1000_ID0W) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) static void AscEnableInterrupt(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) ushort cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) cfg = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) static void AscDisableInterrupt(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) ushort cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) cfg = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) unsigned char byte_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) unsigned short word_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) if (isodd_word(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) AscSetChipLramAddr(iop_base, addr - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) word_data = AscGetChipLramData(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) byte_data = (word_data >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) AscSetChipLramAddr(iop_base, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) word_data = AscGetChipLramData(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) byte_data = word_data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) return byte_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) ushort word_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) AscSetChipLramAddr(iop_base, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) word_data = AscGetChipLramData(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) return (word_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) AscSetChipLramAddr(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) for (i = 0; i < words; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) AscSetChipLramData(iop_base, set_wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) AscSetChipLramAddr(iop_base, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) AscSetChipLramData(iop_base, word_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) ushort word_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) if (isodd_word(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) addr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) word_data = AscReadLramWord(iop_base, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) word_data &= 0x00FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) word_data |= (((ushort)byte_val << 8) & 0xFF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) word_data = AscReadLramWord(iop_base, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) word_data &= 0xFF00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) word_data |= ((ushort)byte_val & 0x00FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) AscWriteLramWord(iop_base, addr, word_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) * Copy 2 bytes to LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) * The source data is assumed to be in little-endian order in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) * and is maintained in little-endian order when written to LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) const uchar *s_buffer, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) AscSetChipLramAddr(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) for (i = 0; i < 2 * words; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) * On a little-endian system the second argument below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) * produces a little-endian ushort which is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) * LRAM in little-endian order. On a big-endian system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) * the second argument produces a big-endian ushort which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) * is "transparently" byte-swapped by outpw() and written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) * in little-endian order to LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) outpw(iop_base + IOP_RAM_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) * Copy 4 bytes to LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) * The source data is assumed to be in little-endian order in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) * and is maintained in little-endian order when written to LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) AscMemDWordCopyPtrToLram(PortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) ushort s_addr, uchar *s_buffer, int dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) AscSetChipLramAddr(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) for (i = 0; i < 4 * dwords; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) * Copy 2 bytes from LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) * The source data is assumed to be in little-endian order in LRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) * and is maintained in little-endian order when written to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) AscMemWordCopyPtrFromLram(PortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) ushort s_addr, uchar *d_buffer, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) AscSetChipLramAddr(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) for (i = 0; i < 2 * words; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) word = inpw(iop_base + IOP_RAM_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) d_buffer[i] = word & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) d_buffer[i + 1] = (word >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) u32 sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) for (i = 0; i < words; i++, s_addr += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) sum += AscReadLramWord(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) return (sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) static void AscInitLram(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) uchar i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) ushort s_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) 64) >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) i = ASC_MIN_ACTIVE_QNO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) (uchar)(i + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) (uchar)(asc_dvc->max_total_qng));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) (uchar)i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) s_addr += ASC_QBLK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) (uchar)(i + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) (uchar)(i - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) (uchar)i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) (uchar)ASC_QLINK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) (uchar)(asc_dvc->max_total_qng - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) (uchar)asc_dvc->max_total_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) s_addr += ASC_QBLK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) i++, s_addr += ASC_QBLK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) const uchar *mcode_buf, ushort mcode_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) u32 chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) ushort mcode_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) ushort mcode_chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) /* Write the microcode buffer starting at LRAM address 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) mcode_word_size = (ushort)(mcode_size >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) (ushort)ASC_CODE_SEC_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) (ushort)((mcode_size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) s_addr - (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) ASC_CODE_SEC_BEG) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) return chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) ushort lram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) AscPutRiscVarFreeQHead(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) AscPutVarFreeQHead(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) (uchar)((int)asc_dvc->max_total_qng + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) (uchar)((int)asc_dvc->max_total_qng + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) asc_dvc->max_total_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) AscPutQDoneInProgress(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) lram_addr = ASC_QADR_BEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) for (i = 0; i < 32; i++, lram_addr += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) AscWriteLramWord(iop_base, lram_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) int warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) __le32 phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) __le32 phy_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) struct asc_board *board = asc_dvc_to_board(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) AscPutMCodeInitSDTRAtID(iop_base, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) asc_dvc->cfg->sdtr_period_offset[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) AscInitQLinkVar(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) asc_dvc->cfg->disc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) /* Ensure overrun buffer is aligned on an 8 byte boundary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) warn_code = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) goto err_dma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) (uchar *)&phy_addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) (uchar *)&phy_size, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) asc_dvc->cfg->mcode_date =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) asc_dvc->cfg->mcode_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) warn_code = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) goto err_mcode_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (AscStartChip(iop_base) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) warn_code = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) goto err_mcode_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) err_mcode_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) dma_unmap_single(board->dev, asc_dvc->overrun_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) err_dma_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) asc_dvc->overrun_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) const char fwname[] = "advansys/mcode.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) unsigned long chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) int warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) AscResetChipAndScsiBus(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) if (!AscFindSignature(asc_dvc->iop_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) AscDisableInterrupt(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) AscInitLram(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) fwname, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) if (fw->size < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) fw->size, fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) (fw->data[1] << 8) | fw->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) fw->size - 4) != chksum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) warn_code |= AscInitMicroCodeVar(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) if (!asc_dvc->overrun_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) AscEnableInterrupt(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) * Load the Microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) * Write the microcode image to RISC memory starting at address 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) * The microcode is stored compressed in the following format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) * 254 word (508 byte) table indexed by byte code followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) * by the following byte codes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) * 1-Byte Code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) * 00: Emit word 0 in table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) * 01: Emit word 1 in table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) * FD: Emit word 253 in table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) * Multi-Byte Code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) * Returns 0 or an error if the checksum doesn't match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) int size, int memsize, int chksum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) int i, j, end, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) u32 sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) for (i = 253 * 2; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) if (buf[i] == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) for (j = 0; j < buf[i + 1]; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) AdvWriteWordAutoIncLram(iop_base, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) len += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) i += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) } else if (buf[i] == 0xfe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) AdvWriteWordAutoIncLram(iop_base, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) i += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) len += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) unsigned int off = buf[i] * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) unsigned short word = (buf[off + 1] << 8) | buf[off];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) AdvWriteWordAutoIncLram(iop_base, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) len += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) end = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) while (len < memsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) AdvWriteWordAutoIncLram(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) len += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) /* Verify the microcode checksum. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) for (len = 0; len < end; len += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) sum += AdvReadWordAutoIncLram(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) if (sum != chksum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) return ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) off_t carr_offset = 0, next_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) dma_addr_t carr_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) for (i = 0; i < carr_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) carr_offset = i * sizeof(ADV_CARR_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) /* Get physical address of the carrier 'carrp'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) carr_paddr = adv_dvc->carrier_addr + carr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) adv_dvc->carrier[i].areq_vpa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) next_offset = carr_offset + sizeof(ADV_CARR_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) if (i == carr_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) next_offset = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) * We cannot have a carrier with 'carr_va' of '0', as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) * a reference to this carrier would be interpreted as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) * list termination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) * So start at carrier 1 with the freelist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) adv_dvc->carr_freelist = &adv_dvc->carrier[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) BUG_ON(offset > ADV_CARRIER_BUFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) index = offset / sizeof(ADV_CARR_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) return &adv_dvc->carrier[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) ADV_CARR_T *carrp = adv_dvc->carr_freelist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) u32 next_vpa = le32_to_cpu(carrp->next_vpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) if (next_vpa == 0 || next_vpa == ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) * insert stopper carrier to terminate list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) return carrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) * 'offset' is the index in the request pointer array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) struct asc_board *boardp = adv_dvc->drv_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) BUG_ON(offset > adv_dvc->max_host_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) return &boardp->adv_reqp[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) * Send an idle command to the chip and wait for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) * Command completion is polled for once per microsecond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) * The function can be called from anywhere including an interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) * functions to prevent reentrancy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) * Return Values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) * ADV_TRUE - command completed successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) * ADV_FALSE - command failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) * ADV_ERROR - command timed out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) ushort idle_cmd, u32 idle_cmd_parameter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) int result, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) * Clear the idle command status which is set by the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) * to a non-zero value to indicate when the command is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) * The non-zero result is one of the IDLE_CMD_STATUS_* values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) * Write the idle command value after the idle command parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) * has been written to avoid a race condition. If the order is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) * followed, the microcode may process the idle command before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) * parameters have been written to LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) cpu_to_le32(idle_cmd_parameter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * Tickle the RISC to tell it to process the idle command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) * Clear the tickle value. In the ASC-3550 the RISC flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) * command 'clr_tickle_b' does not work unless the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) * value is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) /* Wait for up to 100 millisecond for the idle command to timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) /* Poll once each microsecond for command completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) for (j = 0; j < SCSI_US_PER_MSEC; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) BUG(); /* The idle command should never timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) * Reset SCSI Bus and purge all outstanding requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) * ADV_FALSE(0) - Microcode command failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) * may be hung which requires driver recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) * Send the SCSI Bus Reset idle start idle command which asserts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) * the SCSI Bus Reset signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) if (status != ADV_TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) * Delay for the specified SCSI Bus Reset hold time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) * The hold time delay is done on the host because the RISC has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) * microsecond accurate timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) udelay(ASC_SCSI_RESET_HOLD_TIME_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) * Send the SCSI Bus Reset end idle command which de-asserts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) * the SCSI Bus Reset signal and purges any pending requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) if (status != ADV_TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) * Initialize the ASC-3550.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) * Needed after initialization for error recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) const char fwname[] = "advansys/3550.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) int begin_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) int end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) ushort code_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) int word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) unsigned long chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) ushort scsi_cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) uchar tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) ushort wdtr_able = 0, sdtr_able, tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) uchar max_cmd[ADV_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) /* If there is already an error, don't continue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) * Save the RISC memory BIOS region before writing the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) * The BIOS may already be loaded and using its RISC LRAM region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) * so its region must be saved and restored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) * Note: This code makes the assumption, which is currently true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) * that a chip reset does not clear RISC LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) bios_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) * Save current per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) ushort bios_version, major, minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) bios_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) major = (bios_version >> 12) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) minor = (bios_version >> 8) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) if (major < 3 || (major == 3 && minor == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) AdvReadWordLram(iop_base, 0x120, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) fwname, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) if (fw->size < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) fw->size, fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) (fw->data[1] << 8) | fw->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) fw->size - 4, ADV_3550_MEMSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) if (asc_dvc->err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) * Restore the RISC memory BIOS region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) bios_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) * Calculate and write the microcode code checksum to the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) code_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) for (word = begin_addr; word < end_addr; word += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) code_sum += AdvReadWordAutoIncLram(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) * Read and save microcode version and date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) asc_dvc->cfg->mcode_date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) asc_dvc->cfg->mcode_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) * Set the chip type to indicate the ASC3550.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) * If the PCI Configuration Command Register "Parity Error Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) * Control" Bit was clear (0), then set the microcode variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) * to ignore DMA parity errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) word |= CONTROL_FLAG_IGNORE_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) * threshold of 128 bytes. This register is only accessible to the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) START_CTL_EMFU | READ_CMD_MRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) * Microcode operating variables for WDTR, SDTR, and command tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) * queuing will be set in slave_configure() based on what a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) * device reports it is capable of in Inquiry byte 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) * If SCSI Bus Resets have been disabled, then directly set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) * SDTR and WDTR from the EEPROM configuration. This will allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) * the BIOS and warm boot to work without a SCSI bus hang on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) * the Inquiry caused by host and target mismatched DTR values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) * Without the SCSI Bus Reset, before an Inquiry a device can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) * be assumed to be in Asynchronous, Narrow mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) asc_dvc->wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) asc_dvc->sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) * bitmask. These values determine the maximum SDTR speed negotiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) * with a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) * without determining here whether the device supports SDTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) * 4-bit speed SDTR speed name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) * =========== ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) * 0000b (0x0) SDTR disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) * 0001b (0x1) 5 Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) * 0010b (0x2) 10 Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) * 0011b (0x3) 20 Mhz (Ultra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) * 0100b (0x4) 40 Mhz (LVD/Ultra2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) * 0110b (0x6) Undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) * .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) * 1111b (0xF) Undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) /* Set Ultra speed for TID 'tid'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) word |= (0x3 << (4 * (tid % 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) /* Set Fast speed for TID 'tid'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) word |= (0x2 << (4 * (tid % 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) if (tid == 3) { /* Check if done with sdtr_speed1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) } else if (tid == 7) { /* Check if done with sdtr_speed2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) } else if (tid == 11) { /* Check if done with sdtr_speed3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) } else if (tid == 15) { /* Check if done with sdtr_speed4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) /* End of loop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) * Set microcode operating variable for the disconnect per TID bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) asc_dvc->cfg->disc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) * Set SCSI_CFG0 Microcode Default Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) * The microcode will set the SCSI_CFG0 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) asc_dvc->chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) * Determine SCSI_CFG1 Microcode Default Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) * The microcode will set the SCSI_CFG1 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) /* Read current SCSI_CFG1 Register value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) * If all three connectors are in use, return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) * If the internal narrow cable is reversed all of the SCSI_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) * register signals will be set. Check for and return an error if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) * this condition is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) * If this is a differential board and a single-ended device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) * is attached to one of the connectors, return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) * If automatic termination control is enabled, then set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) * termination value based on a table listed in a_condor.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) * If manual termination was specified with an EEPROM setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) * is ready to be 'ored' into SCSI_CFG1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) if (asc_dvc->cfg->termination == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) * The software always controls termination by setting TERM_CTL_SEL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) * If TERM_CTL_SEL were set to 0, the hardware would set termination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) asc_dvc->cfg->termination |= TERM_CTL_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) switch (scsi_cfg1 & CABLE_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) /* TERM_CTL_H: on, TERM_CTL_L: on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) case 0x7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) case 0xB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) case 0xD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) case 0xE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) case 0xF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) /* TERM_CTL_H: on, TERM_CTL_L: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) case 0x5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) case 0x9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) case 0xA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) case 0xC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) asc_dvc->cfg->termination |= TERM_CTL_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) /* TERM_CTL_H: off, TERM_CTL_L: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) case 0x6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) * Clear any set TERM_CTL_H and TERM_CTL_L bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) scsi_cfg1 &= ~TERM_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) * Invert the TERM_CTL_H and TERM_CTL_L bits and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) * set 'scsi_cfg1'. The TERM_POL bit does not need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) * referenced, because the hardware internally inverts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) * the Termination High and Low bits if TERM_POL is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) * Set SCSI_CFG1 Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) * Set filter value and possibly modified termination control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) * bits in the Microcode SCSI_CFG1 Register Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) * The microcode will set the SCSI_CFG1 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) FLTR_DISABLE | scsi_cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) * Set MEM_CFG Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) * The microcode will set the MEM_CFG register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) * MEM_CFG may be accessed as a word or byte, but only bits 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) * are defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) * ASC-3550 has 8KB internal memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) BIOS_EN | RAM_SZ_8KB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) * Set SEL_MASK Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) * The microcode will set the SEL_MASK register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) AdvBuildCarrierFreelist(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) * Set-up the Host->RISC Initiator Command Queue (ICQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) if (!asc_dvc->icq_sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) * Set RISC ICQ physical address start value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) * Set-up the RISC->Host Initiator Response Queue (IRQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) if (!asc_dvc->irq_sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) * Set RISC IRQ physical address start value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) asc_dvc->carr_pending_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) (ADV_INTR_ENABLE_HOST_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) ADV_INTR_ENABLE_GLOBAL_INTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) AdvWriteWordRegister(iop_base, IOPW_PC, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) /* finally, finally, gentlemen, start your engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) * Resets should be performed. The RISC has to be running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) * to issue a SCSI Bus Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) * If the BIOS Signature is present in memory, restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) * BIOS Handshake Configuration Table and do not perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) * a SCSI Bus Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) * Restore per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) AdvWriteByteLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) if (AdvResetSB(asc_dvc) != ADV_TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) warn_code = ASC_WARN_BUSRESET_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) * Initialize the ASC-38C0800.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) * Needed after initialization for error recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) const char fwname[] = "advansys/38C0800.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) int begin_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) int end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) ushort code_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) int word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) unsigned long chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) ushort scsi_cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) uchar byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) uchar tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) ushort wdtr_able, sdtr_able, tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) uchar max_cmd[ADV_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) /* If there is already an error, don't continue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) * Save the RISC memory BIOS region before writing the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) * The BIOS may already be loaded and using its RISC LRAM region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) * so its region must be saved and restored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) * Note: This code makes the assumption, which is currently true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) * that a chip reset does not clear RISC LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) bios_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) * Save current per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) * RAM BIST (RAM Built-In Self Test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) * Address : I/O base + offset 0x38h register (byte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) * Function: Bit 7-6(RW) : RAM mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) * Normal Mode : 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) * Pre-test Mode : 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) * RAM Test Mode : 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) * Bit 5 : unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) * Bit 4(RO) : Done bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) * Bit 3-0(RO) : Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) * Host Error : 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) * Int_RAM Error : 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) * RISC Error : 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) * SCSI Error : 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) * No Error : 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) * Note: RAM BIST code should be put right here, before loading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) * microcode and after saving the RISC memory BIOS region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) * LRAM Pre-test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) * to NORMAL_MODE, return an error too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) mdelay(10); /* Wait for 10ms before reading back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) if ((byte & RAM_TEST_DONE) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) || (byte & 0x0F) != PRE_TEST_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) mdelay(10); /* Wait for 10ms before reading back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) != NORMAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) * LRAM Test - It takes about 1.5 ms to run through the test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) * If Done bit not set or Status not 0, save register byte, set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) * err_code, and return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) mdelay(10); /* Wait for 10ms before checking status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) /* Get here if Done bit not set or Status not 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) asc_dvc->bist_err_code = byte; /* for BIOS display message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) /* We need to reset back to normal mode after LRAM test passes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) fwname, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) if (fw->size < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) fw->size, fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) (fw->data[1] << 8) | fw->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) fw->size - 4, ADV_38C0800_MEMSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) if (asc_dvc->err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) * Restore the RISC memory BIOS region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) bios_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) * Calculate and write the microcode code checksum to the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) code_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) for (word = begin_addr; word < end_addr; word += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) code_sum += AdvReadWordAutoIncLram(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) * Read microcode version and date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) asc_dvc->cfg->mcode_date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) asc_dvc->cfg->mcode_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) * Set the chip type to indicate the ASC38C0800.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) * cable detection and then we are able to read C_DET[3:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) * Microcode Default Value' section below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) scsi_cfg1 | DIS_TERM_DRV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) * If the PCI Configuration Command Register "Parity Error Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) * Control" Bit was clear (0), then set the microcode variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) * to ignore DMA parity errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) word |= CONTROL_FLAG_IGNORE_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) * bits for the default FIFO threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) * For DMA Errata #4 set the BC_THRESH_ENB bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) READ_CMD_MRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) * Microcode operating variables for WDTR, SDTR, and command tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) * queuing will be set in slave_configure() based on what a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) * device reports it is capable of in Inquiry byte 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) * If SCSI Bus Resets have been disabled, then directly set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) * SDTR and WDTR from the EEPROM configuration. This will allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) * the BIOS and warm boot to work without a SCSI bus hang on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) * the Inquiry caused by host and target mismatched DTR values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) * Without the SCSI Bus Reset, before an Inquiry a device can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) * be assumed to be in Asynchronous, Narrow mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) asc_dvc->wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) asc_dvc->sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) * Set microcode operating variables for DISC and SDTR_SPEED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) * configuration values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) * without determining here whether the device supports SDTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) asc_dvc->cfg->disc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) * Set SCSI_CFG0 Microcode Default Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) * The microcode will set the SCSI_CFG0 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) asc_dvc->chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) * Determine SCSI_CFG1 Microcode Default Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) * The microcode will set the SCSI_CFG1 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) /* Read current SCSI_CFG1 Register value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) * If the internal narrow cable is reversed all of the SCSI_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) * register signals will be set. Check for and return an error if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) * this condition is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) * All kind of combinations of devices attached to one of four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) * connectors are acceptable except HVD device attached. For example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) * LVD device can be attached to SE connector while SE device attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) * to LVD connector. If LVD device attached to SE connector, it only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) * runs up to Ultra speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) * If an HVD device is attached to one of LVD connectors, return an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) * error. However, there is no way to detect HVD device attached to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) * SE connectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) if (scsi_cfg1 & HVD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) * If either SE or LVD automatic termination control is enabled, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) * set the termination value based on a table listed in a_condor.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) * If manual termination was specified with an EEPROM setting then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) * to be 'ored' into SCSI_CFG1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) /* SE automatic termination control is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) switch (scsi_cfg1 & C_DET_SE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) /* TERM_SE_HI: on, TERM_SE_LO: on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) asc_dvc->cfg->termination |= TERM_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) /* TERM_SE_HI: on, TERM_SE_LO: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) asc_dvc->cfg->termination |= TERM_SE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) /* LVD automatic termination control is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) switch (scsi_cfg1 & C_DET_LVD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) /* TERM_LVD_HI: on, TERM_LVD_LO: on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) case 0x8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) case 0xC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) asc_dvc->cfg->termination |= TERM_LVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) /* TERM_LVD_HI: off, TERM_LVD_LO: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) * Clear any set TERM_SE and TERM_LVD bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) * bits and set possibly modified termination control bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) * Microcode SCSI_CFG1 Register Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) * Set SCSI_CFG1 Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) * Set possibly modified termination control and reset DIS_TERM_DRV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) * bits in the Microcode SCSI_CFG1 Register Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) * The microcode will set the SCSI_CFG1 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) * Set MEM_CFG Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) * The microcode will set the MEM_CFG register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) * MEM_CFG may be accessed as a word or byte, but only bits 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) * are defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) * ASC-38C0800 has 16KB internal memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) BIOS_EN | RAM_SZ_16KB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) * Set SEL_MASK Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) * The microcode will set the SEL_MASK register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) AdvBuildCarrierFreelist(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) * Set-up the Host->RISC Initiator Command Queue (ICQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) if (!asc_dvc->icq_sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) ASC_DBG(0, "Failed to get ICQ carrier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) * Set RISC ICQ physical address start value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) * carr_pa is LE, must be native before write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) * Set-up the RISC->Host Initiator Response Queue (IRQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) if (!asc_dvc->irq_sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) ASC_DBG(0, "Failed to get IRQ carrier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) * Set RISC IRQ physical address start value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) * carr_pa is LE, must be native before write *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) asc_dvc->carr_pending_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) (ADV_INTR_ENABLE_HOST_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) ADV_INTR_ENABLE_GLOBAL_INTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) AdvWriteWordRegister(iop_base, IOPW_PC, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) /* finally, finally, gentlemen, start your engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) * Resets should be performed. The RISC has to be running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) * to issue a SCSI Bus Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) * If the BIOS Signature is present in memory, restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) * BIOS Handshake Configuration Table and do not perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) * a SCSI Bus Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) * Restore per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) AdvWriteByteLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) if (AdvResetSB(asc_dvc) != ADV_TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) warn_code = ASC_WARN_BUSRESET_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) * Initialize the ASC-38C1600.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) * Needed after initialization for error recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) const char fwname[] = "advansys/38C1600.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) int begin_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) int end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) ushort code_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) long word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) unsigned long chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) ushort scsi_cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) uchar byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) uchar tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) uchar max_cmd[ASC_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) /* If there is already an error, don't continue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) if (asc_dvc->err_code != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) * Save the RISC memory BIOS region before writing the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) * The BIOS may already be loaded and using its RISC LRAM region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) * so its region must be saved and restored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) * Note: This code makes the assumption, which is currently true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) * that a chip reset does not clear RISC LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) bios_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) * Save current per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) for (tid = 0; tid <= ASC_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) * RAM BIST (Built-In Self Test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) * Address : I/O base + offset 0x38h register (byte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) * Function: Bit 7-6(RW) : RAM mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) * Normal Mode : 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) * Pre-test Mode : 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) * RAM Test Mode : 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) * Bit 5 : unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) * Bit 4(RO) : Done bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) * Bit 3-0(RO) : Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) * Host Error : 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) * Int_RAM Error : 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) * RISC Error : 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) * SCSI Error : 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) * No Error : 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) * Note: RAM BIST code should be put right here, before loading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) * microcode and after saving the RISC memory BIOS region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) * LRAM Pre-test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) * to NORMAL_MODE, return an error too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) mdelay(10); /* Wait for 10ms before reading back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) if ((byte & RAM_TEST_DONE) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) || (byte & 0x0F) != PRE_TEST_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) mdelay(10); /* Wait for 10ms before reading back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) != NORMAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) * LRAM Test - It takes about 1.5 ms to run through the test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) * If Done bit not set or Status not 0, save register byte, set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) * err_code, and return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) mdelay(10); /* Wait for 10ms before checking status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) /* Get here if Done bit not set or Status not 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) asc_dvc->bist_err_code = byte; /* for BIOS display message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) /* We need to reset back to normal mode after LRAM test passes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) fwname, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) if (fw->size < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) fw->size, fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) (fw->data[1] << 8) | fw->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) fw->size - 4, ADV_38C1600_MEMSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) if (asc_dvc->err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) * Restore the RISC memory BIOS region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) bios_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) * Calculate and write the microcode code checksum to the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) code_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) for (word = begin_addr; word < end_addr; word += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) code_sum += AdvReadWordAutoIncLram(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) * Read microcode version and date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) asc_dvc->cfg->mcode_date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) asc_dvc->cfg->mcode_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) * Set the chip type to indicate the ASC38C1600.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) * cable detection and then we are able to read C_DET[3:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) * Microcode Default Value' section below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) scsi_cfg1 | DIS_TERM_DRV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) * If the PCI Configuration Command Register "Parity Error Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) * Control" Bit was clear (0), then set the microcode variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) * to ignore DMA parity errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) word |= CONTROL_FLAG_IGNORE_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) * If the BIOS control flag AIPP (Asynchronous Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) * Phase Protection) disable bit is not set, then set the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) * AIPP checking and encoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) word |= CONTROL_FLAG_ENABLE_AIPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) * and START_CTL_TH [3:2].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) * Microcode operating variables for WDTR, SDTR, and command tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) * queuing will be set in slave_configure() based on what a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) * device reports it is capable of in Inquiry byte 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) * If SCSI Bus Resets have been disabled, then directly set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) * SDTR and WDTR from the EEPROM configuration. This will allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) * the BIOS and warm boot to work without a SCSI bus hang on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) * the Inquiry caused by host and target mismatched DTR values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) * Without the SCSI Bus Reset, before an Inquiry a device can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) * be assumed to be in Asynchronous, Narrow mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) asc_dvc->wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) asc_dvc->sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) * Set microcode operating variables for DISC and SDTR_SPEED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) * configuration values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) * without determining here whether the device supports SDTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) asc_dvc->cfg->disc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) * Set SCSI_CFG0 Microcode Default Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) * The microcode will set the SCSI_CFG0 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) asc_dvc->chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) * Calculate SCSI_CFG1 Microcode Default Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) * The microcode will set the SCSI_CFG1 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) * Each ASC-38C1600 function has only two cable detect bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) * The bus mode override bits are in IOPB_SOFT_OVER_WR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) * If the cable is reversed all of the SCSI_CTRL register signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) * will be set. Check for and return an error if this condition is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) * found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) * Each ASC-38C1600 function has two connectors. Only an HVD device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) * can not be connected to either connector. An LVD device or SE device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) * may be connected to either connecor. If an SE device is connected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) * then at most Ultra speed (20 Mhz) can be used on both connectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) * If an HVD device is attached, return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) if (scsi_cfg1 & HVD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) * Each function in the ASC-38C1600 uses only the SE cable detect and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) * termination because there are two connectors for each function. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) * function may use either LVD or SE mode. Corresponding the SE automatic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) * termination control EEPROM bits are used for each function. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) * function has its own EEPROM. If SE automatic control is enabled for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) * the function, then set the termination value based on a table listed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) * in a_condor.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) * If manual termination is specified in the EEPROM for the function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) * ready to be 'ored' into SCSI_CFG1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) /* SE automatic termination control is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) switch (scsi_cfg1 & C_DET_SE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) /* TERM_SE_HI: on, TERM_SE_LO: on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) asc_dvc->cfg->termination |= TERM_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) if (PCI_FUNC(pdev->devfn) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) asc_dvc->cfg->termination |= TERM_SE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) * Clear any set TERM_SE bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) scsi_cfg1 &= ~TERM_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) * Invert the TERM_SE bits and then set 'scsi_cfg1'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) * Clear Big Endian and Terminator Polarity bits and set possibly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) * modified termination control bits in the Microcode SCSI_CFG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) * Register Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) * Big Endian bit is not used even on big endian machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) * Set SCSI_CFG1 Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) * Set possibly modified termination control bits in the Microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) * SCSI_CFG1 Register Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) * The microcode will set the SCSI_CFG1 register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) * Set MEM_CFG Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) * The microcode will set the MEM_CFG register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) * MEM_CFG may be accessed as a word or byte, but only bits 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) * are defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) * ASC-38C1600 has 32KB internal memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) * out a special 16K Adv Library and Microcode version. After the issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) * resolved, we should turn back to the 32K support. Both a_condor.h and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) * mcode.sas files also need to be updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) * BIOS_EN | RAM_SZ_32KB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) BIOS_EN | RAM_SZ_16KB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) * Set SEL_MASK Microcode Default Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) * The microcode will set the SEL_MASK register using this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) * after it is started below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) AdvBuildCarrierFreelist(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) * Set-up the Host->RISC Initiator Command Queue (ICQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) if (!asc_dvc->icq_sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) * Set RISC ICQ physical address start value. Initialize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) * COMMA register to the same value otherwise the RISC will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) * prematurely detect a command is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) le32_to_cpu(asc_dvc->icq_sp->carr_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) * Set-up the RISC->Host Initiator Response Queue (IRQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) if (!asc_dvc->irq_sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) * Set RISC IRQ physical address start value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) asc_dvc->carr_pending_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) (ADV_INTR_ENABLE_HOST_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) ADV_INTR_ENABLE_GLOBAL_INTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) AdvWriteWordRegister(iop_base, IOPW_PC, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) /* finally, finally, gentlemen, start your engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) * Resets should be performed. The RISC has to be running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) * to issue a SCSI Bus Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) * If the BIOS Signature is present in memory, restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) * per TID microcode operating variables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) * Restore per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) for (tid = 0; tid <= ASC_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) AdvWriteByteLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) if (AdvResetSB(asc_dvc) != ADV_TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) warn_code = ASC_WARN_BUSRESET_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) * Reset chip and SCSI Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) ushort wdtr_able, sdtr_able, tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) ushort ppr_able = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) uchar tid, max_cmd[ADV_MAX_TID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) ushort bios_sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) * Save current per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) * Force the AdvInitAsc3550/38C0800Driver() function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) * perform a SCSI Bus Reset by clearing the BIOS signature word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) * The initialization functions assumes a SCSI Bus Reset is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) * needed if the BIOS signature word is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) * Stop chip and reset it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) ADV_CTRL_REG_CMD_WR_IO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) * Reset Adv Library error code, if any, and try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) * re-initializing the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) asc_dvc->err_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) status = AdvInitAsc38C1600Driver(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) status = AdvInitAsc38C0800Driver(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) status = AdvInitAsc3550Driver(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) /* Translate initialization return value to status value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) status = ADV_TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) status = ADV_FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) * Restore the BIOS signature word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) * Restore per TID negotiated values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) max_cmd[tid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) * adv_async_callback() - Adv Library asynchronous event callback function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) case ADV_ASYNC_SCSI_BUS_RESET_DET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) * The firmware detected a SCSI Bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) case ADV_ASYNC_RDMA_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) * Handle RDMA failure by resetting the SCSI Bus and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) * possibly the chip if it is unresponsive. Log the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) * with a unique code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) AdvResetChipAndSB(adv_dvc_varp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) case ADV_HOST_SCSI_BUS_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) * Host generated SCSI bus reset occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) ASC_DBG(0, "unknown code 0x%x\n", code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) * Callback function for the Wide SCSI Adv Library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) struct asc_board *boardp = adv_dvc_varp->drv_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) adv_req_t *reqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) adv_sgblk_t *sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) struct scsi_cmnd *scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) u32 resid_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) dma_addr_t sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) adv_dvc_varp, scsiqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) * Get the adv_req_t structure for the command that has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) * completed. The adv_req_t structure actually contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) * completed ADV_SCSI_REQ_Q structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) ASC_DBG(1, "scp 0x%p\n", scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) if (scp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) ASC_PRINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) reqp = (adv_req_t *)scp->host_scribble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) if (reqp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) ASC_PRINT("adv_isr_callback: reqp is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) * Remove backreferences to avoid duplicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) * command completions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) scp->host_scribble = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) reqp->cmndp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) ASC_STATS(boardp->shost, callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) ASC_DBG(1, "shost 0x%p\n", boardp->shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) sense_addr = le32_to_cpu(scsiqp->sense_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) dma_unmap_single(boardp->dev, sense_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) * 'done_status' contains the command's ending status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) switch (scsiqp->done_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) case QD_NO_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) ASC_DBG(2, "QD_NO_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) scp->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) * Check for an underrun condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) * If there was no error and an underrun condition, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) * then return the number of underrun bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) resid_cnt = le32_to_cpu(scsiqp->data_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) resid_cnt <= scsi_bufflen(scp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) ASC_DBG(1, "underrun condition %lu bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) (ulong)resid_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) scsi_set_resid(scp, resid_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) case QD_WITH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) ASC_DBG(2, "QD_WITH_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) switch (scsiqp->host_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) case QHSTA_NO_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) SCSI_SENSE_BUFFERSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) * Note: The 'status_byte()' macro used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) * target drivers defined in scsi.h shifts the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) * status byte returned by host drivers right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) * by 1 bit. This is why target drivers also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) * use right shifted status byte definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) * For instance target drivers use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) * CHECK_CONDITION, defined to 0x1, instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) * the SCSI defined check condition value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) * 0x2. Host drivers are supposed to return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) * the status byte as it is defined by SCSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) scp->result = DRIVER_BYTE(DRIVER_SENSE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) STATUS_BYTE(scsiqp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) scp->result = STATUS_BYTE(scsiqp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) /* Some other QHSTA error occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) scp->result = HOST_BYTE(DID_BAD_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) case QD_ABORTED_BY_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) scp->result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) scp->result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) * If the 'init_tidmask' bit isn't already set for the target and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) * current request finished normally, then set the bit for the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) * to indicate that a device is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) scsiqp->done_status == QD_NO_ERROR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) scsiqp->host_status == QHSTA_NO_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) asc_scsi_done(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) * Free all 'adv_sgblk_t' structures allocated for the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) while ((sgblkp = reqp->sgblkp) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) /* Remove 'sgblkp' from the request list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) reqp->sgblkp = sgblkp->next_sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) sgblkp->sg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) ASC_DBG(1, "done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) * Adv Library Interrupt Service Routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) * This function is called by a driver's interrupt service routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) * The function disables and re-enables interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) * When a microcode idle command is completed, the ADV_DVC_VAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) * 'idle_cmd_done' field is set to ADV_TRUE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) * Note: AdvISR() can be called when interrupts are disabled or even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) * when there is no hardware interrupt condition present. It will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) * always check for completed idle commands and microcode requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) * This is an important feature that shouldn't be changed because it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) * allows commands to be completed from polling mode loops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) * ADV_TRUE(1) - interrupt was pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) * ADV_FALSE(0) - no interrupt was pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) static int AdvISR(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) uchar int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) ushort target_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) ADV_CARR_T *free_carrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) __le32 irq_next_vpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) ADV_SCSI_REQ_Q *scsiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) adv_req_t *reqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) /* Reading the register clears the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) ADV_INTR_STATUS_INTRC)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) return ADV_FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) * Notify the driver of an asynchronous microcode condition by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) * calling the adv_async_callback function. The function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) * is passed the microcode ASC_MC_INTRB_CODE byte value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) if (int_stat & ADV_INTR_STATUS_INTRB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) uchar intrb_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) asc_dvc->carr_pending_cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) AdvWriteByteRegister(iop_base, IOPB_TICKLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) ADV_TICKLE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) AdvWriteByteRegister(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) IOPB_TICKLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) ADV_TICKLE_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) adv_async_callback(asc_dvc, intrb_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) * Check if the IRQ stopper carrier contains a completed request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) while (((irq_next_vpa =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) * The RISC will have set 'areq_vpa' to a virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) * in AdvExeScsiQueue().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) asc_dvc->irq_sp, pa_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) reqp = adv_get_reqp(asc_dvc, pa_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) scsiq = &reqp->scsi_req_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) * Request finished with good status and the queue was not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) * DMAed to host memory by the firmware. Set all status fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) * to indicate good status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) if ((irq_next_vpa & ADV_RQ_GOOD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) scsiq->done_status = QD_NO_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) scsiq->host_status = scsiq->scsi_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) scsiq->data_cnt = 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) * Advance the stopper pointer to the next carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) * ignoring the lower four bits. Free the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) * stopper carrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) free_carrp = asc_dvc->irq_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) ADV_GET_CARRP(irq_next_vpa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) asc_dvc->carr_freelist = free_carrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) asc_dvc->carr_pending_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) * Clear request microcode control flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) scsiq->cntl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) * Notify the driver of the completed request by passing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) * the ADV_SCSI_REQ_Q pointer to its callback function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) adv_isr_callback(asc_dvc, scsiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) * Note: After the driver callback function is called, 'scsiq'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) * can no longer be referenced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) * Fall through and continue processing other completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) * requests...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) return ADV_TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) if (asc_dvc->err_code == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) asc_dvc->err_code = err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) return err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) static void AscAckInterrupt(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) uchar host_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) uchar risc_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) ushort loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) if (loop++ > 0x7FFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) host_flag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) AscSetChipStatus(iop_base, CIW_INT_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) AscSetChipStatus(iop_base, CIW_INT_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) if (loop++ > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) const uchar *period_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) int max_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) int min_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) period_table = asc_dvc->sdtr_period_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) max_index = (int)asc_dvc->max_sdtr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) min_index = (int)asc_dvc->min_sdtr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) if ((syn_time <= period_table[max_index])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) for (i = min_index; i < (max_index - 1); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) if (syn_time <= period_table[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) return (uchar)i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) return (uchar)max_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) return (uchar)(max_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) static uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) PortAddr iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) uchar sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) EXT_MSG sdtr_buf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) .msg_type = EXTENDED_MESSAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) .msg_len = MS_SDTR_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) .msg_req = EXTENDED_SDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) .xfer_period = sdtr_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) .req_ack_offset = sdtr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) sdtr_offset &= ASC_SYN_MAX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) (uchar *)&sdtr_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) sizeof(EXT_MSG) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) return ((sdtr_period_index << 4) | sdtr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) sdtr_buf.req_ack_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) (uchar *)&sdtr_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) sizeof(EXT_MSG) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) static uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) uchar byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) uchar sdtr_period_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) if (sdtr_period_ix > asc_dvc->max_sdtr_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) return 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) return byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) ASC_SCSI_BIT_ID_TYPE org_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) bool sta = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) AscSetBank(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) org_id = AscReadChipDvcID(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) if (org_id == (0x01 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) org_id = (ASC_SCSI_BIT_ID_TYPE) i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) AscWriteChipDvcID(iop_base, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) AscSetBank(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) AscSetChipSyn(iop_base, sdtr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) if (AscGetChipSyn(iop_base) != sdtr_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) sta = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) sta = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) AscSetBank(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) AscWriteChipDvcID(iop_base, org_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) AscSetBank(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) return (sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) EXT_MSG ext_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) EXT_MSG out_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) ushort halt_q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) bool sdtr_accept;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) ushort int_halt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) ASC_SCSI_BIT_ID_TYPE scsi_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) ASC_SCSI_BIT_ID_TYPE target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) uchar tag_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) uchar q_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) uchar halt_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) uchar sdtr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) uchar target_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) uchar q_cntl, tid_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) uchar cur_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) uchar asyn_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) uchar scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) struct asc_board *boardp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) BUG_ON(!asc_dvc->drv_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) boardp = asc_dvc->drv_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) target_ix = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) (ushort)ASC_SCSIQ_B_TARGET_IX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) q_cntl = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) tid_no = ASC_TIX_TO_TID(target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) if (asc_dvc->pci_fix_asyn_xfer & target_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) asyn_sdtr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) if (asc_dvc->pci_fix_asyn_xfer & target_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) AscSetChipSDTR(iop_base, 0, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) boardp->sdtr_data[tid_no] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) if (asc_dvc->pci_fix_asyn_xfer & target_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) boardp->sdtr_data[tid_no] = asyn_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) AscMemWordCopyPtrFromLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) ASCV_MSGIN_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) (uchar *)&ext_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) sizeof(EXT_MSG) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) if (ext_msg.msg_type == EXTENDED_MESSAGE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) ext_msg.msg_req == EXTENDED_SDTR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) ext_msg.msg_len == MS_SDTR_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) sdtr_accept = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) sdtr_accept = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) if ((ext_msg.xfer_period <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) || (ext_msg.xfer_period >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) asc_dvc->sdtr_period_tbl[asc_dvc->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) max_sdtr_index])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) sdtr_accept = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) ext_msg.xfer_period =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) asc_dvc->sdtr_period_tbl[asc_dvc->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) min_sdtr_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) if (sdtr_accept) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) sdtr_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) ext_msg.req_ack_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) if (sdtr_data == 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) q_cntl |= QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) asc_dvc->init_sdtr &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) asc_dvc->sdtr_done &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) AscSetChipSDTR(iop_base, asyn_sdtr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) boardp->sdtr_data[tid_no] = asyn_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) if (ext_msg.req_ack_offset == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) q_cntl &= ~QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) asc_dvc->init_sdtr &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) asc_dvc->sdtr_done &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) q_cntl &= ~QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) asc_dvc->sdtr_done |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) asc_dvc->init_sdtr |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) asc_dvc->pci_fix_asyn_xfer &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) sdtr_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) AscCalSDTRData(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) ext_msg.xfer_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) ext_msg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) req_ack_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) AscSetChipSDTR(iop_base, sdtr_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) boardp->sdtr_data[tid_no] = sdtr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) q_cntl |= QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) AscMsgOutSDTR(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) ext_msg.xfer_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) ext_msg.req_ack_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) asc_dvc->pci_fix_asyn_xfer &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) sdtr_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) AscCalSDTRData(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) ext_msg.xfer_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) ext_msg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) req_ack_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) AscSetChipSDTR(iop_base, sdtr_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) boardp->sdtr_data[tid_no] = sdtr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) asc_dvc->sdtr_done |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) asc_dvc->init_sdtr |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) (ushort)ASC_SCSIQ_B_CNTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) q_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) ext_msg.msg_req == EXTENDED_WDTR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) ext_msg.msg_len == MS_WDTR_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) ext_msg.wdtr_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) AscMemWordCopyPtrToLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) ASCV_MSGOUT_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) (uchar *)&ext_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) sizeof(EXT_MSG) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) q_cntl |= QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) (ushort)ASC_SCSIQ_B_CNTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) q_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) ext_msg.msg_type = MESSAGE_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) AscMemWordCopyPtrToLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) ASCV_MSGOUT_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) (uchar *)&ext_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) sizeof(EXT_MSG) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) q_cntl |= QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) (ushort)ASC_SCSIQ_B_CNTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) q_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) q_cntl |= QC_REQ_SENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) if ((asc_dvc->init_sdtr & target_id) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) asc_dvc->sdtr_done &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) q_cntl |= QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) AscMsgOutSDTR(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) asc_dvc->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) sdtr_period_tbl[(sdtr_data >> 4) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) (uchar)(asc_dvc->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) max_sdtr_index -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) 1)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) (uchar)(sdtr_data & (uchar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) ASC_SYN_MAX_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) tag_code = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) (ushort)(halt_q_addr + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) ASC_SCSIQ_B_TAG_CODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) tag_code &= 0xDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) if ((asc_dvc->pci_fix_asyn_xfer & target_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) (ushort)ASC_SCSIQ_B_TAG_CODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) tag_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) q_status = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) (ushort)(halt_q_addr + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) ASC_SCSIQ_B_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) q_status |= (QS_READY | QS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) (ushort)ASC_SCSIQ_B_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) q_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) scsi_busy &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) AscMemWordCopyPtrFromLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) ASCV_MSGOUT_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) (uchar *)&out_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) sizeof(EXT_MSG) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) (out_msg.msg_len == MS_SDTR_LEN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) (out_msg.msg_req == EXTENDED_SDTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) asc_dvc->init_sdtr &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) asc_dvc->sdtr_done &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) boardp->sdtr_data[tid_no] = asyn_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) q_cntl &= ~QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) (ushort)(halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) scsi_status = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) (ushort)((ushort)halt_q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) ASC_SCSIQ_SCSI_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) cur_dvc_qng =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) (ushort)((ushort)ASC_QADR_BEG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) (ushort)target_ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) scsi_busy = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) (ushort)ASCV_SCSIBUSY_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) scsi_busy |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) (ushort)ASCV_SCSIBUSY_B, scsi_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) asc_dvc->queue_full_or_busy |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) if (scsi_status == SAM_STAT_TASK_SET_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) cur_dvc_qng -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) asc_dvc->max_dvc_qng[tid_no] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) cur_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) (ushort)((ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) ASCV_MAX_DVC_QNG_BEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) tid_no),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) cur_dvc_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) * Set the device queue depth to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) * number of active requests when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) * QUEUE FULL condition was encountered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) boardp->queue_full |= target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) boardp->queue_full_cnt[tid_no] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) cur_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) * void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) * Calling/Exit State:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) * none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) * Input an ASC_QDONE_INFO structure from the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) AscSetChipLramAddr(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) for (i = 0; i < 2 * words; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) if (i == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) word = inpw(iop_base + IOP_RAM_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) inbuf[i] = word & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) inbuf[i + 1] = (word >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) static uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) _AscCopyLramScsiDoneQ(PortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) ushort q_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) ushort _val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) uchar sg_queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) DvcGetQinfo(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) q_addr + ASC_SCSIQ_DONE_INFO_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) (uchar *)scsiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) _val = AscReadLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) scsiq->q_status = (uchar)_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) scsiq->q_no = (uchar)(_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) _val = AscReadLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) scsiq->cntl = (uchar)_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) sg_queue_cnt = (uchar)(_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) _val = AscReadLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) (ushort)(q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) (ushort)ASC_SCSIQ_B_SENSE_LEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) scsiq->sense_len = (uchar)_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) scsiq->extra_bytes = (uchar)(_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) * Read high word of remain bytes from alternate location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) (ushort)(q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) ASC_SCSIQ_W_ALT_DC1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) * Read low word of remain bytes from original location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) scsiq->remain_bytes += AscReadLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) (ushort)(q_addr + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) ASC_SCSIQ_DW_REMAIN_XFER_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) scsiq->remain_bytes &= max_dma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) return sg_queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) * Interrupt callback function for the Narrow SCSI Asc Library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) struct asc_board *boardp = asc_dvc_varp->drv_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) u32 srb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) struct scsi_cmnd *scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) * Decrease the srb_tag by 1 to find the SCSI command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) srb_tag = qdonep->d2.srb_tag - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) scp = scsi_host_find_tag(boardp->shost, srb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) if (!scp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) ASC_STATS(boardp->shost, callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) * 'qdonep' contains the command's ending status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) switch (qdonep->d3.done_stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) case QD_NO_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) ASC_DBG(2, "QD_NO_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) scp->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) * Check for an underrun condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) * If there was no error and an underrun condition, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) * return the number of underrun bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) qdonep->remain_bytes <= scsi_bufflen(scp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) ASC_DBG(1, "underrun condition %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) (unsigned)qdonep->remain_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) scsi_set_resid(scp, qdonep->remain_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) case QD_WITH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) ASC_DBG(2, "QD_WITH_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) switch (qdonep->d3.host_stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) case QHSTA_NO_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) SCSI_SENSE_BUFFERSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) * Note: The 'status_byte()' macro used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) * target drivers defined in scsi.h shifts the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) * status byte returned by host drivers right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) * by 1 bit. This is why target drivers also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) * use right shifted status byte definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) * For instance target drivers use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) * CHECK_CONDITION, defined to 0x1, instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) * the SCSI defined check condition value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) * 0x2. Host drivers are supposed to return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) * the status byte as it is defined by SCSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) scp->result = DRIVER_BYTE(DRIVER_SENSE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) STATUS_BYTE(qdonep->d3.scsi_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) /* QHSTA error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) scp->result = HOST_BYTE(DID_BAD_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) case QD_ABORTED_BY_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) scp->result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) scsi_msg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) STATUS_BYTE(qdonep->d3.scsi_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) scp->result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) scsi_msg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) STATUS_BYTE(qdonep->d3.scsi_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) * If the 'init_tidmask' bit isn't already set for the target and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) * current request finished normally, then set the bit for the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) * to indicate that a device is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) qdonep->d3.done_stat == QD_NO_ERROR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) qdonep->d3.host_stat == QHSTA_NO_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) asc_scsi_done(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) uchar next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) uchar n_q_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) uchar sg_list_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) uchar sg_queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) uchar q_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) uchar done_q_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) uchar tid_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) ASC_SCSI_BIT_ID_TYPE scsi_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) ASC_SCSI_BIT_ID_TYPE target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) ushort q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) ushort sg_q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) uchar cur_target_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) ASC_QDONE_INFO scsiq_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) ASC_QDONE_INFO *scsiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) bool false_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) n_q_used = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) q_addr = ASC_QNO_TO_QADDR(done_q_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) next_qp = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) if (next_qp != ASC_QLINK_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) AscPutVarDoneQTail(iop_base, next_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) q_addr = ASC_QNO_TO_QADDR(next_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) asc_dvc->max_dma_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) (ushort)(q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) (ushort)ASC_SCSIQ_B_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) (uchar)(scsiq->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) q_status & (uchar)~(QS_READY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) QS_ABORTED)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) if ((scsiq->cntl & QC_SG_HEAD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) sg_q_addr = q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) sg_list_qp = next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) sg_list_qp = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) (ushort)(sg_q_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) ASC_SCSIQ_B_FWD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) if (sg_list_qp == ASC_QLINK_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) AscSetLibErrorCode(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) ASCQ_ERR_SG_Q_LINKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) scsiq->d3.done_stat = QD_WITH_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) scsiq->d3.host_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) QHSTA_D_QDONE_SG_LIST_CORRUPTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) goto FATAL_ERR_QDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) (ushort)(sg_q_addr + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) ASC_SCSIQ_B_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) QS_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) n_q_used = sg_queue_cnt + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) AscPutVarDoneQTail(iop_base, sg_list_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) if (asc_dvc->queue_full_or_busy & target_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) cur_target_qng = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) (ushort)((ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) ASC_QADR_BEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) scsiq->d2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) target_ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) scsi_busy = AscReadLramByte(iop_base, (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) ASCV_SCSIBUSY_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) scsi_busy &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) AscWriteLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) (ushort)ASCV_SCSIBUSY_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) scsi_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) asc_dvc->queue_full_or_busy &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) if (asc_dvc->cur_total_qng >= n_q_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) asc_dvc->cur_total_qng -= n_q_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) asc_dvc->cur_dvc_qng[tid_no]--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) scsiq->d3.done_stat = QD_WITH_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) goto FATAL_ERR_QDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) if ((scsiq->d2.srb_tag == 0UL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) ((scsiq->q_status & QS_ABORTED) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) return (0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) } else if (scsiq->q_status == QS_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) * This is also curious.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) * false_overrun will _always_ be set to 'false'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) false_overrun = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) if (scsiq->extra_bytes != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) scsiq->remain_bytes += scsiq->extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) if (scsiq->d3.done_stat == QD_WITH_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) if (scsiq->d3.host_stat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) QHSTA_M_DATA_OVER_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956) if ((scsiq->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) cntl & (QC_DATA_IN | QC_DATA_OUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) scsiq->d3.done_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) QD_NO_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) scsiq->d3.host_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) QHSTA_NO_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) } else if (false_overrun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) scsiq->d3.done_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) QD_NO_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) scsiq->d3.host_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) QHSTA_NO_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) } else if (scsiq->d3.host_stat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) AscStopChip(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) AscSetChipControl(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) (uchar)(CC_SCSI_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) | CC_HALT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) udelay(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) AscSetChipControl(iop_base, CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) AscSetChipStatus(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) CIW_CLR_SCSI_RESET_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) AscSetChipStatus(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) AscSetChipControl(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) asc_isr_callback(asc_dvc, scsiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) if ((AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) (ushort)(q_addr + (ushort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) ASC_SCSIQ_CDB_BEG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) == START_STOP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) asc_dvc->unit_not_ready &= ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) if (scsiq->d3.done_stat != QD_NO_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) asc_dvc->start_motor &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) ~target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) FATAL_ERR_QDONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001) if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) asc_isr_callback(asc_dvc, scsiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) return (0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) static int AscISR(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) ASC_CS_TYPE chipstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) ushort saved_ram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) uchar ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) uchar saved_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) int int_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) uchar host_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) int_pending = ASC_FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) if (AscIsIntPending(iop_base) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) return int_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) if (asc_dvc->in_critical_cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) if (asc_dvc->is_in_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) asc_dvc->is_in_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) ctrl_reg = AscGetChipControl(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) CC_SINGLE_STEP | CC_DIAG | CC_TEST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) chipstat = AscGetChipStatus(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) if (chipstat & CSW_SCSI_RESET_LATCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) int i = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) int_pending = ASC_TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) asc_dvc->sdtr_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) saved_ctrl_reg &= (uchar)(~CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) while ((AscGetChipStatus(iop_base) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) AscSetChipControl(iop_base, CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) AscSetChipStatus(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) chipstat = AscGetChipStatus(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) saved_ram_addr = AscGetChipLramAddr(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) host_flag = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) ASCV_HOST_FLAG_B) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) (uchar)(~ASC_HOST_FLAG_IN_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) AscAckInterrupt(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) int_pending = ASC_TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) AscIsrChipHalted(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) saved_ctrl_reg &= (uchar)(~CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) while (((status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) AscIsrQDone(asc_dvc)) & 0x01) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) if ((status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) AscIsrQDone(asc_dvc)) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) } while (status == 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) if ((status & 0x80) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) int_pending = ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) AscSetChipLramAddr(iop_base, saved_ram_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) AscSetChipControl(iop_base, saved_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) asc_dvc->is_in_int = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) return int_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) * advansys_reset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) * Reset the host associated with the command 'scp'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) * This function runs its own thread. Interrupts must be blocked but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) * sleeping is allowed and no locking other than for host structures is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) * required. Returns SUCCESS or FAILED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) static int advansys_reset(struct scsi_cmnd *scp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) struct Scsi_Host *shost = scp->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) int ret = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) ASC_DBG(1, "0x%p\n", scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) ASC_STATS(shost, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) /* Reset the chip and SCSI bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) ASC_DBG(1, "before AscInitAsc1000Driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) status = AscInitAsc1000Driver(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) "0x%x, status: 0x%x\n", asc_dvc->err_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) ret = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) } else if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) "0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) scmd_printk(KERN_INFO, scp, "SCSI host reset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) "successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) ASC_DBG(1, "after AscInitAsc1000Driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) * If the suggest reset bus flags are set, then reset the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) * Otherwise only reset the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) * Reset the chip and SCSI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) ASC_DBG(1, "before AdvResetChipAndSB()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) switch (AdvResetChipAndSB(adv_dvc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) case ASC_TRUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) scmd_printk(KERN_INFO, scp, "SCSI host reset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) "successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) case ASC_FALSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) ret = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) spin_lock_irqsave(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) AdvISR(adv_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) spin_unlock_irqrestore(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) ASC_DBG(1, "ret %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) * advansys_biosparam()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) * Translate disk drive geometry if the "BIOS greater than 1 GB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) * support is enabled for a drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) * ip (information pointer) is an int array with the following definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) * ip[0]: heads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) * ip[1]: sectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) * ip[2]: cylinders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) sector_t capacity, int ip[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) struct asc_board *boardp = shost_priv(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) ASC_DBG(1, "begin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) ASC_STATS(sdev->host, biosparam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) ip[0] = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) ip[1] = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) ip[0] = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) ip[1] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) ip[0] = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) ip[1] = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) ip[0] = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) ip[1] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) ASC_DBG(1, "end\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) * First-level interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) static irqreturn_t advansys_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) struct Scsi_Host *shost = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) irqreturn_t result = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) ASC_DBG(2, "boardp 0x%p\n", boardp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) spin_lock_irqsave(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) if (AscIsIntPending(shost->io_port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) result = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) ASC_STATS(shost, interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) ASC_DBG(1, "before AscISR()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) AscISR(&boardp->dvc_var.asc_dvc_var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) ASC_DBG(1, "before AdvISR()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) result = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) ASC_STATS(shost, interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) spin_unlock_irqrestore(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) ASC_DBG(1, "end\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) static bool AscHostReqRiscHalt(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) bool sta = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) uchar saved_stop_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) if (AscIsChipHalted(iop_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) if (AscIsChipHalted(iop_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) sta = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) } while (count++ < 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) return sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) bool sta = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) if (AscHostReqRiscHalt(iop_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) AscStartChip(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) return sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) char type = sdev->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) if (asc_dvc->init_sdtr & tid_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) asc_dvc->pci_fix_asyn_xfer |= tid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) (type == TYPE_ROM) || (type == TYPE_TAPE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) ASYN_SDTR_DATA_FIX_PCI_REV_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) if (sdev->lun == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) asc_dvc->init_sdtr |= tid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) asc_dvc->init_sdtr &= ~tid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) if (orig_init_sdtr != asc_dvc->init_sdtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) AscAsyncFix(asc_dvc, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) if (sdev->tagged_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) if (sdev->lun == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) asc_dvc->cfg->can_tagged_qng |= tid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) asc_dvc->use_tagged_qng |= tid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) scsi_change_queue_depth(sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) asc_dvc->max_dvc_qng[sdev->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) if (sdev->lun == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) asc_dvc->use_tagged_qng &= ~tid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) if ((sdev->lun == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) asc_dvc->cfg->disc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) asc_dvc->use_tagged_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) asc_dvc->cfg->can_tagged_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) asc_dvc->max_dvc_qng[sdev->id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) asc_dvc->cfg->max_tag_qng[sdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) AscWriteLramByte(asc_dvc->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) asc_dvc->max_dvc_qng[sdev->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359) * Wide Transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) * If the EEPROM enabled WDTR for the device and the device supports wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) * write the new value to the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) unsigned short cfg_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) if ((cfg_word & tidmask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) cfg_word |= tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374) AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) * Clear the microcode SDTR and WDTR negotiation done indicators for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) * the target to cause it to negotiate with the new setting set above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) * WDTR when accepted causes the target to enter asynchronous mode, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) * SDTR must be negotiated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) cfg_word &= ~tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) cfg_word &= ~tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) * Synchronous Transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) * If the EEPROM enabled SDTR for the device and the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) * supports synchronous transfers, then turn on the device's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) * 'sdtr_able' bit. Write the new value to the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) unsigned short cfg_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) if ((cfg_word & tidmask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) cfg_word |= tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) * Clear the microcode "SDTR negotiation" done indicator for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) * target to cause it to negotiate with the new setting set above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) cfg_word &= ~tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) * PPR (Parallel Protocol Request) Capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) * If the device supports DT mode, then it must be PPR capable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) * The PPR message will be used in place of the SDTR and WDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422) * messages to negotiate synchronous speed and offset, transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) * width, and protocol options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) AdvPortAddr iop_base, unsigned short tidmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) adv_dvc->ppr_able |= tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) AdvPortAddr iop_base = adv_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) unsigned short tidmask = 1 << sdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) if (sdev->lun == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) * Handle WDTR, SDTR, and Tag Queuing. If the feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) * is enabled in the EEPROM and the device supports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) * feature, then enable it in the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) advansys_wide_enable_wdtr(iop_base, tidmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) advansys_wide_enable_sdtr(iop_base, tidmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) * Tag Queuing is disabled for the BIOS which runs in polled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) * mode and would see no benefit from Tag Queuing. Also by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) * disabling Tag Queuing in the BIOS devices with Tag Queuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) * bugs will at least work with the BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) if ((adv_dvc->tagqng_able & tidmask) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) sdev->tagged_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) unsigned short cfg_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) cfg_word |= tidmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465) cfg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) AdvWriteByteLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) adv_dvc->max_dvc_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) * Set the number of commands to queue per device for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) * specified host adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) static int advansys_slave_configure(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) struct asc_board *boardp = shost_priv(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) if (ASC_NARROW_BOARD(boardp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) advansys_narrow_slave_configure(sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) &boardp->dvc_var.asc_dvc_var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) advansys_wide_slave_configure(sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) &boardp->dvc_var.adv_dvc_var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494) static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) struct asc_board *board = shost_priv(scp->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) SCSI_SENSE_BUFFERSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) if (dma_mapping_error(board->dev, scp->SCp.dma_handle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) ASC_DBG(1, "failed to map sense buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) return cpu_to_le32(scp->SCp.dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) struct asc_scsi_q *asc_scsi_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) int use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) u32 srb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) * Set the srb_tag to the command tag + 1, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) * srb_tag '0' is used internally by the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) srb_tag = scp->request->tag + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) asc_scsi_q->q2.srb_tag = srb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) * Build the ASC_SCSI_Q request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) asc_scsi_q->cdbptr = &scp->cmnd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) asc_scsi_q->q2.cdb_len = scp->cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) asc_scsi_q->q1.target_lun = scp->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) asc_scsi_q->q2.target_ix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) asc_scsi_q->q1.sense_addr = asc_get_sense_buffer_dma(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) if (!asc_scsi_q->q1.sense_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) * If there are any outstanding requests for the current target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) * then every 255th request send an ORDERED request. This heuristic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541) * tries to retain the benefit of request sorting while preventing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) * request starvation. 255 is the max number of tags or pending commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) * a device may have outstanding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) * The request count is incremented below for every successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) * started request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549) if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) (boardp->reqcnt[scp->device->id] % 255) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) /* Build ASC_SCSI_Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) use_sg = scsi_dma_map(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) if (use_sg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) ASC_DBG(1, "failed to map sglist\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) } else if (use_sg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) int sgcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) struct scatterlist *slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) struct asc_sg_head *asc_sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) if (use_sg > scp->device->host->sg_tablesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) scmd_printk(KERN_ERR, scp, "use_sg %d > "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568) "sg_tablesize %d\n", use_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) scp->device->host->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) scsi_dma_unmap(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) scp->result = HOST_BYTE(DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) if (!asc_sg_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) scsi_dma_unmap(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) scp->result = HOST_BYTE(DID_SOFT_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) asc_scsi_q->q1.cntl |= QC_SG_HEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584) asc_scsi_q->sg_head = asc_sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) asc_scsi_q->q1.data_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) asc_scsi_q->q1.data_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) /* This is a byte value, otherwise it would need to be swapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) ASC_STATS_ADD(scp->device->host, xfer_elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) asc_sg_head->entry_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) * Convert scatter-gather list into ASC_SG_HEAD list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) asc_sg_head->sg_list[sgcnt].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) cpu_to_le32(sg_dma_address(slp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598) asc_sg_head->sg_list[sgcnt].bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) cpu_to_le32(sg_dma_len(slp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) ASC_STATS_ADD(scp->device->host, xfer_sect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) DIV_ROUND_UP(sg_dma_len(slp), 512));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605) ASC_STATS(scp->device->host, xfer_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) return ASC_NOERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) * Build scatter-gather list for Adv Library (Wide Board).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) * Additional ADV_SG_BLOCK structures will need to be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) * if the total number of scatter-gather elements exceeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) * assumed to be physically contiguous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) * ADV_SUCCESS(1) - SG List successfully created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) * ADV_ERROR(-1) - SG List creation failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627) ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) adv_sgblk_t *sgblkp, *prev_sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) struct scatterlist *slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) int sg_elem_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) ADV_SG_BLOCK *sg_block, *prev_sg_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) dma_addr_t sgblk_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) slp = scsi_sglist(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) sg_elem_cnt = use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638) prev_sgblkp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) prev_sg_block = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) reqp->sgblkp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) * Allocate a 'adv_sgblk_t' structure from the board free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645) * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) * (15) scatter-gather elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) &sgblk_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650) if (!sgblkp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) ASC_DBG(1, "no free adv_sgblk_t\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) ASC_STATS(scp->device->host, adv_build_nosg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) * Allocation failed. Free 'adv_sgblk_t' structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) * already allocated for the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) while ((sgblkp = reqp->sgblkp) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) /* Remove 'sgblkp' from the request list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) reqp->sgblkp = sgblkp->next_sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661) sgblkp->next_sgblkp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) sgblkp->sg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) /* Complete 'adv_sgblk_t' board allocation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) sgblkp->sg_addr = sgblk_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) sgblkp->next_sgblkp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670) sg_block = &sgblkp->sg_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) * Check if this is the first 'adv_sgblk_t' for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) if (reqp->sgblkp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) /* Request's first scatter-gather block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) reqp->sgblkp = sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) * address pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) scsiqp->sg_list_ptr = sg_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) /* Request's second or later scatter-gather block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) prev_sgblkp->next_sgblkp = sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) * Point the previous ADV_SG_BLOCK structure to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) * the newly allocated ADV_SG_BLOCK structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) sg_block->sg_list[i].sg_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) cpu_to_le32(sg_dma_address(slp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) sg_block->sg_list[i].sg_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) cpu_to_le32(sg_dma_len(slp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) ASC_STATS_ADD(scp->device->host, xfer_sect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) DIV_ROUND_UP(sg_dma_len(slp), 512));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) if (--sg_elem_cnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) * Last ADV_SG_BLOCK and scatter-gather entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) sg_block->sg_cnt = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) return ADV_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) slp = sg_next(slp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) prev_sg_block = sg_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) prev_sgblkp = sgblkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) * Build a request structure for the Adv Library (Wide Board).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) * If an adv_req_t can not be allocated to issue the request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) * microcode for DMA addresses or math operations are byte swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) * to little-endian order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) adv_req_t **adv_reqpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) u32 srb_tag = scp->request->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) adv_req_t *reqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) ADV_SCSI_REQ_Q *scsiqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) int use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) dma_addr_t sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) * Allocate an adv_req_t structure from the board to execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) * the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) reqp = &boardp->adv_reqp[srb_tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) if (reqp->cmndp && reqp->cmndp != scp ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) ASC_DBG(1, "no free adv_req_t\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) ASC_STATS(scp->device->host, adv_build_noreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) scsiqp = &reqp->scsi_req_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) * Initialize the structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) * Set the srb_tag to the command tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765) scsiqp->srb_tag = srb_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) * Set 'host_scribble' to point to the adv_req_t structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) reqp->cmndp = scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) scp->host_scribble = (void *)reqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) * Build the ADV_SCSI_REQ_Q request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) /* Set CDB length and copy it to the request structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) scsiqp->cdb_len = scp->cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) /* Copy first 12 CDB bytes to cdb[]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) /* Copy last 4 CDB bytes, if present, to cdb16[]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) if (scp->cmd_len > 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) int cdb16_len = scp->cmd_len - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) scsiqp->target_id = scp->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) scsiqp->target_lun = scp->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793) if (dma_mapping_error(boardp->dev, sense_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) ASC_DBG(1, "failed to map sense buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) ASC_STATS(scp->device->host, adv_build_noreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) scsiqp->sense_addr = cpu_to_le32(sense_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) /* Build ADV_SCSI_REQ_Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) use_sg = scsi_dma_map(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) if (use_sg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) ASC_DBG(1, "failed to map SG list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) ASC_STATS(scp->device->host, adv_build_noreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) } else if (use_sg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809) /* Zero-length transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) reqp->sgblkp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) scsiqp->data_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) scsiqp->data_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814) scsiqp->sg_list_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) scsiqp->sg_real_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) if (use_sg > ADV_MAX_SG_LIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818) scmd_printk(KERN_ERR, scp, "use_sg %d > "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) "ADV_MAX_SG_LIST %d\n", use_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) scp->device->host->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821) scsi_dma_unmap(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) scp->result = HOST_BYTE(DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) reqp->cmndp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) scp->host_scribble = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832) if (ret != ADV_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833) scsi_dma_unmap(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) scp->result = HOST_BYTE(DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) reqp->cmndp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836) scp->host_scribble = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841) ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844) ASC_STATS(scp->device->host, xfer_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847) ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) *adv_reqpp = reqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) return ASC_NOERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854) static int AscSgListToQueue(int sg_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) int n_sg_list_qs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859) if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) n_sg_list_qs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) return n_sg_list_qs + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) static uint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) uint cur_used_qs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) uint cur_free_qs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) ASC_SCSI_BIT_ID_TYPE target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) uchar tid_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872) target_id = ASC_TIX_TO_TARGET_ID(target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) tid_no = ASC_TIX_TO_TID(target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) if ((asc_dvc->unit_not_ready & target_id) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875) (asc_dvc->queue_full_or_busy & target_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878) if (n_qs == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) cur_used_qs = (uint) asc_dvc->cur_total_qng +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) cur_used_qs = (uint) asc_dvc->cur_total_qng +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) (uint) ASC_MIN_FREE_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) if (asc_dvc->cur_dvc_qng[tid_no] >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888) asc_dvc->max_dvc_qng[tid_no]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891) return cur_free_qs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) if (n_qs > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) if ((n_qs > asc_dvc->last_q_shortage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) asc_dvc->last_q_shortage = n_qs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) ushort q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905) uchar next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) uchar q_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908) q_addr = ASC_QNO_TO_QADDR(free_q_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909) q_status = (uchar)AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) (ushort)(q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911) ASC_SCSIQ_B_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913) if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) return next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) return ASC_QLINK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918) static uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919) AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) uchar i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923) for (i = 0; i < n_free_q; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) if (free_q_head == ASC_QLINK_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928) return free_q_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932) * void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) * Calling/Exit State:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) * none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) * Output an ASC_SCSI_Q structure to the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942) DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946) ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) AscSetChipLramAddr(iop_base, s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948) for (i = 0; i < 2 * words; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) if (i == 4 || i == 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952) outpw(iop_base + IOP_RAM_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957) static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) ushort q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) uchar tid_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961) uchar sdtr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) uchar syn_period_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963) uchar syn_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969) tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) syn_period_ix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972) (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973) syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974) AscMsgOutSDTR(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) asc_dvc->sdtr_period_tbl[syn_period_ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976) syn_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977) scsiq->q1.cntl |= QC_MSG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979) q_addr = ASC_QNO_TO_QADDR(q_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980) if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981) scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7983) scsiq->q1.status = QS_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7984) AscMemWordCopyPtrToLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7985) q_addr + ASC_SCSIQ_CDB_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7986) (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7988) DvcPutScsiQ(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7989) q_addr + ASC_SCSIQ_CPY_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7990) (uchar *)&scsiq->q1.cntl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7991) ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7992) AscWriteLramWord(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7993) (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7994) (ushort)(((ushort)scsiq->q1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7995) q_no << 8) | (ushort)QS_READY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7996) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7999) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8000) AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8002) int sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8003) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8004) ASC_SG_HEAD *sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8005) ASC_SG_LIST_Q scsi_sg_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8006) __le32 saved_data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8007) __le32 saved_data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8008) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8009) ushort sg_list_dwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8010) ushort sg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8011) ushort sg_entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8012) ushort q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8013) uchar next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8015) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8016) sg_head = scsiq->sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8017) saved_data_addr = scsiq->q1.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8018) saved_data_cnt = scsiq->q1.data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8019) scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8020) scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8022) * Set sg_entry_cnt to be the number of SG elements that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8023) * will fit in the allocated SG queues. It is minus 1, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8024) * the first SG element is handled above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8026) sg_entry_cnt = sg_head->entry_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8028) if (sg_entry_cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8029) scsiq->q1.cntl |= QC_SG_HEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8030) q_addr = ASC_QNO_TO_QADDR(q_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8031) sg_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8032) scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8033) scsi_sg_q.sg_head_qp = q_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8034) scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8035) for (i = 0; i < sg_head->queue_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8036) scsi_sg_q.seq_no = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8037) if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8038) sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8039) sg_entry_cnt -= ASC_SG_LIST_PER_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8040) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8041) scsi_sg_q.sg_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8042) ASC_SG_LIST_PER_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8043) scsi_sg_q.sg_cur_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8044) ASC_SG_LIST_PER_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8045) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8046) scsi_sg_q.sg_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8047) ASC_SG_LIST_PER_Q - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8048) scsi_sg_q.sg_cur_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8049) ASC_SG_LIST_PER_Q - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8051) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8052) scsi_sg_q.cntl |= QCSG_SG_XFER_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8053) sg_list_dwords = sg_entry_cnt << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8054) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8055) scsi_sg_q.sg_list_cnt = sg_entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8056) scsi_sg_q.sg_cur_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8057) sg_entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8059) scsi_sg_q.sg_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8060) sg_entry_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8061) scsi_sg_q.sg_cur_list_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8062) sg_entry_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8064) sg_entry_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8066) next_qp = AscReadLramByte(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8067) (ushort)(q_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8068) ASC_SCSIQ_B_FWD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8069) scsi_sg_q.q_no = next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8070) q_addr = ASC_QNO_TO_QADDR(next_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8071) AscMemWordCopyPtrToLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8072) q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8073) (uchar *)&scsi_sg_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8074) sizeof(ASC_SG_LIST_Q) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8075) AscMemDWordCopyPtrToLram(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8076) q_addr + ASC_SGQ_LIST_BEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8077) (uchar *)&sg_head->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8078) sg_list[sg_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8079) sg_list_dwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8080) sg_index += ASC_SG_LIST_PER_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8081) scsiq->next_sg_index = sg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8084) scsiq->q1.cntl &= ~QC_SG_HEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8086) sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8087) scsiq->q1.data_addr = saved_data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8088) scsiq->q1.data_cnt = saved_data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8089) return (sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8092) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8093) AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8095) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8096) uchar free_q_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8097) uchar next_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8098) uchar tid_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8099) uchar target_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8100) int sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8102) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8103) target_ix = scsiq->q2.target_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8104) tid_no = ASC_TIX_TO_TID(target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8105) sta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8106) free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8107) if (n_q_required > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8108) next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8109) (uchar)n_q_required);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8110) if (next_qp != ASC_QLINK_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8111) asc_dvc->last_q_shortage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8112) scsiq->sg_head->queue_cnt = n_q_required - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8113) scsiq->q1.q_no = free_q_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8114) sta = AscPutReadySgListQueue(asc_dvc, scsiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8115) free_q_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8117) } else if (n_q_required == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8118) next_qp = AscAllocFreeQueue(iop_base, free_q_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8119) if (next_qp != ASC_QLINK_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8120) scsiq->q1.q_no = free_q_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8121) sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8124) if (sta == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8125) AscPutVarFreeQHead(iop_base, next_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8126) asc_dvc->cur_total_qng += n_q_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8127) asc_dvc->cur_dvc_qng[tid_no]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8129) return sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8132) #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8133) static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8134) INQUIRY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8135) REQUEST_SENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8136) READ_CAPACITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8137) READ_TOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8138) MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8139) MODE_SENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8140) MODE_SELECT_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8141) MODE_SENSE_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8142) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8143) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8144) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8145) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8146) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8147) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8148) 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8149) 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8152) static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8154) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8155) int sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8156) int n_q_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8157) bool disable_syn_offset_one_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8158) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8159) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8160) ushort sg_entry_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8161) ushort sg_entry_cnt_minus_one = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8162) uchar target_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8163) uchar tid_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8164) uchar sdtr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8165) uchar extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8166) uchar scsi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8167) uchar disable_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8168) ASC_SG_HEAD *sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8169) unsigned long data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8171) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8172) sg_head = scsiq->sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8173) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8174) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8175) scsiq->q1.q_no = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8176) if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8177) scsiq->q1.extra_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8179) sta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8180) target_ix = scsiq->q2.target_ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8181) tid_no = ASC_TIX_TO_TID(target_ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8182) n_q_required = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8183) if (scsiq->cdbptr[0] == REQUEST_SENSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8184) if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8185) asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8186) sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8187) AscMsgOutSDTR(asc_dvc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8188) asc_dvc->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8189) sdtr_period_tbl[(sdtr_data >> 4) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8190) (uchar)(asc_dvc->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8191) max_sdtr_index -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8192) 1)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8193) (uchar)(sdtr_data & (uchar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8194) ASC_SYN_MAX_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8195) scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8198) if (asc_dvc->in_critical_cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8199) AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8200) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8202) asc_dvc->in_critical_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8203) if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8204) if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8205) asc_dvc->in_critical_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8206) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8208) if (sg_entry_cnt > ASC_MAX_SG_LIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8209) asc_dvc->in_critical_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8210) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8212) if (sg_entry_cnt == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8213) scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8214) scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8215) scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8217) sg_entry_cnt_minus_one = sg_entry_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8219) scsi_cmd = scsiq->cdbptr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8220) disable_syn_offset_one_fix = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8221) if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8222) !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8223) if (scsiq->q1.cntl & QC_SG_HEAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8224) data_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8225) for (i = 0; i < sg_entry_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8226) data_cnt += le32_to_cpu(sg_head->sg_list[i].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8227) bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8230) data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8232) if (data_cnt != 0UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8233) if (data_cnt < 512UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8234) disable_syn_offset_one_fix = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8236) for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8237) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8238) disable_cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8239) _syn_offset_one_disable_cmd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8240) if (disable_cmd == 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8243) if (scsi_cmd == disable_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8244) disable_syn_offset_one_fix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8245) true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8252) if (disable_syn_offset_one_fix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8253) scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8254) scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8255) ASC_TAG_FLAG_DISABLE_DISCONNECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8257) scsiq->q2.tag_code &= 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8259) if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8260) if (asc_dvc->bug_fix_cntl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8261) if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8262) if ((scsi_cmd == READ_6) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8263) (scsi_cmd == READ_10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8264) addr = le32_to_cpu(sg_head->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8265) sg_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8266) [sg_entry_cnt_minus_one].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8267) addr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8268) le32_to_cpu(sg_head->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8269) sg_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8270) [sg_entry_cnt_minus_one].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8271) bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8272) extra_bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8273) (uchar)((ushort)addr & 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8274) if ((extra_bytes != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8275) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8276) ((scsiq->q2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8277) tag_code &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8278) ASC_TAG_FLAG_EXTRA_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8279) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8280) scsiq->q2.tag_code |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8281) ASC_TAG_FLAG_EXTRA_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8282) scsiq->q1.extra_bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8283) extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8284) data_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8285) le32_to_cpu(sg_head->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8286) sg_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8287) [sg_entry_cnt_minus_one].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8288) bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8289) data_cnt -= extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8290) sg_head->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8291) sg_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8292) [sg_entry_cnt_minus_one].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8293) bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8294) cpu_to_le32(data_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8299) sg_head->entry_to_copy = sg_head->entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8300) n_q_required = AscSgListToQueue(sg_entry_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8301) if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8302) (uint) n_q_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8303) || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8304) if ((sta =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8305) AscSendScsiQueue(asc_dvc, scsiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8306) n_q_required)) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8307) asc_dvc->in_critical_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8308) return (sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8312) if (asc_dvc->bug_fix_cntl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8313) if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8314) if ((scsi_cmd == READ_6) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8315) (scsi_cmd == READ_10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8316) addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8317) le32_to_cpu(scsiq->q1.data_addr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8318) le32_to_cpu(scsiq->q1.data_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8319) extra_bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8320) (uchar)((ushort)addr & 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8321) if ((extra_bytes != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8322) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8323) ((scsiq->q2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8324) tag_code &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8325) ASC_TAG_FLAG_EXTRA_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8326) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8327) data_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8328) le32_to_cpu(scsiq->q1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8329) data_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8330) if (((ushort)data_cnt & 0x01FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8331) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8332) scsiq->q2.tag_code |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8333) ASC_TAG_FLAG_EXTRA_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8334) data_cnt -= extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8335) scsiq->q1.data_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8336) cpu_to_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8337) (data_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8338) scsiq->q1.extra_bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8339) extra_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8345) n_q_required = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8346) if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8347) ((scsiq->q1.cntl & QC_URGENT) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8348) if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8349) n_q_required)) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8350) asc_dvc->in_critical_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8351) return (sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8355) asc_dvc->in_critical_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8356) return (sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8360) * AdvExeScsiQueue() - Send a request to the RISC microcode program.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8362) * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8363) * add the carrier to the ICQ (Initiator Command Queue), and tickle the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8364) * RISC to notify it a new command is ready to be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8366) * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8367) * set to SCSI_MAX_RETRY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8369) * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8370) * for DMA addresses or math operations are byte swapped to little-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8371) * order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8373) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8374) * ADV_SUCCESS(1) - The request was successfully queued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8375) * ADV_BUSY(0) - Resource unavailable; Retry again after pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8376) * request completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8377) * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8378) * host IC error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8380) static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8382) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8383) ADV_CARR_T *new_carrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8384) ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8387) * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8389) if (scsiq->target_id > ADV_MAX_TID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8390) scsiq->host_status = QHSTA_M_INVALID_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8391) scsiq->done_status = QD_WITH_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8392) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8395) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8398) * Allocate a carrier ensuring at least one carrier always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8399) * remains on the freelist and initialize fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8401) new_carrp = adv_get_next_carrier(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8402) if (!new_carrp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8403) ASC_DBG(1, "No free carriers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8404) return ADV_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8407) asc_dvc->carr_pending_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8409) /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8410) scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8411) scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8413) scsiq->carr_va = asc_dvc->icq_sp->carr_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8414) scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8417) * Use the current stopper to send the ADV_SCSI_REQ_Q command to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8418) * the microcode. The newly allocated stopper will become the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8419) * stopper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8421) asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8424) * Set the 'next_vpa' pointer for the old stopper to be the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8425) * physical address of the new stopper. The RISC can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8426) * follow physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8428) asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8431) * Set the host adapter stopper pointer to point to the new carrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8433) asc_dvc->icq_sp = new_carrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8435) if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8436) asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8438) * Tickle the RISC to tell it to read its Command Queue Head pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8440) AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8441) if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8443) * Clear the tickle value. In the ASC-3550 the RISC flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8444) * command 'clr_tickle_a' does not work unless the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8445) * value is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8447) AdvWriteByteRegister(iop_base, IOPB_TICKLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8448) ADV_TICKLE_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8450) } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8452) * Notify the RISC a carrier is ready by writing the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8453) * address of the new carrier stopper to the COMMA register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8455) AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8456) le32_to_cpu(new_carrp->carr_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8459) return ADV_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8463) * Execute a single 'struct scsi_cmnd'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8465) static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8467) int ret, err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8468) struct asc_board *boardp = shost_priv(scp->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8470) ASC_DBG(1, "scp 0x%p\n", scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8472) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8473) ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8474) struct asc_scsi_q asc_scsi_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8476) ret = asc_build_req(boardp, scp, &asc_scsi_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8477) if (ret != ASC_NOERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8478) ASC_STATS(scp->device->host, build_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8482) ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8483) kfree(asc_scsi_q.sg_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8484) err_code = asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8485) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8486) ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8487) adv_req_t *adv_reqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8489) switch (adv_build_req(boardp, scp, &adv_reqp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8490) case ASC_NOERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8491) ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8493) case ASC_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8494) ASC_DBG(1, "adv_build_req ASC_BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8496) * The asc_stats fields 'adv_build_noreq' and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8497) * 'adv_build_nosg' count wide board busy conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8498) * They are updated in adv_build_req and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8499) * adv_get_sglist, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8501) return ASC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8502) case ASC_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8504) ASC_DBG(1, "adv_build_req ASC_ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8505) ASC_STATS(scp->device->host, build_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8506) return ASC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8509) ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8510) err_code = adv_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8513) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8514) case ASC_NOERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8515) ASC_STATS(scp->device->host, exe_noerror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8517) * Increment monotonically increasing per device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8518) * successful request counter. Wrapping doesn't matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8520) boardp->reqcnt[scp->device->id]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8521) ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8523) case ASC_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8524) ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8525) ASC_STATS(scp->device->host, exe_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8527) case ASC_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8528) scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8529) "err_code 0x%x\n", err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8530) ASC_STATS(scp->device->host, exe_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8531) scp->result = HOST_BYTE(DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8533) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8534) scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8535) "err_code 0x%x\n", err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8536) ASC_STATS(scp->device->host, exe_unknown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8537) scp->result = HOST_BYTE(DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8541) ASC_DBG(1, "end\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8546) * advansys_queuecommand() - interrupt-driven I/O entrypoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8548) * This function always returns 0. Command return status is saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8549) * in the 'scp' result field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8551) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8552) advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8554) struct Scsi_Host *shost = scp->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8555) int asc_res, result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8557) ASC_STATS(shost, queuecommand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8558) scp->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8560) asc_res = asc_execute_scsi_cmnd(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8562) switch (asc_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8563) case ASC_NOERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8565) case ASC_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8566) result = SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8568) case ASC_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8569) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8570) asc_scsi_done(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8574) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8577) static DEF_SCSI_QCMD(advansys_queuecommand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8579) static ushort AscGetEisaChipCfg(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8581) PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8582) (PortAddr) (ASC_EISA_CFG_IOP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8583) return inpw(eisa_cfg_iop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8587) * Return the BIOS address of the adapter at the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8588) * I/O port and with the specified bus type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8590) static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8591) unsigned short bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8593) unsigned short cfg_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8594) unsigned short bios_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8597) * The PCI BIOS is re-located by the motherboard BIOS. Because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8598) * of this the driver can not determine where a PCI BIOS is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8599) * loaded and executes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8601) if (bus_type & ASC_IS_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8604) if ((bus_type & ASC_IS_EISA) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8605) cfg_lsw = AscGetEisaChipCfg(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8606) cfg_lsw &= 0x000F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8607) bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8608) return bios_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8611) cfg_lsw = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8614) * ISA PnP uses the top bit as the 32K BIOS flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8616) if (bus_type == ASC_IS_ISAPNP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8617) cfg_lsw &= 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8618) bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8619) return bios_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8622) static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8624) ushort cfg_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8626) if (AscGetChipScsiID(iop_base) == new_host_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8627) return (new_host_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8629) cfg_lsw = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8630) cfg_lsw &= 0xF8FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8631) cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8632) AscSetChipCfgLsw(iop_base, cfg_lsw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8633) return (AscGetChipScsiID(iop_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8636) static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8638) unsigned char sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8640) AscSetBank(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8641) sc = inp(iop_base + IOP_REG_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8642) AscSetBank(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8643) return sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8646) static unsigned char AscGetChipVersion(PortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8647) unsigned short bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8649) if (bus_type & ASC_IS_EISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8650) PortAddr eisa_iop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8651) unsigned char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8652) eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8653) (PortAddr) ASC_EISA_REV_IOP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8654) revision = inp(eisa_iop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8655) return ASC_CHIP_MIN_VER_EISA - 1 + revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8657) return AscGetChipVerNo(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8660) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8661) static void AscEnableIsaDma(uchar dma_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8663) if (dma_channel < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8664) outp(0x000B, (ushort)(0xC0 | dma_channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8665) outp(0x000A, dma_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8666) } else if (dma_channel < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8667) outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8668) outp(0x00D4, (ushort)(dma_channel - 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8671) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8673) static int AscStopQueueExe(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8675) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8677) if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8678) AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8679) ASC_STOP_REQ_RISC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8680) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8681) if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8682) ASC_STOP_ACK_RISC_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8683) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8685) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8686) } while (count++ < 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8688) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8691) static unsigned int AscGetMaxDmaCount(ushort bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8693) if (bus_type & ASC_IS_ISA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8694) return ASC_MAX_ISA_DMA_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8695) else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8696) return ASC_MAX_VL_DMA_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8697) return ASC_MAX_PCI_DMA_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8700) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8701) static ushort AscGetIsaDmaChannel(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8703) ushort channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8705) channel = AscGetChipCfgLsw(iop_base) & 0x0003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8706) if (channel == 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8707) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8708) else if (channel == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8709) return (7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8710) return (channel + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8713) static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8715) ushort cfg_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8716) uchar value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8718) if ((dma_channel >= 5) && (dma_channel <= 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8719) if (dma_channel == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8720) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8722) value = dma_channel - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8723) cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8724) cfg_lsw |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8725) AscSetChipCfgLsw(iop_base, cfg_lsw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8726) return (AscGetIsaDmaChannel(iop_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8731) static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8733) uchar speed_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8735) AscSetBank(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8736) speed_value = AscReadChipDmaSpeed(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8737) speed_value &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8738) AscSetBank(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8739) return speed_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8742) static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8744) speed_value &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8745) AscSetBank(iop_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8746) AscWriteChipDmaSpeed(iop_base, speed_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8747) AscSetBank(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8748) return AscGetIsaDmaSpeed(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8750) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8752) static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8754) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8755) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8756) uchar chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8758) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8759) asc_dvc->err_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8760) if ((asc_dvc->bus_type &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8761) (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8762) asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8764) AscSetChipControl(iop_base, CC_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8765) AscSetChipStatus(iop_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8766) asc_dvc->bug_fix_cntl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8767) asc_dvc->pci_fix_asyn_xfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8768) asc_dvc->pci_fix_asyn_xfer_always = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8769) /* asc_dvc->init_state initialized in AscInitGetConfig(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8770) asc_dvc->sdtr_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8771) asc_dvc->cur_total_qng = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8772) asc_dvc->is_in_int = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8773) asc_dvc->in_critical_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8774) asc_dvc->last_q_shortage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8775) asc_dvc->use_tagged_qng = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8776) asc_dvc->no_scam = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8777) asc_dvc->unit_not_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8778) asc_dvc->queue_full_or_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8779) asc_dvc->redo_scam = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8780) asc_dvc->res2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8781) asc_dvc->min_sdtr_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8782) asc_dvc->cfg->can_tagged_qng = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8783) asc_dvc->cfg->cmd_qng_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8784) asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8785) asc_dvc->init_sdtr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8786) asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8787) asc_dvc->scsi_reset_wait = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8788) asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8789) asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8790) asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8791) asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8792) asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8793) chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8794) asc_dvc->cfg->chip_version = chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8795) asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8796) asc_dvc->max_sdtr_index = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8797) if ((asc_dvc->bus_type & ASC_IS_PCI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8798) (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8799) asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8800) asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8801) asc_dvc->max_sdtr_index = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8802) if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8803) AscSetExtraControl(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8804) (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8805) } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8806) AscSetExtraControl(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8807) (SEC_ACTIVE_NEGATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8808) SEC_ENABLE_FILTER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8811) if (asc_dvc->bus_type == ASC_IS_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8812) AscSetExtraControl(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8813) (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8816) asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8817) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8818) if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8819) if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8820) AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8821) asc_dvc->bus_type = ASC_IS_ISAPNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8823) asc_dvc->cfg->isa_dma_channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8824) (uchar)AscGetIsaDmaChannel(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8826) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8827) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8828) asc_dvc->cur_dvc_qng[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8829) asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8830) asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8831) asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8832) asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8836) static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8838) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8840) for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8841) unsigned char read_back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8842) AscSetChipEEPCmd(iop_base, cmd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8843) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8844) read_back = AscGetChipEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8845) if (read_back == cmd_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8846) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8851) static void AscWaitEEPRead(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8853) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8856) static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8858) ushort read_wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8859) uchar cmd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8861) AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8862) AscWaitEEPRead();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8863) cmd_reg = addr | ASC_EEP_CMD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8864) AscWriteEEPCmdReg(iop_base, cmd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8865) AscWaitEEPRead();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8866) read_wval = AscGetChipEEPData(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8867) AscWaitEEPRead();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8868) return read_wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8871) static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8872) ushort bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8874) ushort wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8875) ushort sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8876) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8877) int cfg_beg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8878) int cfg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8879) int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8880) int s_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8882) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8883) sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8884) /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8885) for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8886) *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8887) sum += *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8889) if (bus_type & ASC_IS_VL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8890) cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8891) cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8893) cfg_beg = ASC_EEP_DVC_CFG_BEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8894) cfg_end = ASC_EEP_MAX_DVC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8896) for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8897) wval = AscReadEEPWord(iop_base, (uchar)s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8898) if (s_addr <= uchar_end_in_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8900) * Swap all char fields - must unswap bytes already swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8901) * by AscReadEEPWord().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8903) *wbuf = le16_to_cpu(wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8904) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8905) /* Don't swap word field at the end - cntl field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8906) *wbuf = wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8908) sum += wval; /* Checksum treats all EEPROM data as words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8911) * Read the checksum word which will be compared against 'sum'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8912) * by the caller. Word field already swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8914) *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8915) return sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8918) static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8920) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8921) ushort q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8922) ushort saved_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8923) int sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8925) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8926) sta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8927) q_addr = ASC_QNO_TO_QADDR(241);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8928) saved_word = AscReadLramWord(iop_base, q_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8929) AscSetChipLramAddr(iop_base, q_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8930) AscSetChipLramData(iop_base, 0x55AA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8931) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8932) AscSetChipLramAddr(iop_base, q_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8933) if (AscGetChipLramData(iop_base) == 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8934) sta = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8935) AscWriteLramWord(iop_base, q_addr, saved_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8937) return (sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8940) static void AscWaitEEPWrite(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8942) mdelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8945) static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8947) ushort read_back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8948) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8950) retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8951) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8952) AscSetChipEEPData(iop_base, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8953) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8954) read_back = AscGetChipEEPData(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8955) if (read_back == data_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8956) return (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8958) if (retry++ > ASC_EEP_MAX_RETRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8959) return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8964) static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8966) ushort read_wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8968) read_wval = AscReadEEPWord(iop_base, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8969) if (read_wval != word_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8970) AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8971) AscWaitEEPRead();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8972) AscWriteEEPDataReg(iop_base, word_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8973) AscWaitEEPRead();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8974) AscWriteEEPCmdReg(iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8975) (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8976) AscWaitEEPWrite();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8977) AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8978) AscWaitEEPRead();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8979) return (AscReadEEPWord(iop_base, addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8981) return (read_wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8984) static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8985) ushort bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8987) int n_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8988) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8989) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8990) ushort sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8991) int s_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8992) int cfg_beg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8993) int cfg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8994) int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8996) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8997) n_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8998) sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8999) /* Write two config words; AscWriteEEPWord() will swap bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9000) for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9001) sum += *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9002) if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9003) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9006) if (bus_type & ASC_IS_VL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9007) cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9008) cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9009) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9010) cfg_beg = ASC_EEP_DVC_CFG_BEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9011) cfg_end = ASC_EEP_MAX_DVC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9013) for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9014) if (s_addr <= uchar_end_in_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9016) * This is a char field. Swap char fields before they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9017) * swapped again by AscWriteEEPWord().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9019) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9020) if (word !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9021) AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9022) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9024) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9025) /* Don't swap word field at the end - cntl field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9026) if (*wbuf !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9027) AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9028) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9031) sum += *wbuf; /* Checksum calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9033) /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9034) *wbuf = sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9035) if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9036) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9039) /* Read EEPROM back again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9040) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9042) * Read two config words; Byte-swapping done by AscReadEEPWord().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9044) for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9045) if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9046) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9049) if (bus_type & ASC_IS_VL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9050) cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9051) cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9052) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9053) cfg_beg = ASC_EEP_DVC_CFG_BEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9054) cfg_end = ASC_EEP_MAX_DVC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9056) for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9057) if (s_addr <= uchar_end_in_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9059) * Swap all char fields. Must unswap bytes already swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9060) * by AscReadEEPWord().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9062) word =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9063) le16_to_cpu(AscReadEEPWord
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9064) (iop_base, (uchar)s_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9066) /* Don't swap word field at the end - cntl field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9067) word = AscReadEEPWord(iop_base, (uchar)s_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9069) if (*wbuf != word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9070) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9073) /* Read checksum; Byte swapping not needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9074) if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9075) n_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9077) return n_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9080) static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9081) ushort bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9083) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9084) int n_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9086) retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9087) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9088) if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9089) bus_type)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9092) if (++retry > ASC_EEP_MAX_RETRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9096) return n_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9099) static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9101) ASCEEP_CONFIG eep_config_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9102) ASCEEP_CONFIG *eep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9103) PortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9104) ushort chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9105) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9106) ushort cfg_msw, cfg_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9107) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9108) int write_eep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9110) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9111) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9112) AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9113) AscStopQueueExe(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9114) if ((AscStopChip(iop_base)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9115) (AscGetChipScsiCtrl(iop_base) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9116) asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9117) AscResetChipAndScsiBus(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9118) mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9120) if (!AscIsChipHalted(iop_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9121) asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9122) return (warn_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9124) AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9125) if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9126) asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9127) return (warn_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9129) eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9130) cfg_msw = AscGetChipCfgMsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9131) cfg_lsw = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9132) if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9133) cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9134) warn_code |= ASC_WARN_CFG_MSW_RECOVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9135) AscSetChipCfgMsw(iop_base, cfg_msw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9137) chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9138) ASC_DBG(1, "chksum 0x%x\n", chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9139) if (chksum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9140) chksum = 0xaa55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9142) if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9143) warn_code |= ASC_WARN_AUTO_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9144) if (asc_dvc->cfg->chip_version == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9145) if (eep_config->cfg_lsw != cfg_lsw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9146) warn_code |= ASC_WARN_EEPROM_RECOVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9147) eep_config->cfg_lsw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9148) AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9150) if (eep_config->cfg_msw != cfg_msw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9151) warn_code |= ASC_WARN_EEPROM_RECOVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9152) eep_config->cfg_msw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9153) AscGetChipCfgMsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9157) eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9158) eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9159) ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9160) if (chksum != eep_config->chksum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9161) if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9162) ASC_CHIP_VER_PCI_ULTRA_3050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9163) ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9164) eep_config->init_sdtr = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9165) eep_config->disc_enable = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9166) eep_config->start_motor = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9167) eep_config->use_cmd_qng = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9168) eep_config->max_total_qng = 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9169) eep_config->max_tag_qng = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9170) eep_config->cntl = 0xBFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9171) ASC_EEP_SET_CHIP_ID(eep_config, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9172) eep_config->no_scam = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9173) eep_config->adapter_info[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9174) eep_config->adapter_info[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9175) eep_config->adapter_info[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9176) eep_config->adapter_info[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9177) eep_config->adapter_info[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9178) /* Indicate EEPROM-less board. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9179) eep_config->adapter_info[5] = 0xBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9181) ASC_PRINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9182) ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9183) write_eep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9184) warn_code |= ASC_WARN_EEPROM_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9187) asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9188) asc_dvc->cfg->disc_enable = eep_config->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9189) asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9190) asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9191) asc_dvc->start_motor = eep_config->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9192) asc_dvc->dvc_cntl = eep_config->cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9193) asc_dvc->no_scam = eep_config->no_scam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9194) asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9195) asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9196) asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9197) asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9198) asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9199) asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9200) if (!AscTestExternalLram(asc_dvc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9201) if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9202) ASC_IS_PCI_ULTRA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9203) eep_config->max_total_qng =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9204) ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9205) eep_config->max_tag_qng =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9206) ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9207) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9208) eep_config->cfg_msw |= 0x0800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9209) cfg_msw |= 0x0800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9210) AscSetChipCfgMsw(iop_base, cfg_msw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9211) eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9212) eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9216) if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9217) eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9219) if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9220) eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9222) if (eep_config->max_tag_qng > eep_config->max_total_qng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9223) eep_config->max_tag_qng = eep_config->max_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9225) if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9226) eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9228) asc_dvc->max_total_qng = eep_config->max_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9229) if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9230) eep_config->use_cmd_qng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9231) eep_config->disc_enable = eep_config->use_cmd_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9232) warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9234) ASC_EEP_SET_CHIP_ID(eep_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9235) ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9236) asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9237) if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9238) !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9239) asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9242) for (i = 0; i <= ASC_MAX_TID; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9243) asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9244) asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9245) asc_dvc->cfg->sdtr_period_offset[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9246) (uchar)(ASC_DEF_SDTR_OFFSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9247) (asc_dvc->min_sdtr_index << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9249) eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9250) if (write_eep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9251) if ((i = AscSetEEPConfig(iop_base, eep_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9252) asc_dvc->bus_type)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9253) ASC_PRINT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9254) ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9255) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9257) ASC_PRINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9258) ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9261) return (warn_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9264) static int AscInitGetConfig(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9266) struct asc_board *board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9267) ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9268) unsigned short warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9270) asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9271) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9272) return asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9274) if (AscFindSignature(asc_dvc->iop_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9275) AscInitAscDvcVar(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9276) warn_code = AscInitFromEEP(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9277) asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9278) if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9279) asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9281) asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9284) switch (warn_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9285) case 0: /* No error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9287) case ASC_WARN_IO_PORT_ROTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9288) shost_printk(KERN_WARNING, shost, "I/O port address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9289) "modified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9291) case ASC_WARN_AUTO_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9292) shost_printk(KERN_WARNING, shost, "I/O port increment switch "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9293) "enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9295) case ASC_WARN_EEPROM_CHKSUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9296) shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9298) case ASC_WARN_IRQ_MODIFIED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9299) shost_printk(KERN_WARNING, shost, "IRQ modified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9301) case ASC_WARN_CMD_QNG_CONFLICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9302) shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9303) "disconnects\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9305) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9306) shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9307) warn_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9311) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9312) shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9313) "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9315) return asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9318) static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9320) struct asc_board *board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9321) ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9322) PortAddr iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9323) unsigned short cfg_msw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9324) unsigned short warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9326) asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9327) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9328) return asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9329) if (!AscFindSignature(asc_dvc->iop_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9330) asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9331) return asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9334) cfg_msw = AscGetChipCfgMsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9335) if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9336) cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9337) warn_code |= ASC_WARN_CFG_MSW_RECOVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9338) AscSetChipCfgMsw(iop_base, cfg_msw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9340) if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9341) asc_dvc->cfg->cmd_qng_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9342) asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9343) warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9345) if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9346) warn_code |= ASC_WARN_AUTO_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9348) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9349) if (asc_dvc->bus_type & ASC_IS_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9350) cfg_msw &= 0xFFC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9351) AscSetChipCfgMsw(iop_base, cfg_msw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9352) if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9354) if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9355) (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9356) asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9357) asc_dvc->bug_fix_cntl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9358) ASC_BUG_FIX_ASYN_USE_SYN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9361) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9362) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9363) if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9364) if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9365) == ASC_CHIP_VER_ASYN_BUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9366) asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9369) if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9370) asc_dvc->cfg->chip_scsi_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9371) asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9373) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9374) if (asc_dvc->bus_type & ASC_IS_ISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9375) AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9376) AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9378) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9380) asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9382) switch (warn_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9383) case 0: /* No error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9385) case ASC_WARN_IO_PORT_ROTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9386) shost_printk(KERN_WARNING, shost, "I/O port address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9387) "modified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9389) case ASC_WARN_AUTO_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9390) shost_printk(KERN_WARNING, shost, "I/O port increment switch "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9391) "enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9393) case ASC_WARN_EEPROM_CHKSUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9394) shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9396) case ASC_WARN_IRQ_MODIFIED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9397) shost_printk(KERN_WARNING, shost, "IRQ modified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9399) case ASC_WARN_CMD_QNG_CONFLICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9400) shost_printk(KERN_WARNING, shost, "tag queuing w/o "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9401) "disconnects\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9403) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9404) shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9405) warn_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9409) if (asc_dvc->err_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9410) shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9411) "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9413) return asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9417) * EEPROM Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9419) * All drivers should use this structure to set the default EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9420) * configuration. The BIOS now uses this structure when it is built.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9421) * Additional structure information can be found in a_condor.h where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9422) * the structure is defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9424) * The *_Field_IsChar structs are needed to correct for endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9425) * These values are read from the board 16 bits at a time directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9426) * into the structs. Because some fields are char, the values will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9427) * in the wrong order. The *_Field_IsChar tells when to flip the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9428) * bytes. Data read and written to PCI memory is automatically swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9429) * on big-endian platforms so char fields read as words are actually being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9430) * unswapped on big-endian platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9432) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9433) static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9434) ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9435) 0x0000, /* cfg_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9436) 0xFFFF, /* disc_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9437) 0xFFFF, /* wdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9438) 0xFFFF, /* sdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9439) 0xFFFF, /* start_motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9440) 0xFFFF, /* tagqng_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9441) 0xFFFF, /* bios_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9442) 0, /* scam_tolerant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9443) 7, /* adapter_scsi_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9444) 0, /* bios_boot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9445) 3, /* scsi_reset_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9446) 0, /* bios_id_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9447) 0, /* termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9448) 0, /* reserved1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9449) 0xFFE7, /* bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9450) 0xFFFF, /* ultra_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9451) 0, /* reserved2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9452) ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9453) ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9454) 0, /* dvc_cntl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9455) 0, /* bug_fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9456) 0, /* serial_number_word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9457) 0, /* serial_number_word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9458) 0, /* serial_number_word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9459) 0, /* check_sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9460) {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9461) , /* oem_name[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9462) 0, /* dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9463) 0, /* adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9464) 0, /* adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9465) 0, /* saved_dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9466) 0, /* saved_adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9467) 0, /* saved_adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9468) 0 /* num_of_err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9471) static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9472) 0, /* cfg_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9473) 0, /* cfg_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9474) 0, /* -disc_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9475) 0, /* wdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9476) 0, /* sdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9477) 0, /* start_motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9478) 0, /* tagqng_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9479) 0, /* bios_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9480) 0, /* scam_tolerant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9481) 1, /* adapter_scsi_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9482) 1, /* bios_boot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9483) 1, /* scsi_reset_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9484) 1, /* bios_id_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9485) 1, /* termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9486) 1, /* reserved1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9487) 0, /* bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9488) 0, /* ultra_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9489) 0, /* reserved2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9490) 1, /* max_host_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9491) 1, /* max_dvc_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9492) 0, /* dvc_cntl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9493) 0, /* bug_fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9494) 0, /* serial_number_word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9495) 0, /* serial_number_word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9496) 0, /* serial_number_word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9497) 0, /* check_sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9498) {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9499) , /* oem_name[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9500) 0, /* dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9501) 0, /* adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9502) 0, /* adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9503) 0, /* saved_dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9504) 0, /* saved_adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9505) 0, /* saved_adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9506) 0 /* num_of_err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9509) static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9510) ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9511) 0x0000, /* 01 cfg_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9512) 0xFFFF, /* 02 disc_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9513) 0xFFFF, /* 03 wdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9514) 0x4444, /* 04 sdtr_speed1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9515) 0xFFFF, /* 05 start_motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9516) 0xFFFF, /* 06 tagqng_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9517) 0xFFFF, /* 07 bios_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9518) 0, /* 08 scam_tolerant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9519) 7, /* 09 adapter_scsi_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9520) 0, /* bios_boot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9521) 3, /* 10 scsi_reset_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9522) 0, /* bios_id_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9523) 0, /* 11 termination_se */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9524) 0, /* termination_lvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9525) 0xFFE7, /* 12 bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9526) 0x4444, /* 13 sdtr_speed2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9527) 0x4444, /* 14 sdtr_speed3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9528) ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9529) ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9530) 0, /* 16 dvc_cntl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9531) 0x4444, /* 17 sdtr_speed4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9532) 0, /* 18 serial_number_word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9533) 0, /* 19 serial_number_word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9534) 0, /* 20 serial_number_word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9535) 0, /* 21 check_sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9536) {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9537) , /* 22-29 oem_name[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9538) 0, /* 30 dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9539) 0, /* 31 adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9540) 0, /* 32 adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9541) 0, /* 33 saved_dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9542) 0, /* 34 saved_adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9543) 0, /* 35 saved_adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9544) 0, /* 36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9545) 0, /* 37 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9546) 0, /* 38 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9547) 0, /* 39 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9548) 0, /* 40 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9549) 0, /* 41 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9550) 0, /* 42 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9551) 0, /* 43 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9552) 0, /* 44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9553) 0, /* 45 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9554) 0, /* 46 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9555) 0, /* 47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9556) 0, /* 48 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9557) 0, /* 49 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9558) 0, /* 50 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9559) 0, /* 51 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9560) 0, /* 52 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9561) 0, /* 53 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9562) 0, /* 54 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9563) 0, /* 55 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9564) 0, /* 56 cisptr_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9565) 0, /* 57 cisprt_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9566) PCI_VENDOR_ID_ASP, /* 58 subsysvid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9567) PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9568) 0, /* 60 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9569) 0, /* 61 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9570) 0, /* 62 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9571) 0 /* 63 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9574) static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9575) 0, /* 00 cfg_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9576) 0, /* 01 cfg_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9577) 0, /* 02 disc_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9578) 0, /* 03 wdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9579) 0, /* 04 sdtr_speed1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9580) 0, /* 05 start_motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9581) 0, /* 06 tagqng_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9582) 0, /* 07 bios_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9583) 0, /* 08 scam_tolerant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9584) 1, /* 09 adapter_scsi_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9585) 1, /* bios_boot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9586) 1, /* 10 scsi_reset_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9587) 1, /* bios_id_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9588) 1, /* 11 termination_se */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9589) 1, /* termination_lvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9590) 0, /* 12 bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9591) 0, /* 13 sdtr_speed2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9592) 0, /* 14 sdtr_speed3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9593) 1, /* 15 max_host_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9594) 1, /* max_dvc_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9595) 0, /* 16 dvc_cntl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9596) 0, /* 17 sdtr_speed4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9597) 0, /* 18 serial_number_word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9598) 0, /* 19 serial_number_word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9599) 0, /* 20 serial_number_word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9600) 0, /* 21 check_sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9601) {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9602) , /* 22-29 oem_name[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9603) 0, /* 30 dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9604) 0, /* 31 adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9605) 0, /* 32 adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9606) 0, /* 33 saved_dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9607) 0, /* 34 saved_adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9608) 0, /* 35 saved_adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9609) 0, /* 36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9610) 0, /* 37 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9611) 0, /* 38 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9612) 0, /* 39 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9613) 0, /* 40 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9614) 0, /* 41 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9615) 0, /* 42 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9616) 0, /* 43 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9617) 0, /* 44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9618) 0, /* 45 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9619) 0, /* 46 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9620) 0, /* 47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9621) 0, /* 48 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9622) 0, /* 49 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9623) 0, /* 50 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9624) 0, /* 51 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9625) 0, /* 52 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9626) 0, /* 53 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9627) 0, /* 54 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9628) 0, /* 55 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9629) 0, /* 56 cisptr_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9630) 0, /* 57 cisprt_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9631) 0, /* 58 subsysvid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9632) 0, /* 59 subsysid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9633) 0, /* 60 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9634) 0, /* 61 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9635) 0, /* 62 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9636) 0 /* 63 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9639) static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9640) ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9641) 0x0000, /* 01 cfg_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9642) 0xFFFF, /* 02 disc_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9643) 0xFFFF, /* 03 wdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9644) 0x5555, /* 04 sdtr_speed1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9645) 0xFFFF, /* 05 start_motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9646) 0xFFFF, /* 06 tagqng_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9647) 0xFFFF, /* 07 bios_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9648) 0, /* 08 scam_tolerant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9649) 7, /* 09 adapter_scsi_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9650) 0, /* bios_boot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9651) 3, /* 10 scsi_reset_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9652) 0, /* bios_id_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9653) 0, /* 11 termination_se */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9654) 0, /* termination_lvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9655) 0xFFE7, /* 12 bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9656) 0x5555, /* 13 sdtr_speed2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9657) 0x5555, /* 14 sdtr_speed3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9658) ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9659) ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9660) 0, /* 16 dvc_cntl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9661) 0x5555, /* 17 sdtr_speed4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9662) 0, /* 18 serial_number_word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9663) 0, /* 19 serial_number_word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9664) 0, /* 20 serial_number_word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9665) 0, /* 21 check_sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9666) {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9667) , /* 22-29 oem_name[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9668) 0, /* 30 dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9669) 0, /* 31 adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9670) 0, /* 32 adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9671) 0, /* 33 saved_dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9672) 0, /* 34 saved_adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9673) 0, /* 35 saved_adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9674) 0, /* 36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9675) 0, /* 37 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9676) 0, /* 38 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9677) 0, /* 39 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9678) 0, /* 40 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9679) 0, /* 41 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9680) 0, /* 42 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9681) 0, /* 43 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9682) 0, /* 44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9683) 0, /* 45 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9684) 0, /* 46 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9685) 0, /* 47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9686) 0, /* 48 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9687) 0, /* 49 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9688) 0, /* 50 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9689) 0, /* 51 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9690) 0, /* 52 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9691) 0, /* 53 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9692) 0, /* 54 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9693) 0, /* 55 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9694) 0, /* 56 cisptr_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9695) 0, /* 57 cisprt_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9696) PCI_VENDOR_ID_ASP, /* 58 subsysvid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9697) PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9698) 0, /* 60 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9699) 0, /* 61 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9700) 0, /* 62 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9701) 0 /* 63 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9704) static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9705) 0, /* 00 cfg_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9706) 0, /* 01 cfg_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9707) 0, /* 02 disc_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9708) 0, /* 03 wdtr_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9709) 0, /* 04 sdtr_speed1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9710) 0, /* 05 start_motor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9711) 0, /* 06 tagqng_able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9712) 0, /* 07 bios_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9713) 0, /* 08 scam_tolerant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9714) 1, /* 09 adapter_scsi_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9715) 1, /* bios_boot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9716) 1, /* 10 scsi_reset_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9717) 1, /* bios_id_lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9718) 1, /* 11 termination_se */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9719) 1, /* termination_lvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9720) 0, /* 12 bios_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9721) 0, /* 13 sdtr_speed2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9722) 0, /* 14 sdtr_speed3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9723) 1, /* 15 max_host_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9724) 1, /* max_dvc_qng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9725) 0, /* 16 dvc_cntl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9726) 0, /* 17 sdtr_speed4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9727) 0, /* 18 serial_number_word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9728) 0, /* 19 serial_number_word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9729) 0, /* 20 serial_number_word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9730) 0, /* 21 check_sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9731) {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9732) , /* 22-29 oem_name[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9733) 0, /* 30 dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9734) 0, /* 31 adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9735) 0, /* 32 adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9736) 0, /* 33 saved_dvc_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9737) 0, /* 34 saved_adv_err_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9738) 0, /* 35 saved_adv_err_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9739) 0, /* 36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9740) 0, /* 37 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9741) 0, /* 38 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9742) 0, /* 39 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9743) 0, /* 40 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9744) 0, /* 41 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9745) 0, /* 42 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9746) 0, /* 43 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9747) 0, /* 44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9748) 0, /* 45 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9749) 0, /* 46 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9750) 0, /* 47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9751) 0, /* 48 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9752) 0, /* 49 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9753) 0, /* 50 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9754) 0, /* 51 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9755) 0, /* 52 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9756) 0, /* 53 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9757) 0, /* 54 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9758) 0, /* 55 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9759) 0, /* 56 cisptr_lsw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9760) 0, /* 57 cisprt_msw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9761) 0, /* 58 subsysvid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9762) 0, /* 59 subsysid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9763) 0, /* 60 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9764) 0, /* 61 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9765) 0, /* 62 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9766) 0 /* 63 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9770) * Wait for EEPROM command to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9772) static void AdvWaitEEPCmd(AdvPortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9774) int eep_delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9776) for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9777) if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9778) ASC_EEP_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9781) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9783) if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9784) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9785) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9789) * Read the EEPROM from specified location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9791) static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9793) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9794) ASC_EEP_CMD_READ | eep_word_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9795) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9796) return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9800) * Write the EEPROM from 'cfg_buf'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9802) static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9803) ADVEEP_3550_CONFIG *cfg_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9805) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9806) ushort addr, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9807) ushort *charfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9809) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9810) charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9811) chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9813) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9814) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9817) * Write EEPROM from word 0 to word 20.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9819) for (addr = ADV_EEP_DVC_CFG_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9820) addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9821) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9823) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9824) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9826) word = *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9828) chksum += *wbuf; /* Checksum is calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9829) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9830) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9831) ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9832) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9833) mdelay(ADV_EEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9837) * Write EEPROM checksum at word 21.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9839) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9840) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9841) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9842) wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9843) charfields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9846) * Write EEPROM OEM name at words 22 to 29.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9848) for (addr = ADV_EEP_DVC_CTL_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9849) addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9850) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9852) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9853) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9854) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9855) word = *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9857) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9858) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9859) ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9860) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9862) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9863) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9867) * Write the EEPROM from 'cfg_buf'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9869) static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9870) ADVEEP_38C0800_CONFIG *cfg_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9872) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9873) ushort *charfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9874) ushort addr, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9876) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9877) charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9878) chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9880) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9881) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9884) * Write EEPROM from word 0 to word 20.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9886) for (addr = ADV_EEP_DVC_CFG_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9887) addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9888) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9890) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9891) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9893) word = *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9895) chksum += *wbuf; /* Checksum is calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9896) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9897) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9898) ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9899) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9900) mdelay(ADV_EEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9904) * Write EEPROM checksum at word 21.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9906) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9907) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9908) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9909) wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9910) charfields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9913) * Write EEPROM OEM name at words 22 to 29.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9915) for (addr = ADV_EEP_DVC_CTL_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9916) addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9917) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9919) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9920) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9921) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9922) word = *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9924) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9925) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9926) ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9927) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9929) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9930) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9934) * Write the EEPROM from 'cfg_buf'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9936) static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9937) ADVEEP_38C1600_CONFIG *cfg_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9939) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9940) ushort *charfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9941) ushort addr, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9943) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9944) charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9945) chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9947) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9948) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9951) * Write EEPROM from word 0 to word 20.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9953) for (addr = ADV_EEP_DVC_CFG_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9954) addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9955) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9957) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9958) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9959) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9960) word = *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9962) chksum += *wbuf; /* Checksum is calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9963) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9964) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9965) ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9966) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9967) mdelay(ADV_EEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9971) * Write EEPROM checksum at word 21.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9973) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9974) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9975) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9976) wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9977) charfields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9980) * Write EEPROM OEM name at words 22 to 29.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9982) for (addr = ADV_EEP_DVC_CTL_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9983) addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9984) ushort word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9986) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9987) word = cpu_to_le16(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9988) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9989) word = *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9991) AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9992) AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9993) ASC_EEP_CMD_WRITE | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9994) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9996) AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9997) AdvWaitEEPCmd(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10001) * Read EEPROM configuration into the specified buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10003) * Return a checksum based on the EEPROM configuration read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10005) static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10006) ADVEEP_3550_CONFIG *cfg_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10008) ushort wval, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10009) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10010) int eep_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10011) ushort *charfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10013) charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10014) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10015) chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10017) for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10018) eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10019) wval = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10020) chksum += wval; /* Checksum is calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10021) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10022) *wbuf = le16_to_cpu(wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10023) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10024) *wbuf = wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10027) /* Read checksum word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10028) *wbuf = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10029) wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10030) charfields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10032) /* Read rest of EEPROM not covered by the checksum. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10033) for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10034) eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10035) *wbuf = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10036) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10037) *wbuf = le16_to_cpu(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10040) return chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10043) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10044) * Read EEPROM configuration into the specified buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10046) * Return a checksum based on the EEPROM configuration read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10047) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10048) static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10049) ADVEEP_38C0800_CONFIG *cfg_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10051) ushort wval, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10052) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10053) int eep_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10054) ushort *charfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10056) charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10057) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10058) chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10060) for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10061) eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10062) wval = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10063) chksum += wval; /* Checksum is calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10064) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10065) *wbuf = le16_to_cpu(wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10066) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10067) *wbuf = wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10070) /* Read checksum word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10071) *wbuf = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10072) wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10073) charfields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10075) /* Read rest of EEPROM not covered by the checksum. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10076) for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10077) eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10078) *wbuf = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10079) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10080) *wbuf = le16_to_cpu(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10083) return chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10087) * Read EEPROM configuration into the specified buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10088) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10089) * Return a checksum based on the EEPROM configuration read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10091) static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10092) ADVEEP_38C1600_CONFIG *cfg_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10094) ushort wval, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10095) ushort *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10096) int eep_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10097) ushort *charfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10099) charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10100) wbuf = (ushort *)cfg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10101) chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10103) for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10104) eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10105) wval = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10106) chksum += wval; /* Checksum is calculated from word values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10107) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10108) *wbuf = le16_to_cpu(wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10110) *wbuf = wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10113) /* Read checksum word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10114) *wbuf = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10115) wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10116) charfields++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10118) /* Read rest of EEPROM not covered by the checksum. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10119) for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10120) eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10121) *wbuf = AdvReadEEPWord(iop_base, eep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10122) if (*charfields++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10123) *wbuf = le16_to_cpu(*wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10126) return chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10130) * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10131) * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10132) * all of this is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10134) * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10136) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10137) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10139) * Note: Chip is stopped on entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10141) static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10143) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10144) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10145) ADVEEP_3550_CONFIG eep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10147) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10149) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10152) * Read the board's EEPROM configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10154) * Set default values if a bad checksum is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10156) if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10157) warn_code |= ASC_WARN_EEPROM_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10160) * Set EEPROM default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10162) memcpy(&eep_config, &Default_3550_EEPROM_Config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10163) sizeof(ADVEEP_3550_CONFIG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10166) * Assume the 6 byte board serial number that was read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10167) * EEPROM is correct even if the EEPROM checksum failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10169) eep_config.serial_number_word3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10170) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10172) eep_config.serial_number_word2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10173) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10175) eep_config.serial_number_word1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10176) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10178) AdvSet3550EEPConfig(iop_base, &eep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10181) * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10182) * EEPROM configuration that was read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10184) * This is the mapping of EEPROM fields to Adv Library fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10186) asc_dvc->wdtr_able = eep_config.wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10187) asc_dvc->sdtr_able = eep_config.sdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10188) asc_dvc->ultra_able = eep_config.ultra_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10189) asc_dvc->tagqng_able = eep_config.tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10190) asc_dvc->cfg->disc_enable = eep_config.disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10191) asc_dvc->max_host_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10192) asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10193) asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10194) asc_dvc->start_motor = eep_config.start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10195) asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10196) asc_dvc->bios_ctrl = eep_config.bios_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10197) asc_dvc->no_scam = eep_config.scam_tolerant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10198) asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10199) asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10200) asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10203) * Set the host maximum queuing (max. 253, min. 16) and the per device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10204) * maximum queuing (max. 63, min. 4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10206) if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10207) eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10208) } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10209) /* If the value is zero, assume it is uninitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10210) if (eep_config.max_host_qng == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10211) eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10213) eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10217) if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10218) eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10219) } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10220) /* If the value is zero, assume it is uninitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10221) if (eep_config.max_dvc_qng == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10222) eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10224) eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10229) * If 'max_dvc_qng' is greater than 'max_host_qng', then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10230) * set 'max_dvc_qng' to 'max_host_qng'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10232) if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10233) eep_config.max_dvc_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10237) * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10238) * values based on possibly adjusted EEPROM values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10240) asc_dvc->max_host_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10241) asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10244) * If the EEPROM 'termination' field is set to automatic (0), then set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10245) * the ADV_DVC_CFG 'termination' field to automatic also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10247) * If the termination is specified with a non-zero 'termination'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10248) * value check that a legal value is set and set the ADV_DVC_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10249) * 'termination' field appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10251) if (eep_config.termination == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10252) asc_dvc->cfg->termination = 0; /* auto termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10254) /* Enable manual control with low off / high off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10255) if (eep_config.termination == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10256) asc_dvc->cfg->termination = TERM_CTL_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10258) /* Enable manual control with low off / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10259) } else if (eep_config.termination == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10260) asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10262) /* Enable manual control with low on / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10263) } else if (eep_config.termination == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10264) asc_dvc->cfg->termination =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10265) TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10266) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10268) * The EEPROM 'termination' field contains a bad value. Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10269) * automatic termination instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10271) asc_dvc->cfg->termination = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10272) warn_code |= ASC_WARN_EEPROM_TERMINATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10276) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10280) * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10281) * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10282) * all of this is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10284) * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10286) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10287) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10289) * Note: Chip is stopped on entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10291) static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10293) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10294) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10295) ADVEEP_38C0800_CONFIG eep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10296) uchar tid, termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10297) ushort sdtr_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10299) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10301) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10304) * Read the board's EEPROM configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10306) * Set default values if a bad checksum is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10308) if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10309) eep_config.check_sum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10310) warn_code |= ASC_WARN_EEPROM_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10313) * Set EEPROM default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10315) memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10316) sizeof(ADVEEP_38C0800_CONFIG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10319) * Assume the 6 byte board serial number that was read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10320) * EEPROM is correct even if the EEPROM checksum failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10322) eep_config.serial_number_word3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10323) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10325) eep_config.serial_number_word2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10326) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10328) eep_config.serial_number_word1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10329) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10331) AdvSet38C0800EEPConfig(iop_base, &eep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10334) * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10335) * EEPROM configuration that was read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10337) * This is the mapping of EEPROM fields to Adv Library fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10339) asc_dvc->wdtr_able = eep_config.wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10340) asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10341) asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10342) asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10343) asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10344) asc_dvc->tagqng_able = eep_config.tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10345) asc_dvc->cfg->disc_enable = eep_config.disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10346) asc_dvc->max_host_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10347) asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10348) asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10349) asc_dvc->start_motor = eep_config.start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10350) asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10351) asc_dvc->bios_ctrl = eep_config.bios_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10352) asc_dvc->no_scam = eep_config.scam_tolerant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10353) asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10354) asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10355) asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10358) * For every Target ID if any of its 'sdtr_speed[1234]' bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10359) * are set, then set an 'sdtr_able' bit for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10361) asc_dvc->sdtr_able = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10362) for (tid = 0; tid <= ADV_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10363) if (tid == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10364) sdtr_speed = asc_dvc->sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10365) } else if (tid == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10366) sdtr_speed = asc_dvc->sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10367) } else if (tid == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10368) sdtr_speed = asc_dvc->sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10369) } else if (tid == 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10370) sdtr_speed = asc_dvc->sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10372) if (sdtr_speed & ADV_MAX_TID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10373) asc_dvc->sdtr_able |= (1 << tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10375) sdtr_speed >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10379) * Set the host maximum queuing (max. 253, min. 16) and the per device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10380) * maximum queuing (max. 63, min. 4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10382) if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10383) eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10384) } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10385) /* If the value is zero, assume it is uninitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10386) if (eep_config.max_host_qng == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10387) eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10389) eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10393) if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10394) eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10395) } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10396) /* If the value is zero, assume it is uninitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10397) if (eep_config.max_dvc_qng == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10398) eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10399) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10400) eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10405) * If 'max_dvc_qng' is greater than 'max_host_qng', then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10406) * set 'max_dvc_qng' to 'max_host_qng'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10408) if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10409) eep_config.max_dvc_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10413) * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10414) * values based on possibly adjusted EEPROM values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10416) asc_dvc->max_host_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10417) asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10420) * If the EEPROM 'termination' field is set to automatic (0), then set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10421) * the ADV_DVC_CFG 'termination' field to automatic also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10422) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10423) * If the termination is specified with a non-zero 'termination'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10424) * value check that a legal value is set and set the ADV_DVC_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10425) * 'termination' field appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10427) if (eep_config.termination_se == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10428) termination = 0; /* auto termination for SE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10430) /* Enable manual control with low off / high off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10431) if (eep_config.termination_se == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10432) termination = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10434) /* Enable manual control with low off / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10435) } else if (eep_config.termination_se == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10436) termination = TERM_SE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10438) /* Enable manual control with low on / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10439) } else if (eep_config.termination_se == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10440) termination = TERM_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10443) * The EEPROM 'termination_se' field contains a bad value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10444) * Use automatic termination instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10446) termination = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10447) warn_code |= ASC_WARN_EEPROM_TERMINATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10451) if (eep_config.termination_lvd == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10452) asc_dvc->cfg->termination = termination; /* auto termination for LVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10454) /* Enable manual control with low off / high off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10455) if (eep_config.termination_lvd == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10456) asc_dvc->cfg->termination = termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10458) /* Enable manual control with low off / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10459) } else if (eep_config.termination_lvd == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10460) asc_dvc->cfg->termination = termination | TERM_LVD_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10462) /* Enable manual control with low on / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10463) } else if (eep_config.termination_lvd == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10464) asc_dvc->cfg->termination = termination | TERM_LVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10467) * The EEPROM 'termination_lvd' field contains a bad value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10468) * Use automatic termination instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10470) asc_dvc->cfg->termination = termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10471) warn_code |= ASC_WARN_EEPROM_TERMINATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10475) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10479) * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10480) * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10481) * all of this is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10483) * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10485) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10486) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10488) * Note: Chip is stopped on entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10490) static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10492) AdvPortAddr iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10493) ushort warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10494) ADVEEP_38C1600_CONFIG eep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10495) uchar tid, termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10496) ushort sdtr_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10498) iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10500) warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10503) * Read the board's EEPROM configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10505) * Set default values if a bad checksum is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10507) if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10508) eep_config.check_sum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10509) struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10510) warn_code |= ASC_WARN_EEPROM_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10513) * Set EEPROM default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10515) memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10516) sizeof(ADVEEP_38C1600_CONFIG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10518) if (PCI_FUNC(pdev->devfn) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10519) u8 ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10521) * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10522) * and old Mac system booting problem. The Expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10523) * ROM must be disabled in Function 1 for these systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10525) eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10527) * Clear the INTAB (bit 11) if the GPIO 0 input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10528) * indicates the Function 1 interrupt line is wired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10529) * to INTB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10530) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10531) * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10532) * 1 - Function 1 interrupt line wired to INT A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10533) * 0 - Function 1 interrupt line wired to INT B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10534) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10535) * Note: Function 0 is always wired to INTA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10536) * Put all 5 GPIO bits in input mode and then read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10537) * their input values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10539) AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10540) ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10541) if ((ints & 0x01) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10542) eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10546) * Assume the 6 byte board serial number that was read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10547) * EEPROM is correct even if the EEPROM checksum failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10549) eep_config.serial_number_word3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10550) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10551) eep_config.serial_number_word2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10552) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10553) eep_config.serial_number_word1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10554) AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10556) AdvSet38C1600EEPConfig(iop_base, &eep_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10560) * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10561) * EEPROM configuration that was read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10563) * This is the mapping of EEPROM fields to Adv Library fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10565) asc_dvc->wdtr_able = eep_config.wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10566) asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10567) asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10568) asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10569) asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10570) asc_dvc->ppr_able = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10571) asc_dvc->tagqng_able = eep_config.tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10572) asc_dvc->cfg->disc_enable = eep_config.disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10573) asc_dvc->max_host_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10574) asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10575) asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10576) asc_dvc->start_motor = eep_config.start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10577) asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10578) asc_dvc->bios_ctrl = eep_config.bios_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10579) asc_dvc->no_scam = eep_config.scam_tolerant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10582) * For every Target ID if any of its 'sdtr_speed[1234]' bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10583) * are set, then set an 'sdtr_able' bit for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10585) asc_dvc->sdtr_able = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10586) for (tid = 0; tid <= ASC_MAX_TID; tid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10587) if (tid == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10588) sdtr_speed = asc_dvc->sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10589) } else if (tid == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10590) sdtr_speed = asc_dvc->sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10591) } else if (tid == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10592) sdtr_speed = asc_dvc->sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10593) } else if (tid == 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10594) sdtr_speed = asc_dvc->sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10596) if (sdtr_speed & ASC_MAX_TID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10597) asc_dvc->sdtr_able |= (1 << tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10599) sdtr_speed >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10603) * Set the host maximum queuing (max. 253, min. 16) and the per device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10604) * maximum queuing (max. 63, min. 4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10606) if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10607) eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10608) } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10609) /* If the value is zero, assume it is uninitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10610) if (eep_config.max_host_qng == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10611) eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10612) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10613) eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10617) if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10618) eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10619) } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10620) /* If the value is zero, assume it is uninitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10621) if (eep_config.max_dvc_qng == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10622) eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10624) eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10629) * If 'max_dvc_qng' is greater than 'max_host_qng', then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10630) * set 'max_dvc_qng' to 'max_host_qng'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10632) if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10633) eep_config.max_dvc_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10637) * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10638) * values based on possibly adjusted EEPROM values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10640) asc_dvc->max_host_qng = eep_config.max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10641) asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10644) * If the EEPROM 'termination' field is set to automatic (0), then set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10645) * the ASC_DVC_CFG 'termination' field to automatic also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10646) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10647) * If the termination is specified with a non-zero 'termination'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10648) * value check that a legal value is set and set the ASC_DVC_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10649) * 'termination' field appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10651) if (eep_config.termination_se == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10652) termination = 0; /* auto termination for SE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10653) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10654) /* Enable manual control with low off / high off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10655) if (eep_config.termination_se == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10656) termination = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10658) /* Enable manual control with low off / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10659) } else if (eep_config.termination_se == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10660) termination = TERM_SE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10662) /* Enable manual control with low on / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10663) } else if (eep_config.termination_se == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10664) termination = TERM_SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10665) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10667) * The EEPROM 'termination_se' field contains a bad value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10668) * Use automatic termination instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10670) termination = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10671) warn_code |= ASC_WARN_EEPROM_TERMINATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10675) if (eep_config.termination_lvd == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10676) asc_dvc->cfg->termination = termination; /* auto termination for LVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10678) /* Enable manual control with low off / high off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10679) if (eep_config.termination_lvd == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10680) asc_dvc->cfg->termination = termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10682) /* Enable manual control with low off / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10683) } else if (eep_config.termination_lvd == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10684) asc_dvc->cfg->termination = termination | TERM_LVD_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10686) /* Enable manual control with low on / high on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10687) } else if (eep_config.termination_lvd == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10688) asc_dvc->cfg->termination = termination | TERM_LVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10691) * The EEPROM 'termination_lvd' field contains a bad value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10692) * Use automatic termination instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10694) asc_dvc->cfg->termination = termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10695) warn_code |= ASC_WARN_EEPROM_TERMINATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10699) return warn_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10703) * Initialize the ADV_DVC_VAR structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10704) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10705) * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10707) * For a non-fatal error return a warning code. If there are no warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10708) * then 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10710) static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10712) struct asc_board *board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10713) ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10714) unsigned short warn_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10715) AdvPortAddr iop_base = asc_dvc->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10716) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10717) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10719) asc_dvc->err_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10722) * Save the state of the PCI Configuration Command Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10723) * "Parity Error Response Control" Bit. If the bit is clear (0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10724) * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10725) * DMA parity errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10727) asc_dvc->cfg->control_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10728) pci_read_config_word(pdev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10729) if ((cmd & PCI_COMMAND_PARITY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10730) asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10732) asc_dvc->cfg->chip_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10733) AdvGetChipVersion(iop_base, asc_dvc->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10735) ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10736) (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10737) (ushort)ADV_CHIP_ID_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10739) ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10740) (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10741) (ushort)ADV_CHIP_ID_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10744) * Reset the chip to start and allow register writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10746) if (AdvFindSignature(iop_base) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10747) asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10748) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10749) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10751) * The caller must set 'chip_type' to a valid setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10753) if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10754) asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10755) asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10756) asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10757) return ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10761) * Reset Chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10763) AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10764) ADV_CTRL_REG_CMD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10765) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10766) AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10767) ADV_CTRL_REG_CMD_WR_IO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10769) if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10770) status = AdvInitFrom38C1600EEP(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10771) } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10772) status = AdvInitFrom38C0800EEP(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10773) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10774) status = AdvInitFrom3550EEP(asc_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10776) warn_code |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10779) if (warn_code != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10780) shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10782) if (asc_dvc->err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10783) shost_printk(KERN_ERR, shost, "error code 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10784) asc_dvc->err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10786) return asc_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10788) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10790) static struct scsi_host_template advansys_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10791) .proc_name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10792) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10793) .show_info = advansys_show_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10794) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10795) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10796) .info = advansys_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10797) .queuecommand = advansys_queuecommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10798) .eh_host_reset_handler = advansys_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10799) .bios_param = advansys_biosparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10800) .slave_configure = advansys_slave_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10802) * Because the driver may control an ISA adapter 'unchecked_isa_dma'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10803) * must be set. The flag will be cleared in advansys_board_found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10804) * for non-ISA adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10806) .unchecked_isa_dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10809) static int advansys_wide_init_chip(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10811) struct asc_board *board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10812) struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10813) size_t sgblk_pool_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10814) int warn_code, err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10817) * Allocate buffer carrier structures. The total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10818) * is about 8 KB, so allocate all at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10820) adv_dvc->carrier = dma_alloc_coherent(board->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10821) ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10822) ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10824) if (!adv_dvc->carrier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10825) goto kmalloc_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10828) * Allocate up to 'max_host_qng' request structures for the Wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10829) * board. The total size is about 16 KB, so allocate all at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10830) * If the allocation fails decrement and try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10832) board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10833) if (board->adv_reqp_size & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10834) ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10835) board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10837) board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10838) &board->adv_reqp_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10840) if (!board->adv_reqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10841) goto kmalloc_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10843) ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10844) adv_dvc->max_host_qng, board->adv_reqp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10847) * Allocate up to ADV_TOT_SG_BLOCK request structures for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10848) * the Wide board. Each structure is about 136 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10850) sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10851) board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10852) sgblk_pool_size, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10854) ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10855) sizeof(adv_sgblk_t), sgblk_pool_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10857) if (!board->adv_sgblk_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10858) goto kmalloc_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10860) if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10861) ASC_DBG(2, "AdvInitAsc3550Driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10862) warn_code = AdvInitAsc3550Driver(adv_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10863) } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10864) ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10865) warn_code = AdvInitAsc38C0800Driver(adv_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10866) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10867) ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10868) warn_code = AdvInitAsc38C1600Driver(adv_dvc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10870) err_code = adv_dvc->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10872) if (warn_code || err_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10873) shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10874) "0x%x\n", warn_code, err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10877) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10879) kmalloc_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10880) shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10881) err_code = ADV_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10882) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10883) return err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10886) static void advansys_wide_free_mem(struct asc_board *board)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10888) struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10890) if (adv_dvc->carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10891) dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10892) adv_dvc->carrier, adv_dvc->carrier_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10893) adv_dvc->carrier = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10895) if (board->adv_reqp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10896) dma_free_coherent(board->dev, board->adv_reqp_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10897) board->adv_reqp, board->adv_reqp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10898) board->adv_reqp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10900) if (board->adv_sgblk_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10901) dma_pool_destroy(board->adv_sgblk_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10902) board->adv_sgblk_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10906) static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10907) int bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10909) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10910) struct asc_board *boardp = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10911) ASC_DVC_VAR *asc_dvc_varp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10912) ADV_DVC_VAR *adv_dvc_varp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10913) int share_irq, warn_code, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10915) pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10917) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10918) ASC_DBG(1, "narrow board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10919) asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10920) asc_dvc_varp->bus_type = bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10921) asc_dvc_varp->drv_ptr = boardp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10922) asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10923) asc_dvc_varp->iop_base = iop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10924) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10925) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10926) adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10927) adv_dvc_varp->drv_ptr = boardp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10928) adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10929) if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10930) ASC_DBG(1, "wide board ASC-3550\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10931) adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10932) } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10933) ASC_DBG(1, "wide board ASC-38C0800\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10934) adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10935) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10936) ASC_DBG(1, "wide board ASC-38C1600\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10937) adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10940) boardp->asc_n_io_port = pci_resource_len(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10941) boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10942) if (!boardp->ioremap_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10943) shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10944) "returned NULL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10945) (long)pci_resource_start(pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10946) boardp->asc_n_io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10947) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10948) goto err_shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10950) adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10951) ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10954) * Even though it isn't used to access wide boards, other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10955) * than for the debug line below, save I/O Port address so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10956) * that it can be reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10958) boardp->ioport = iop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10960) ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10961) (ushort)inp(iop + 1), (ushort)inpw(iop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10962) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10965) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10967) * Set the board bus type and PCI IRQ before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10968) * calling AscInitGetConfig().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10970) switch (asc_dvc_varp->bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10971) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10972) case ASC_IS_ISA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10973) shost->unchecked_isa_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10974) share_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10976) case ASC_IS_VL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10977) shost->unchecked_isa_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10978) share_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10980) case ASC_IS_EISA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10981) shost->unchecked_isa_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10982) share_irq = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10984) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10985) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10986) case ASC_IS_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10987) shost->unchecked_isa_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10988) share_irq = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10990) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10991) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10992) shost_printk(KERN_ERR, shost, "unknown adapter type: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10993) "%d\n", asc_dvc_varp->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10994) shost->unchecked_isa_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10995) share_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11000) * NOTE: AscInitGetConfig() may change the board's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11001) * bus_type value. The bus_type value should no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11002) * longer be used. If the bus_type field must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11003) * referenced only use the bit-wise AND operator "&".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11005) ASC_DBG(2, "AscInitGetConfig()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11006) ret = AscInitGetConfig(shost) ? -ENODEV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11007) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11008) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11010) * For Wide boards set PCI information before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11011) * AdvInitGetConfig().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11013) shost->unchecked_isa_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11014) share_irq = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11015) ASC_DBG(2, "AdvInitGetConfig()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11017) ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11018) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11019) share_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11020) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11021) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11024) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11025) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11028) * Save the EEPROM configuration so that it can be displayed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11029) * from /proc/scsi/advansys/[0...].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11031) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11033) ASCEEP_CONFIG *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11036) * Set the adapter's target id bit in the 'init_tidmask' field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11038) boardp->init_tidmask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11039) ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11042) * Save EEPROM settings for the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11044) ep = &boardp->eep_config.asc_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11046) ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11047) ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11048) ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11049) ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11050) ep->start_motor = asc_dvc_varp->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11051) ep->cntl = asc_dvc_varp->dvc_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11052) ep->no_scam = asc_dvc_varp->no_scam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11053) ep->max_total_qng = asc_dvc_varp->max_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11054) ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11055) /* 'max_tag_qng' is set to the same value for every device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11056) ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11057) ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11058) ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11059) ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11060) ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11061) ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11062) ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11065) * Modify board configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11067) ASC_DBG(2, "AscInitSetConfig()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11068) ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11070) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11071) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11072) ADVEEP_3550_CONFIG *ep_3550;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11073) ADVEEP_38C0800_CONFIG *ep_38C0800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11074) ADVEEP_38C1600_CONFIG *ep_38C1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11077) * Save Wide EEP Configuration Information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11079) if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11080) ep_3550 = &boardp->eep_config.adv_3550_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11082) ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11083) ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11084) ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11085) ep_3550->termination = adv_dvc_varp->cfg->termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11086) ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11087) ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11088) ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11089) ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11090) ep_3550->ultra_able = adv_dvc_varp->ultra_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11091) ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11092) ep_3550->start_motor = adv_dvc_varp->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11093) ep_3550->scsi_reset_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11094) adv_dvc_varp->scsi_reset_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11095) ep_3550->serial_number_word1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11096) adv_dvc_varp->cfg->serial1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11097) ep_3550->serial_number_word2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11098) adv_dvc_varp->cfg->serial2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11099) ep_3550->serial_number_word3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11100) adv_dvc_varp->cfg->serial3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11101) } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11102) ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11104) ep_38C0800->adapter_scsi_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11105) adv_dvc_varp->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11106) ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11107) ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11108) ep_38C0800->termination_lvd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11109) adv_dvc_varp->cfg->termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11110) ep_38C0800->disc_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11111) adv_dvc_varp->cfg->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11112) ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11113) ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11114) ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11115) ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11116) ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11117) ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11118) ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11119) ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11120) ep_38C0800->start_motor = adv_dvc_varp->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11121) ep_38C0800->scsi_reset_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11122) adv_dvc_varp->scsi_reset_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11123) ep_38C0800->serial_number_word1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11124) adv_dvc_varp->cfg->serial1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11125) ep_38C0800->serial_number_word2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11126) adv_dvc_varp->cfg->serial2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11127) ep_38C0800->serial_number_word3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11128) adv_dvc_varp->cfg->serial3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11130) ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11132) ep_38C1600->adapter_scsi_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11133) adv_dvc_varp->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11134) ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11135) ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11136) ep_38C1600->termination_lvd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11137) adv_dvc_varp->cfg->termination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11138) ep_38C1600->disc_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11139) adv_dvc_varp->cfg->disc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11140) ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11141) ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11142) ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11143) ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11144) ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11145) ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11146) ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11147) ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11148) ep_38C1600->start_motor = adv_dvc_varp->start_motor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11149) ep_38C1600->scsi_reset_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11150) adv_dvc_varp->scsi_reset_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11151) ep_38C1600->serial_number_word1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11152) adv_dvc_varp->cfg->serial1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11153) ep_38C1600->serial_number_word2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11154) adv_dvc_varp->cfg->serial2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11155) ep_38C1600->serial_number_word3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11156) adv_dvc_varp->cfg->serial3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11160) * Set the adapter's target id bit in the 'init_tidmask' field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11162) boardp->init_tidmask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11163) ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11167) * Channels are numbered beginning with 0. For AdvanSys one host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11168) * structure supports one channel. Multi-channel boards have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11169) * separate host structure for each channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11171) shost->max_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11172) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11173) shost->max_id = ASC_MAX_TID + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11174) shost->max_lun = ASC_MAX_LUN + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11175) shost->max_cmd_len = ASC_MAX_CDB_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11177) shost->io_port = asc_dvc_varp->iop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11178) boardp->asc_n_io_port = ASC_IOADR_GAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11179) shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11181) /* Set maximum number of queues the adapter can handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11182) shost->can_queue = asc_dvc_varp->max_total_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11184) shost->max_id = ADV_MAX_TID + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11185) shost->max_lun = ADV_MAX_LUN + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11186) shost->max_cmd_len = ADV_MAX_CDB_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11189) * Save the I/O Port address and length even though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11190) * I/O ports are not used to access Wide boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11191) * Instead the Wide boards are accessed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11192) * PCI Memory Mapped I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11194) shost->io_port = iop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11196) shost->this_id = adv_dvc_varp->chip_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11198) /* Set maximum number of queues the adapter can handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11199) shost->can_queue = adv_dvc_varp->max_host_qng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11203) * Set the maximum number of scatter-gather elements the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11204) * adapter can handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11206) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11208) * Allow two commands with 'sg_tablesize' scatter-gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11209) * elements to be executed simultaneously. This value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11210) * the theoretical hardware limit. It may be decreased
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11211) * below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11213) shost->sg_tablesize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11214) (((asc_dvc_varp->max_total_qng - 2) / 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11215) ASC_SG_LIST_PER_Q) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11217) shost->sg_tablesize = ADV_MAX_SG_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11221) * The value of 'sg_tablesize' can not exceed the SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11222) * mid-level driver definition of SG_ALL. SG_ALL also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11223) * must not be exceeded, because it is used to define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11224) * size of the scatter-gather table in 'struct asc_sg_head'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11226) if (shost->sg_tablesize > SG_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11227) shost->sg_tablesize = SG_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11230) ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11232) /* BIOS start address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11233) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11234) shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11235) asc_dvc_varp->bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11238) * Fill-in BIOS board variables. The Wide BIOS saves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11239) * information in LRAM that is used by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11241) AdvReadWordLram(adv_dvc_varp->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11242) BIOS_SIGNATURE, boardp->bios_signature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11243) AdvReadWordLram(adv_dvc_varp->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11244) BIOS_VERSION, boardp->bios_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11245) AdvReadWordLram(adv_dvc_varp->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11246) BIOS_CODESEG, boardp->bios_codeseg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11247) AdvReadWordLram(adv_dvc_varp->iop_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11248) BIOS_CODELEN, boardp->bios_codelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11250) ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11251) boardp->bios_signature, boardp->bios_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11253) ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11254) boardp->bios_codeseg, boardp->bios_codelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11257) * If the BIOS saved a valid signature, then fill in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11258) * the BIOS code segment base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11260) if (boardp->bios_signature == 0x55AA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11262) * Convert x86 realmode code segment to a linear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11263) * address by shifting left 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11265) shost->base = ((ulong)boardp->bios_codeseg << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11266) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11267) shost->base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11272) * Register Board Resources - I/O Port, DMA, IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11275) /* Register DMA Channel for Narrow boards. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11276) shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11277) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11278) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11279) /* Register DMA channel for ISA bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11280) if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11281) shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11282) ret = request_dma(shost->dma_channel, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11283) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11284) shost_printk(KERN_ERR, shost, "request_dma() "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11285) "%d failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11286) shost->dma_channel, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11287) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11289) AscEnableIsaDma(shost->dma_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11292) #endif /* CONFIG_ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11294) /* Register IRQ Number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11295) ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11297) ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11298) DRV_NAME, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11300) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11301) if (ret == -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11302) shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11303) "already in use\n", boardp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11304) } else if (ret == -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11305) shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11306) "not valid\n", boardp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11308) shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11309) "failed with %d\n", boardp->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11311) goto err_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11315) * Initialize board RISC chip and enable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11317) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11318) ASC_DBG(2, "AscInitAsc1000Driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11320) asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11321) if (!asc_dvc_varp->overrun_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11322) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11323) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11325) warn_code = AscInitAsc1000Driver(asc_dvc_varp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11327) if (warn_code || asc_dvc_varp->err_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11328) shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11329) "warn 0x%x, error 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11330) asc_dvc_varp->init_state, warn_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11331) asc_dvc_varp->err_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11332) if (!asc_dvc_varp->overrun_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11333) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11334) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11338) if (advansys_wide_init_chip(shost)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11339) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11340) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11344) ASC_DBG_PRT_SCSI_HOST(2, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11346) ret = scsi_add_host(shost, boardp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11347) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11348) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11350) scsi_scan_host(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11353) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11354) if (ASC_NARROW_BOARD(boardp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11355) if (asc_dvc_varp->overrun_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11356) dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11357) ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11358) kfree(asc_dvc_varp->overrun_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11359) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11360) advansys_wide_free_mem(boardp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11361) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11362) free_irq(boardp->irq, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11363) err_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11364) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11365) if (shost->dma_channel != NO_ISA_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11366) free_dma(shost->dma_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11368) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11369) if (boardp->ioremap_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11370) iounmap(boardp->ioremap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11371) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11372) err_shost:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11378) * advansys_release()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11380) * Release resources allocated for a single AdvanSys adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11382) static int advansys_release(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11384) struct asc_board *board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11385) ASC_DBG(1, "begin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11386) scsi_remove_host(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11387) free_irq(board->irq, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11388) #ifdef CONFIG_ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11389) if (shost->dma_channel != NO_ISA_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11390) ASC_DBG(1, "free_dma()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11391) free_dma(shost->dma_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11393) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11394) if (ASC_NARROW_BOARD(board)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11395) dma_unmap_single(board->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11396) board->dvc_var.asc_dvc_var.overrun_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11397) ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11398) kfree(board->dvc_var.asc_dvc_var.overrun_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11399) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11400) iounmap(board->ioremap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11401) advansys_wide_free_mem(board);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11403) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11404) ASC_DBG(1, "end\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11408) #define ASC_IOADR_TABLE_MAX_IX 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11410) static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11411) 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11412) 0x0210, 0x0230, 0x0250, 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11416) * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11417) * 00: 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11418) * 01: 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11419) * 10: 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11420) * 11: 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11422) static unsigned int advansys_isa_irq_no(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11424) unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11425) unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11426) if (chip_irq == 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11427) chip_irq = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11428) return chip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11431) static int advansys_isa_probe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11433) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11434) PortAddr iop_base = _asc_def_iop_base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11435) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11436) struct asc_board *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11438) if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11439) ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11440) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11442) ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11443) if (!AscFindSignature(iop_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11444) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11445) if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11446) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11448) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11449) shost = scsi_host_alloc(&advansys_template, sizeof(*board));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11450) if (!shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11451) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11453) board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11454) board->irq = advansys_isa_irq_no(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11455) board->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11456) board->shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11458) err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11459) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11460) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11462) dev_set_drvdata(dev, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11465) free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11466) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11467) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11468) release_region(iop_base, ASC_IOADR_GAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11469) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11472) static int advansys_isa_remove(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11474) int ioport = _asc_def_iop_base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11475) advansys_release(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11476) release_region(ioport, ASC_IOADR_GAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11480) static struct isa_driver advansys_isa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11481) .probe = advansys_isa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11482) .remove = advansys_isa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11483) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11484) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11485) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11490) * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11491) * 000: invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11492) * 001: 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11493) * 010: 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11494) * 011: 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11495) * 100: invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11496) * 101: 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11497) * 110: 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11498) * 111: invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11500) static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11502) unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11503) unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11504) if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11506) return chip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11509) static int advansys_vlb_probe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11511) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11512) PortAddr iop_base = _asc_def_iop_base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11513) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11514) struct asc_board *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11516) if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11517) ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11518) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11520) ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11521) if (!AscFindSignature(iop_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11522) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11524) * I don't think this condition can actually happen, but the old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11525) * driver did it, and the chances of finding a VLB setup in 2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11526) * to do testing with is slight to none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11528) if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11529) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11531) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11532) shost = scsi_host_alloc(&advansys_template, sizeof(*board));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11533) if (!shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11534) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11536) board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11537) board->irq = advansys_vlb_irq_no(iop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11538) board->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11539) board->shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11541) err = advansys_board_found(shost, iop_base, ASC_IS_VL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11542) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11543) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11545) dev_set_drvdata(dev, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11548) free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11549) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11550) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11551) release_region(iop_base, ASC_IOADR_GAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11552) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11555) static struct isa_driver advansys_vlb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11556) .probe = advansys_vlb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11557) .remove = advansys_isa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11558) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11559) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11560) .name = "advansys_vlb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11564) static struct eisa_device_id advansys_eisa_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11565) { "ABP7401" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11566) { "ABP7501" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11567) { "" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11570) MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11573) * EISA is a little more tricky than PCI; each EISA device may have two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11574) * channels, and this driver is written to make each channel its own Scsi_Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11576) struct eisa_scsi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11577) struct Scsi_Host *host[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11581) * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11582) * 000: 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11583) * 001: 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11584) * 010: 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11585) * 011: invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11586) * 100: 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11587) * 101: 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11588) * 110: invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11589) * 111: invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11591) static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11593) unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11594) unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11595) if ((chip_irq == 13) || (chip_irq > 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11597) return chip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11600) static int advansys_eisa_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11602) int i, ioport, irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11603) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11604) struct eisa_device *edev = to_eisa_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11605) struct eisa_scsi_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11607) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11608) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11609) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11610) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11611) ioport = edev->base_addr + 0xc30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11613) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11614) for (i = 0; i < 2; i++, ioport += 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11615) struct asc_board *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11616) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11617) if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11618) printk(KERN_WARNING "Region %x-%x busy\n", ioport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11619) ioport + ASC_IOADR_GAP - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11620) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11622) if (!AscFindSignature(ioport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11623) release_region(ioport, ASC_IOADR_GAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11624) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11628) * I don't know why we need to do this for EISA chips, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11629) * not for any others. It looks to be equivalent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11630) * AscGetChipCfgMsw, but I may have overlooked something,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11631) * so I'm not converting it until I get an EISA board to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11632) * test with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11634) inw(ioport + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11636) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11637) irq = advansys_eisa_irq_no(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11639) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11640) shost = scsi_host_alloc(&advansys_template, sizeof(*board));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11641) if (!shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11642) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11644) board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11645) board->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11646) board->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11647) board->shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11649) err = advansys_board_found(shost, ioport, ASC_IS_EISA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11650) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11651) data->host[i] = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11652) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11655) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11656) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11657) release_region(ioport, ASC_IOADR_GAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11661) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11662) goto free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11663) dev_set_drvdata(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11666) free_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11667) kfree(data->host[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11668) kfree(data->host[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11669) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11670) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11671) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11674) static int advansys_eisa_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11676) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11677) struct eisa_scsi_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11679) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11680) int ioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11681) struct Scsi_Host *shost = data->host[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11682) if (!shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11683) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11684) ioport = shost->io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11685) advansys_release(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11686) release_region(ioport, ASC_IOADR_GAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11689) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11693) static struct eisa_driver advansys_eisa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11694) .id_table = advansys_eisa_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11695) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11696) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11697) .probe = advansys_eisa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11698) .remove = advansys_eisa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11702) /* PCI Devices supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11703) static struct pci_device_id advansys_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11704) {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11705) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11706) {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11707) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11708) {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11709) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11710) {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11711) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11712) {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11713) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11714) {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11715) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11716) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11719) MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11721) static void advansys_set_latency(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11723) if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11724) (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11725) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11727) u8 latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11728) pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11729) if (latency < 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11730) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11734) static int advansys_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11735) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11737) int err, ioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11738) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11739) struct asc_board *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11741) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11742) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11743) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11744) err = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11745) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11746) goto disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11747) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11748) advansys_set_latency(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11750) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11751) if (pci_resource_len(pdev, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11752) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11754) ioport = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11756) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11757) shost = scsi_host_alloc(&advansys_template, sizeof(*board));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11758) if (!shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11759) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11761) board = shost_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11762) board->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11763) board->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11764) board->shost = shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11766) if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11767) pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11768) pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11769) board->flags |= ASC_IS_WIDE_BOARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11772) err = advansys_board_found(shost, ioport, ASC_IS_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11773) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11774) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11776) pci_set_drvdata(pdev, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11779) free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11780) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11781) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11782) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11783) disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11784) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11785) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11786) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11789) static void advansys_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11791) advansys_release(pci_get_drvdata(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11792) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11793) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11796) static struct pci_driver advansys_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11797) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11798) .id_table = advansys_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11799) .probe = advansys_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11800) .remove = advansys_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11803) static int __init advansys_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11805) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11807) error = isa_register_driver(&advansys_isa_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11808) ASC_IOADR_TABLE_MAX_IX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11809) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11810) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11812) error = isa_register_driver(&advansys_vlb_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11813) ASC_IOADR_TABLE_MAX_IX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11814) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11815) goto unregister_isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11817) error = eisa_driver_register(&advansys_eisa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11818) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11819) goto unregister_vlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11821) error = pci_register_driver(&advansys_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11822) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11823) goto unregister_eisa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11827) unregister_eisa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11828) eisa_driver_unregister(&advansys_eisa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11829) unregister_vlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11830) isa_unregister_driver(&advansys_vlb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11831) unregister_isa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11832) isa_unregister_driver(&advansys_isa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11833) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11834) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11837) static void __exit advansys_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11839) pci_unregister_driver(&advansys_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11840) eisa_driver_unregister(&advansys_eisa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11841) isa_unregister_driver(&advansys_vlb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11842) isa_unregister_driver(&advansys_isa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11845) module_init(advansys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11846) module_exit(advansys_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11848) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11849) MODULE_FIRMWARE("advansys/mcode.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11850) MODULE_FIRMWARE("advansys/3550.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11851) MODULE_FIRMWARE("advansys/38C0800.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11852) MODULE_FIRMWARE("advansys/38C1600.bin");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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