^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Adaptec AAC series RAID controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (c) Copyright 2001 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the old aacraid driver that is..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Adaptec aacraid device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2000-2010 Adaptec, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Module Name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * comminit.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Abstract: This supports the initialization of the host adapter commuication interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This is a platform dependent module for the pci cyclone board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "aacraid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct aac_common aac_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .irq_mod = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline int aac_is_msix_mode(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (aac_is_src(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) status = src_readl(dev, MUnit.OMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return (status & AAC_INT_MODE_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline void aac_change_to_intx(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) aac_src_access_devreg(dev, AAC_DISABLE_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) aac_src_access_devreg(dev, AAC_ENABLE_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int aac_alloc_comm(struct aac_dev *dev, void **commaddr, unsigned long commsize, unsigned long commalign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long size, align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const unsigned long fibsize = dev->max_fib_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const unsigned long printfbufsiz = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long host_rrq_size, aac_init_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) union aac_init *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long aac_max_hostphysmempages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) !dev->sa_firmware)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) host_rrq_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) aac_init_size = sizeof(union aac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } else if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev->sa_firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) host_rrq_size = (dev->scsi_host_ptr->can_queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) + AAC_NUM_MGT_FIB) * sizeof(u32) * AAC_MAX_MSIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) aac_init_size = sizeof(union aac_init) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) host_rrq_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) aac_init_size = sizeof(union aac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) size = fibsize + aac_init_size + commsize + commalign +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) printfbufsiz + host_rrq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) base = dma_alloc_coherent(&dev->pdev->dev, size, &phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) printk(KERN_ERR "aacraid: unable to create mapping.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev->comm_addr = (void *)base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev->comm_phys = phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev->comm_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev->host_rrq = (u32 *)(base + fibsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev->host_rrq_pa = phys + fibsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) memset(dev->host_rrq, 0, host_rrq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev->init = (union aac_init *)(base + fibsize + host_rrq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev->init_pa = phys + fibsize + host_rrq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) init = dev->init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) init->r8.init_struct_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) init->r8.init_flags = cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) INITFLAGS_DRIVER_USES_UTC_TIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) INITFLAGS_DRIVER_SUPPORTS_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) init->r8.init_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cpu_to_le32(INITFLAGS_DRIVER_SUPPORTS_HBA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) init->r8.rr_queue_count = cpu_to_le32(dev->max_msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) init->r8.max_io_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cpu_to_le32(dev->scsi_host_ptr->max_sectors << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) init->r8.max_num_aif = init->r8.reserved1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) init->r8.reserved2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < dev->max_msix; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) addr = (u64)dev->host_rrq_pa + dev->vector_cap * i *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) init->r8.rrq[i].host_addr_high = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) init->r8.rrq[i].host_addr_low = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) lower_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) init->r8.rrq[i].msix_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) init->r8.rrq[i].element_count = cpu_to_le16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (u16)dev->vector_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) init->r8.rrq[i].comp_thresh =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) init->r8.rrq[i].unused = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_warn("aacraid: Comm Interface type3 enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) init->r7.init_struct_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (dev->max_fib_size != sizeof(struct hw_fib))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) init->r7.init_struct_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) init->r7.no_of_msix_vectors = cpu_to_le32(SA_MINIPORT_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) init->r7.fsrev = cpu_to_le32(dev->fsrev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Adapter Fibs are the first thing allocated so that they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * start page aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev->aif_base_va = (struct hw_fib *)base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) init->r7.adapter_fibs_virtual_address = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) init->r7.adapter_fibs_physical_address = cpu_to_le32((u32)phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) init->r7.adapter_fibs_size = cpu_to_le32(fibsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) init->r7.adapter_fib_align = cpu_to_le32(sizeof(struct hw_fib));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * number of 4k pages of host physical memory. The aacraid fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * needs this number to be less than 4gb worth of pages. New
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * firmware doesn't have any issues with the mapping system, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * older Firmware did, and had *troubles* dealing with the math
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * overloading past 32 bits, thus we must limit this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) aac_max_hostphysmempages =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dma_get_required_mask(&dev->pdev->dev) >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (aac_max_hostphysmempages < AAC_MAX_HOSTPHYSMEMPAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) init->r7.host_phys_mem_pages =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cpu_to_le32(aac_max_hostphysmempages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) init->r7.host_phys_mem_pages =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cpu_to_le32(AAC_MAX_HOSTPHYSMEMPAGES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) init->r7.init_flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cpu_to_le32(INITFLAGS_DRIVER_USES_UTC_TIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) INITFLAGS_DRIVER_SUPPORTS_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) init->r7.max_io_commands =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cpu_to_le32(dev->scsi_host_ptr->can_queue +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) AAC_NUM_MGT_FIB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) init->r7.max_io_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cpu_to_le32(dev->scsi_host_ptr->max_sectors << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) init->r7.max_fib_size = cpu_to_le32(dev->max_fib_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) init->r7.max_num_aif = cpu_to_le32(dev->max_num_aif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (dev->comm_interface == AAC_COMM_MESSAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) init->r7.init_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_warn("aacraid: Comm Interface enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) init->r7.init_struct_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) init->r7.init_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) INITFLAGS_NEW_COMM_TYPE1_SUPPORTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) INITFLAGS_FAST_JBOD_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) init->r7.host_rrq_addr_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cpu_to_le32(upper_32_bits(dev->host_rrq_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) init->r7.host_rrq_addr_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cpu_to_le32(lower_32_bits(dev->host_rrq_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pr_warn("aacraid: Comm Interface type1 enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) init->r7.init_struct_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cpu_to_le32(ADAPTER_INIT_STRUCT_REVISION_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) init->r7.init_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cpu_to_le32(INITFLAGS_NEW_COMM_SUPPORTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) INITFLAGS_NEW_COMM_TYPE2_SUPPORTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) INITFLAGS_FAST_JBOD_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) init->r7.host_rrq_addr_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cpu_to_le32(upper_32_bits(dev->host_rrq_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) init->r7.host_rrq_addr_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cpu_to_le32(lower_32_bits(dev->host_rrq_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) init->r7.no_of_msix_vectors =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cpu_to_le32(dev->max_msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* must be the COMM_PREFERRED_SETTINGS values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_warn("aacraid: Comm Interface type2 enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Increment the base address by the amount already used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) base = base + fibsize + host_rrq_size + aac_init_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) phys = (dma_addr_t)((ulong)phys + fibsize + host_rrq_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) aac_init_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Align the beginning of Headers to commalign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) align = (commalign - ((uintptr_t)(base) & (commalign - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) base = base + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) phys = phys + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Fill in addresses of the Comm Area Headers and Queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *commaddr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) init->r7.comm_header_address = cpu_to_le32((u32)phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Increment the base address by the size of the CommArea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) base = base + commsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) phys = phys + commsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Place the Printf buffer area after the Fast I/O comm area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev->printfbuf = (void *)base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) init->r7.printfbuf = cpu_to_le32(phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) init->r7.printfbufsiz = cpu_to_le32(printfbufsiz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) memset(base, 0, printfbufsiz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void aac_queue_init(struct aac_dev * dev, struct aac_queue * q, u32 *mem, int qsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) atomic_set(&q->numpending, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) q->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) init_waitqueue_head(&q->cmdready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) INIT_LIST_HEAD(&q->cmdq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) init_waitqueue_head(&q->qfull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_lock_init(&q->lockdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) q->lock = &q->lockdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) q->headers.producer = (__le32 *)mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) q->headers.consumer = (__le32 *)(mem+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *(q->headers.producer) = cpu_to_le32(qsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *(q->headers.consumer) = cpu_to_le32(qsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) q->entries = qsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static bool wait_for_io_iter(struct scsi_cmnd *cmd, void *data, bool rsvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int *active = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (cmd->SCp.phase == AAC_OWNER_FIRMWARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *active = *active + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void aac_wait_for_io_completion(struct aac_dev *aac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int i = 0, active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 60; i; --i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) scsi_host_busy_iter(aac->scsi_host_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) wait_for_io_iter, &active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * We can exit If all the commands are complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (active == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_info(&aac->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "Wait for %d commands to complete\n", active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ssleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(&aac->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "%d outstanding commands during shutdown\n", active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * aac_send_shutdown - shutdown an adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @dev: Adapter to shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * This routine will send a VM_CloseAll (shutdown) request to the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int aac_send_shutdown(struct aac_dev * dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct fib * fibctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct aac_close *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (aac_adapter_check_health(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!dev->adapter_shutdown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mutex_lock(&dev->ioctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev->adapter_shutdown = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mutex_unlock(&dev->ioctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) aac_wait_for_io_completion(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fibctx = aac_fib_alloc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!fibctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) aac_fib_init(fibctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cmd = (struct aac_close *) fib_data(fibctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cmd->command = cpu_to_le32(VM_CloseAll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cmd->cid = cpu_to_le32(0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) status = aac_fib_send(ContainerCommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) fibctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) sizeof(struct aac_close),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FsaNormal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) -2 /* Timeout silently */, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (status >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) aac_fib_complete(fibctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* FIB should be freed only after getting the response from the F/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (status != -ERESTARTSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) aac_fib_free(fibctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (aac_is_src(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) aac_set_intx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * aac_comm_init - Initialise FSA data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @dev: Adapter to initialise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Initializes the data structures that are required for the FSA commuication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * interface to operate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * 1 - if we were able to init the commuication interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * 0 - If there were errors initing. This is a fatal error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int aac_comm_init(struct aac_dev * dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned long hdrsize = (sizeof(u32) * NUMBER_OF_COMM_QUEUES) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned long queuesize = sizeof(struct aac_entry) * TOTAL_QUEUE_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 *headers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct aac_entry * queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct aac_queue_block * comm = dev->queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Now allocate and initialize the zone structures used as our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * pool of FIB context records. The size of the zone is based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * on the system memory size. We also initialize the mutex used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * to protect the zone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) spin_lock_init(&dev->fib_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Allocate the physically contiguous space for the commuication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * queue headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) size = hdrsize + queuesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!aac_alloc_comm(dev, (void * *)&headers, size, QUEUE_ALIGNMENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) queues = (struct aac_entry *)(((ulong)headers) + hdrsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Adapter to Host normal priority Command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) comm->queue[HostNormCmdQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) aac_queue_init(dev, &comm->queue[HostNormCmdQueue], headers, HOST_NORM_CMD_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) queues += HOST_NORM_CMD_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) headers += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Adapter to Host high priority command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) comm->queue[HostHighCmdQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) aac_queue_init(dev, &comm->queue[HostHighCmdQueue], headers, HOST_HIGH_CMD_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) queues += HOST_HIGH_CMD_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) headers +=2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Host to adapter normal priority command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) comm->queue[AdapNormCmdQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) aac_queue_init(dev, &comm->queue[AdapNormCmdQueue], headers, ADAP_NORM_CMD_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) queues += ADAP_NORM_CMD_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) headers += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* host to adapter high priority command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) comm->queue[AdapHighCmdQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) aac_queue_init(dev, &comm->queue[AdapHighCmdQueue], headers, ADAP_HIGH_CMD_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) queues += ADAP_HIGH_CMD_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) headers += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* adapter to host normal priority response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) comm->queue[HostNormRespQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) aac_queue_init(dev, &comm->queue[HostNormRespQueue], headers, HOST_NORM_RESP_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) queues += HOST_NORM_RESP_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) headers += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* adapter to host high priority response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) comm->queue[HostHighRespQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) aac_queue_init(dev, &comm->queue[HostHighRespQueue], headers, HOST_HIGH_RESP_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) queues += HOST_HIGH_RESP_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) headers += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* host to adapter normal priority response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) comm->queue[AdapNormRespQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) aac_queue_init(dev, &comm->queue[AdapNormRespQueue], headers, ADAP_NORM_RESP_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) queues += ADAP_NORM_RESP_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) headers += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* host to adapter high priority response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) comm->queue[AdapHighRespQueue].base = queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) aac_queue_init(dev, &comm->queue[AdapHighRespQueue], headers, ADAP_HIGH_RESP_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) comm->queue[AdapNormCmdQueue].lock = comm->queue[HostNormRespQueue].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) comm->queue[AdapHighCmdQueue].lock = comm->queue[HostHighRespQueue].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) comm->queue[AdapNormRespQueue].lock = comm->queue[HostNormCmdQueue].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) comm->queue[AdapHighRespQueue].lock = comm->queue[HostHighCmdQueue].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void aac_define_int_mode(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int i, msi_count, min_msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msi_count = i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* max. vectors from GET_COMM_PREFERRED_SETTINGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (dev->max_msix == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev->pdev->device == PMC_DEVICE_S6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev->sync_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev->max_msix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev->vector_cap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev->scsi_host_ptr->can_queue +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) AAC_NUM_MGT_FIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Don't bother allocating more MSI-X vectors than cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msi_count = min(dev->max_msix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) (unsigned int)num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev->max_msix = msi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (msi_count > AAC_MAX_MSIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) msi_count = AAC_MAX_MSIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (msi_count > 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) min_msix = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) i = pci_alloc_irq_vectors(dev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) min_msix, msi_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (i > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev->msi_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) msi_count = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev->msi_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "MSIX not supported!! Will try INTX 0x%x.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!dev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev->max_msix = msi_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (dev->max_msix > msi_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev->max_msix = msi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3 && dev->sa_firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev->vector_cap = dev->scsi_host_ptr->can_queue +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) AAC_NUM_MGT_FIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev->vector_cap = (dev->scsi_host_ptr->can_queue +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) AAC_NUM_MGT_FIB) / msi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct aac_dev *aac_init_adapter(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 status[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct Scsi_Host * host = dev->scsi_host_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) extern int aac_sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Check the preferred comm settings, defaults from template.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev->management_fib_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) spin_lock_init(&dev->manage_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_lock_init(&dev->sync_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_lock_init(&dev->iq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev->max_fib_size = sizeof(struct hw_fib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev->sg_tablesize = host->sg_tablesize = (dev->max_fib_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) - sizeof(struct aac_fibhdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) - sizeof(struct aac_write) + sizeof(struct sgentry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) / sizeof(struct sgentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev->comm_interface = AAC_COMM_PRODUCER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev->raw_io_interface = dev->raw_io_64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Enable INTX mode, if not done already Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (aac_is_msix_mode(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) aac_change_to_intx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_info(&dev->pdev->dev, "Changed firmware to INTX mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if ((!aac_adapter_sync_cmd(dev, GET_ADAPTER_PROPERTIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) status+0, status+1, status+2, status+3, status+4)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (status[0] == 0x00000001)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev->doorbell_mask = status[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (status[1] & AAC_OPT_NEW_COMM_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev->raw_io_64 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev->sync_mode = aac_sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (dev->a_ops.adapter_comm &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) (status[1] & AAC_OPT_NEW_COMM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev->comm_interface = AAC_COMM_MESSAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev->raw_io_interface = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if ((status[1] & AAC_OPT_NEW_COMM_TYPE1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* driver supports TYPE1 (Tupelo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev->comm_interface = AAC_COMM_MESSAGE_TYPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } else if (status[1] & AAC_OPT_NEW_COMM_TYPE2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* driver supports TYPE2 (Denali, Yosemite) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev->comm_interface = AAC_COMM_MESSAGE_TYPE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } else if (status[1] & AAC_OPT_NEW_COMM_TYPE3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* driver supports TYPE3 (Yosemite, Thor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev->comm_interface = AAC_COMM_MESSAGE_TYPE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else if (status[1] & AAC_OPT_NEW_COMM_TYPE4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* not supported TYPE - switch to sync. mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev->comm_interface = AAC_COMM_MESSAGE_TYPE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev->sync_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if ((status[1] & le32_to_cpu(AAC_OPT_EXTENDED)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (status[4] & le32_to_cpu(AAC_EXTOPT_SA_FIRMWARE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev->sa_firmware = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev->sa_firmware = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (status[4] & le32_to_cpu(AAC_EXTOPT_SOFT_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev->soft_reset_support = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev->soft_reset_support = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if ((dev->comm_interface == AAC_COMM_MESSAGE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) (status[2] > dev->base_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) aac_adapter_ioremap(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev->base_size = status[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (aac_adapter_ioremap(dev, status[2])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* remap failed, go back ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev->comm_interface = AAC_COMM_PRODUCER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (aac_adapter_ioremap(dev, AAC_MIN_FOOTPRINT_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "aacraid: unable to map adapter.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev->max_msix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev->msi_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev->adapter_shutdown = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if ((!aac_adapter_sync_cmd(dev, GET_COMM_PREFERRED_SETTINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) status+0, status+1, status+2, status+3, status+4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) && (status[0] == 0x00000001)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * status[1] >> 16 maximum command size in KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * status[1] & 0xFFFF maximum FIB size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * status[2] >> 16 maximum SG elements to driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * status[2] & 0xFFFF maximum SG elements from driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * status[3] & 0xFFFF maximum number FIBs outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) host->max_sectors = (status[1] >> 16) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Multiple of 32 for PMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev->max_fib_size = status[1] & 0xFFE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) host->sg_tablesize = status[2] >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev->sg_tablesize = status[2] & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (aac_is_src(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (host->can_queue > (status[3] >> 16) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) AAC_NUM_MGT_FIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) host->can_queue = (status[3] >> 16) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) AAC_NUM_MGT_FIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else if (host->can_queue > (status[3] & 0xFFFF) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) AAC_NUM_MGT_FIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) host->can_queue = (status[3] & 0xFFFF) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) AAC_NUM_MGT_FIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev->max_num_aif = status[4] & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (numacb > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (numacb < host->can_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) host->can_queue = numacb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pr_warn("numacb=%d ignored\n", numacb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (aac_is_src(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) aac_define_int_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Ok now init the communication subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev->queues = kzalloc(sizeof(struct aac_queue_block), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (dev->queues == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) printk(KERN_ERR "Error could not allocate comm region.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (aac_comm_init(dev)<0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) kfree(dev->queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Initialize the list of fibs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (aac_fib_setup(dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) kfree(dev->queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) INIT_LIST_HEAD(&dev->fib_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) INIT_LIST_HEAD(&dev->sync_fib_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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