^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Adaptec AAC series RAID controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the old aacraid driver that is..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Adaptec aacraid device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2000-2010 Adaptec, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Module Name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * aacraid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Abstract: Contains all routines for control of the aacraid driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef _AACRAID_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define _AACRAID_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef dprintk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define dprintk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* eg: if (nblank(dprintk(x))) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _nblank(x) #x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define nblank(x) _nblank(x)[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * D E F I N E S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AAC_MAX_MSIX 32 /* vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AAC_PCI_MSI_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AAC_ENABLE_INTERRUPT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) AAC_DISABLE_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) AAC_ENABLE_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) AAC_DISABLE_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) AAC_CLEAR_AIF_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) AAC_CLEAR_SYNC_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) AAC_ENABLE_INTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AAC_INT_MODE_INTX (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AAC_INT_MODE_MSI (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AAC_INT_MODE_AIF (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AAC_INT_MODE_SYNC (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AAC_INT_MODE_MSIX (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AAC_INT_DISABLE_ALL 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Bit definitions in IOA->Host Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PMC_IOA_UNIT_CHECK (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PMC_IOARRIN_LOST (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PMC_HOST_RRQ_VALID (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMC_OPERATIONAL_STATUS (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PMC_IOA_UNIT_CHECK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PMC_IOARRIN_LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PMC_SYSTEM_BUS_MMIO_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PMC_IOA_PROCESSOR_IN_ERROR_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PMC_HOST_RRQ_VALID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PMC_TRANSITION_TO_OPERATIONAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PMC_ALLOW_MSIX_VECTOR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PMC_GLOBAL_INT_BIT2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PMC_GLOBAL_INT_BIT0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifndef AAC_DRIVER_BUILD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define AAC_DRIVER_BUILD 50983
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define AAC_DRIVER_BRANCH "-custom"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAXIMUM_NUM_CONTAINERS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AAC_NUM_MGT_FIB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AAC_MAX_LUN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AAC_MAX_NATIVE_TARGETS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AAC_MAX_BUSES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AAC_MAX_TARGETS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AAC_MAX_NATIVE_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FW_ERROR_BUFFER_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AAC_SA_TIMEOUT 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AAC_ARC_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define get_bus_number(x) (x/AAC_MAX_TARGETS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define get_target_number(x) (x%AAC_MAX_TARGETS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Thor AIF events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SA_AIF_HOTPLUG (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SA_AIF_HARDWARE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SA_AIF_PDEV_CHANGE (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SA_AIF_LDEV_CHANGE (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SA_AIF_BPSTAT_CHANGE (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SA_AIF_BPCFG_CHANGE (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HBA_MAX_SG_EMBEDDED 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HBA_MAX_SG_SEPARATE 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HBA_SENSE_DATA_LEN_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HBA_SGL_FLAGS_EXT 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct aac_hba_sgl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 addr_lo; /* Lower 32-bits of SGL element address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 addr_hi; /* Upper 32-bits of SGL element address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 len; /* Length of SGL element in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 flags; /* SGL element flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) HBA_IU_TYPE_SATA_REQ = 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) HBA_IU_TYPE_RESP = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) HBA_IU_TYPE_COALESCED_RESP = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) HBA_RESP_DATAPRES_NO_DATA = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) HBA_RESP_DATAPRES_RESPONSE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) HBA_RESP_DATAPRES_SENSE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) HBA_RESP_SVCRES_FAILURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) HBA_RESP_SVCRES_TMF_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) HBA_RESP_SVCRES_TMF_SUCCEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HBA_RESP_SVCRES_TMF_REJECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HBA_RESP_SVCRES_TMF_LUN_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) HBA_RESP_STAT_IO_ERROR = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) HBA_RESP_STAT_IO_ABORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) HBA_RESP_STAT_NO_PATH_TO_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) HBA_RESP_STAT_INVALID_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) HBA_RESP_STAT_UNDERRUN = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) HBA_RESP_STAT_OVERRUN = 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct aac_hba_cmd_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 iu_type; /* HBA information unit type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * byte1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * [2] TYPE - 0=PCI, 1=DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 byte1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 reply_qid; /* Host reply queue to post response to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 it_nexus; /* Device handle for the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __le32 request_id; /* Sender context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Lower 32-bits of tweak value for crypto enabled IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 tweak_value_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 cdb[16]; /* SCSI CDB of the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 lun[8]; /* SCSI LUN of the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Total data length in bytes to be read/written (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __le32 data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* [2:0] Task Attribute, [6:3] Command Priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 attr_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Number of SGL elements embedded in the HBA req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 emb_data_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le16 dek_index; /* DEK index for crypto enabled IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Lower 32-bits of reserved error data target location on the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le32 error_ptr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Upper 32-bits of reserved error data target location on the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __le32 error_ptr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Length of reserved error data area on the host in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __le32 error_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Upper 32-bits of tweak value for crypto enabled IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __le32 tweak_value_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * structure must not exceed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Task Management Functions (TMF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HBA_TMF_ABORT_TASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HBA_TMF_LUN_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct aac_hba_tm_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 iu_type; /* HBA information unit type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 reply_qid; /* Host reply queue to post response to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 tmf; /* Task management function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __le32 it_nexus; /* Device handle for the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 lun[8]; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Used to hold sender context. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __le32 request_id; /* Sender context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Request identifier of managed task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __le32 managed_request_id; /* Sender context being managed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __le32 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Lower 32-bits of reserved error data target location on the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __le32 error_ptr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Upper 32-bits of reserved error data target location on the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __le32 error_ptr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Length of reserved error data area on the host in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __le32 error_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct aac_hba_reset_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 iu_type; /* HBA information unit type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* 0 - reset specified device, 1 - reset all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 reset_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 reply_qid; /* Host reply queue to post response to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __le32 it_nexus; /* Device handle for the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __le32 request_id; /* Sender context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Lower 32-bits of reserved error data target location on the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __le32 error_ptr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Upper 32-bits of reserved error data target location on the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __le32 error_ptr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Length of reserved error data area on the host in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __le32 error_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct aac_hba_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 iu_type; /* HBA information unit type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __le32 request_identifier; /* sender context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 service_response; /* SCSI service response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 status; /* SCSI status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 datapres; /* [1:0] - data present, [7:2] - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 sense_response_data_len; /* Sense/response data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __le32 residual_count; /* Residual data length in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Sense/response data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct aac_native_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct aac_hba_cmd_req cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct aac_hba_tm_req tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct aac_hba_resp err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CISS_REPORT_PHYSICAL_LUNS 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define WRITE_HOST_WELLNESS 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define BMIC_IN 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define BMIC_OUT 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct aac_ciss_phys_luns_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 list_length[4]; /* LUN list length (N-7, big endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 resp_flag; /* extended response_flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct _ciss_lun {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 tid[3]; /* Target ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 bus; /* Bus, flag (bits 6,7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 level3[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 level2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 node_ident[16]; /* phys. node identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } lun[1]; /* List of phys. devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define AAC_MAX_HRRQ 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct aac_ciss_identify_pd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 scsi_bus; /* SCSI Bus number on controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 scsi_id; /* SCSI ID on this bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u16 block_size; /* sector size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 total_blocks; /* number for sectors on drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 reserved_blocks; /* controller reserved (RIS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 model[40]; /* Physical Drive Model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 serial_number[40]; /* Drive Serial Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 firmware_revision[8]; /* drive firmware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 compaq_drive_stamp; /* 0 means drive not stamped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 last_failure_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 more_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 scsi_lun; /* SCSI LUN for phys drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 yet_more_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 even_more_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 phys_connector[2]; /* connector number on controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 phys_box_on_bus; /* phys enclosure this drive resides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 phys_bay_in_box; /* phys drv bay this drive resides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 rpm; /* Drive rotational speed in rpm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 device_type; /* type of drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 sata_version; /* only valid when drive_type is SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u64 big_total_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u64 ris_starting_lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 ris_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 wwid[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 controller_phy_map[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u16 phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 phy_connected_dev_type[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 phy_to_drive_bay_num[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u16 phy_to_attached_dev_index[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 box_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 spitfire_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u16 extra_physical_drive_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 negotiated_link_rate[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 phy_to_phy_map[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 redundant_path_present_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 redundant_path_failure_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 active_path_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u16 alternate_paths_phys_connector[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 alternate_paths_phys_box_on_port[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 multi_lun_device_lun_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 minimum_good_fw_revision[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 unique_inquiry_bytes[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 current_temperature_degreesC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 temperature_threshold_degreesC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u8 max_temperature_degreesC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u16 current_queue_depth_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 switch_name[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 switch_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 alternate_paths_switch_name[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 alternate_paths_switch_port[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u16 power_on_hours; /* valid only if gas gauge supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u16 percent_endurance_used; /* valid only if gas gauge supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 drive_authentication;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 smart_carrier_authentication;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 smart_carrier_app_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u8 smart_carrier_bootloader_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 SanitizeSecureEraseSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 DriveKeyFlags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 encryption_key_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 misc_drive_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u16 dek_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u16 drive_encryption_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 sanitize_maximum_time[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 connector_info_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 connector_info_number[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 long_connector_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 device_unique_identifier[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 padto_2K[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * These macros convert from physical channels to virtual channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CONTAINER_CHANNEL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define NATIVE_CHANNEL (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CONTAINER_TO_ID(cont) (cont)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CONTAINER_TO_LUN(cont) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define ENCLOSURE_CHANNEL (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PMC_DEVICE_S6 0x28b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PMC_DEVICE_S7 0x28c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PMC_DEVICE_S8 0x28d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define aac_phys_to_logical(x) ((x)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define aac_logical_to_phys(x) ((x)?(x)-1:0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * These macros are for keeping track of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * character device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define AAC_CHARDEV_UNREGISTERED (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define AAC_CHARDEV_NEEDS_REINIT (-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* #define AAC_DETAILED_STATUS_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct diskparm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int cylinders;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Firmware constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CT_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CT_OK 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Host side memory scatter gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Used by the adapter for read, write, and readdirplus operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * We have separate 32 and 64 bit version because even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * on 64 bit systems not all cards support the 64 bit version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct sgentry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __le32 addr; /* 32-bit address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __le32 count; /* Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct user_sgentry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 addr; /* 32-bit address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 count; /* Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct sgentry64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __le32 count; /* Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct user_sgentry64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 count; /* Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct sgentryraw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) __le32 next; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __le32 prev; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __le32 addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __le32 flags; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct user_sgentryraw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 next; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 prev; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 flags; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct sge_ieee1212 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 addrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 addrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * SGMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * This is the SGMAP structure for all commands that use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * 32-bit addressing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct sgmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct sgentry sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct user_sgmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct user_sgentry sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct sgmap64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct sgentry64 sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct user_sgmap64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct user_sgentry64 sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct sgmapraw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct sgentryraw sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct user_sgmapraw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct user_sgentryraw sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct creation_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 buildnum; /* e.g., 588 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 usec; /* e.g., 588 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u8 via; /* e.g., 1 = FSU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * 2 = API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 year; /* e.g., 1997 = 97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) __le32 date; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * unsigned Month :4; // 1 - 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * unsigned Day :6; // 1 - 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * unsigned Hour :6; // 0 - 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * unsigned Minute :6; // 0 - 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * unsigned Second :6; // 0 - 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * Define all the constants needed for the communication interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Define how many queue entries each queue will have and the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * number of entries for the entire communication interface. Also define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * how many queues we support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * This has to match the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define HOST_HIGH_CMD_ENTRIES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define HOST_NORM_CMD_ENTRIES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define ADAP_HIGH_CMD_ENTRIES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define ADAP_NORM_CMD_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define HOST_HIGH_RESP_ENTRIES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define HOST_NORM_RESP_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define ADAP_HIGH_RESP_ENTRIES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define ADAP_NORM_RESP_ENTRIES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define TOTAL_QUEUE_ENTRIES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Set the queues on a 16 byte alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define QUEUE_ALIGNMENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * The queue headers define the Communication Region queues. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * are physically contiguous and accessible by both the adapter and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * host. Even though all queue headers are in the same contiguous block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * they will be represented as individual units in the data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct aac_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) __le32 size; /* Size in bytes of Fib which this QE points to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) __le32 addr; /* Receiver address of the FIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * adjacently and in that order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct aac_qhdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __le64 header_addr;/* Address to hand the adapter to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) to this queue head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __le32 *producer; /* The producer index for this queue (host address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __le32 *consumer; /* The consumer index for this queue (host address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Define all the events which the adapter would like to notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * the host of.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define HostNormCmdQue 1 /* Change in host normal priority command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define HostHighCmdQue 2 /* Change in host high priority command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define HostNormRespQue 3 /* Change in host normal priority response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define HostHighRespQue 4 /* Change in host high priority response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define AdapNormRespNotFull 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define AdapHighRespNotFull 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define AdapNormCmdNotFull 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define AdapHighCmdNotFull 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SynchCommandComplete 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Define all the events the host wishes to notify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * adapter of. The first four values much match the Qid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * corresponding queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define AdapNormCmdQue 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define AdapHighCmdQue 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define AdapNormRespQue 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define AdapHighRespQue 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define HostShutdown 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define HostPowerFail 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define FatalCommError 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define HostNormRespNotFull 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define HostHighRespNotFull 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define HostNormCmdNotFull 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define HostHighCmdNotFull 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define FastIo 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define AdapPrintfDone 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Define all the queues that the adapter and host use to communicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Number them to match the physical queue layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) enum aac_queue_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) HostHighCmdQueue, /* Adapter to host high priority command traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) AdapHighCmdQueue, /* Host to adapter high priority command traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) HostNormRespQueue, /* Adapter to host normal priority response traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) HostHighRespQueue, /* Adapter to host high priority response traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) AdapNormRespQueue, /* Host to adapter normal priority response traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) AdapHighRespQueue /* Host to adapter high priority response traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Assign type values to the FSA communication data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define FIB_MAGIC 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define FIB_MAGIC2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define FIB_MAGIC2_64 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Define the priority levels the FSA communication routines support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define FsaNormal 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* transport FIB header (PMC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct aac_fib_xporthdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __le64 HostAddress; /* FIB host address w/o xport header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __le32 Size; /* FIB size excluding xport header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __le32 Handle; /* driver handle to reference the FIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __le64 Reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define ALIGN32 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Define the FIB. The FIB is the where all the requested data and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * command information are put to the application on the FSA adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct aac_fibhdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) __le32 XferState; /* Current transfer state for this CCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __le16 Command; /* Routing information for the destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u8 StructType; /* Type FIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 Unused; /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __le16 Size; /* Size of this FIB in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) __le16 SenderSize; /* Size of the FIB in the sender
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) (for response sizing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __le32 SenderFibAddress; /* Host defined data in the FIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) __le32 ReceiverFibAddress;/* Logical address of this FIB for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) the adapter (old) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) __le32 TimeStamp; /* otherwise timestamp for FW internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le32 Handle; /* FIB handle used for MSGU commnunication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 Previous; /* FW internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 Next; /* FW internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct hw_fib {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct aac_fibhdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * FIB commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define TestCommandResponse 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TestAdapterCommand 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * Lowlevel and comm commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define LastTestCommand 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define ReinitHostNormCommandQueue 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ReinitHostHighCommandQueue 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define ReinitHostHighRespQueue 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define ReinitHostNormRespQueue 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define ReinitAdapNormCommandQueue 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define ReinitAdapHighCommandQueue 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define ReinitAdapHighRespQueue 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define ReinitAdapNormRespQueue 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define InterfaceShutdown 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define DmaCommandFib 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define StartProfile 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define TermProfile 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SpeedTest 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define TakeABreakPt 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define RequestPerfData 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SetInterruptDefTimer 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SetInterruptDefCount 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define GetInterruptDefStatus 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define LastCommCommand 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * Filesystem commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define NuFileSystem 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define UFS 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define HostFileSystem 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define LastFileSystemCommand 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Container Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define ContainerCommand 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define ContainerCommand64 501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define ContainerRawIo 502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define ContainerRawIo2 503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Scsi Port commands (scsi passthrough)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define ScsiPortCommand 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define ScsiPortCommand64 601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Misc house keeping and generic adapter initiated commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define AifRequest 700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define CheckRevision 701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define FsaHostShutdown 702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define RequestAdapterInfo 703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define IsAdapterPaused 704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SendHostTime 705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define RequestSupplementAdapterInfo 706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define LastMiscCommand 707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Commands that will target the failover level on the FSA adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) enum fib_xfer_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) HostOwned = (1<<0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) AdapterOwned = (1<<1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) FibInitialized = (1<<2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) FibEmpty = (1<<3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) AllocatedFromPool = (1<<4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SentFromHost = (1<<5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SentFromAdapter = (1<<6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ResponseExpected = (1<<7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) NoResponseExpected = (1<<8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) AdapterProcessed = (1<<9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) HostProcessed = (1<<10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) HighPriority = (1<<11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) NormalPriority = (1<<12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) Async = (1<<13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) AsyncIo = (1<<13), // rpbfix: remove with new regime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PageFileIo = (1<<14), // rpbfix: remove with new regime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ShutdownRequest = (1<<15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) LazyWrite = (1<<16), // rpbfix: remove with new regime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) AdapterMicroFib = (1<<17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) BIOSFibPath = (1<<18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) FastResponseCapable = (1<<19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ApiFib = (1<<20), /* Its an API Fib */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* PMC NEW COMM: There is no more AIF data pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) NoMoreAifDataAvailable = (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * The following defines needs to be updated any time there is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * incompatible change made to the aac_init structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define ADAPTER_INIT_STRUCT_REVISION 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) union aac_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct _r7 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __le32 init_struct_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __le32 no_of_msix_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __le32 fsrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) __le32 comm_header_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __le32 fast_io_comm_area_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) __le32 adapter_fibs_physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __le32 adapter_fibs_virtual_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) __le32 adapter_fibs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) __le32 adapter_fib_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __le32 printfbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) __le32 printfbufsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* number of 4k pages of host phys. mem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) __le32 host_phys_mem_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* number of seconds since 1970. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) __le32 host_elapsed_seconds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __le32 init_flags; /* flags for supported features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) __le32 max_io_commands; /* max outstanding commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) __le32 max_io_size; /* largest I/O command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) __le32 max_fib_size; /* largest FIB to adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __le32 max_num_aif; /* max number of aif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Host RRQ (response queue) for SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __le32 host_rrq_addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __le32 host_rrq_addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } r7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct _r8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* ADAPTER_INIT_STRUCT_REVISION_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) __le32 init_struct_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) __le32 rr_queue_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __le32 host_elapsed_seconds; /* number of secs since 1970. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __le32 init_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __le32 max_io_size; /* largest I/O command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) __le32 max_num_aif; /* max number of aif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) __le32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct _rrq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) __le32 host_addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __le32 host_addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __le16 msix_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __le16 element_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __le16 comp_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) __le16 unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } rrq[1]; /* up to 64 RRQ addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } r8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) enum aac_log_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) LOG_AAC_INIT = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) LOG_AAC_INFORMATIONAL = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) LOG_AAC_WARNING = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) LOG_AAC_LOW_ERROR = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) LOG_AAC_MEDIUM_ERROR = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) LOG_AAC_HIGH_ERROR = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) LOG_AAC_PANIC = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) LOG_AAC_DEBUG = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) LOG_AAC_WINDBG_PRINT = 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define FSAFS_NTC_FIB_CONTEXT 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct aac_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct fib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct scsi_cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct adapter_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Low level operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) void (*adapter_interrupt)(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) void (*adapter_notify)(struct aac_dev *dev, u32 event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) void (*adapter_disable_int)(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) void (*adapter_enable_int)(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int (*adapter_check_health)(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) void (*adapter_start)(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Transport operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) irq_handler_t adapter_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Packet operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int (*adapter_deliver)(struct fib * fib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Administrative operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int (*adapter_comm)(struct aac_dev * dev, int comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Define which interrupt handler needs to be installed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct aac_driver_ident
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int (*init)(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) char * name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) char * vname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) char * model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u16 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * Some adapter firmware needs communication memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * below 2gig. This tells the init function to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * dma mask such that fib memory will be allocated where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * adapter firmware can get to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define AAC_QUIRK_31BIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * Some adapter firmware, when the raid card's cache is turned off, can not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * split up scatter gathers in order to deal with the limits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * underlying CHIM. This limit is 34 scatter gather elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define AAC_QUIRK_34SG 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * This adapter is a slave (no Firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define AAC_QUIRK_SLAVE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * This adapter is a master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define AAC_QUIRK_MASTER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * Some adapter firmware perform poorly when it must split up scatter gathers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * in order to deal with the limits of the underlying CHIM. This limit in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * class of adapters is 17 scatter gather elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define AAC_QUIRK_17SG 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * Some adapter firmware does not support 64 bit scsi passthrough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define AAC_QUIRK_SCSI_32 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * SRC based adapters support the AifReqEvent functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define AAC_QUIRK_SRC 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * The adapter interface specs all queues to be located in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * physically contiguous block. The host structure that defines the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * commuication queues will assume they are each a separate physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * contiguous memory region that will support them all being one big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * contiguous block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * There is a command and response queue for each level and direction of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * commuication. These regions are accessed by both the host and adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct aac_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u64 logical; /*address we give the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct aac_entry *base; /*system virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct aac_qhdr headers; /*producer,consumer q headers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 entries; /*Number of queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) wait_queue_head_t qfull; /*Event to wait on if q full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) wait_queue_head_t cmdready; /*Cmd ready from the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* This is only valid for adapter to host command queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* only valid for command queues which receive entries from the adapter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Number of entries on outstanding queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) atomic_t numpending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct aac_dev * dev; /* Back pointer to adapter structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * Message queues. The order here is important, see also the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * queue type ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct aac_queue_block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct aac_queue queue[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * SaP1 Message Unit Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct sa_drawbridge_CSR {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* Offset | Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __le32 reserved[10]; /* 00h-27h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u8 LUT_Offset; /* 28h | Lookup Table Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u8 reserved1[3]; /* 29h-2bh | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) __le32 LUT_Data; /* 2ch | Looup Table Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) __le32 reserved2[26]; /* 30h-97h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __le32 MAILBOX0; /* a8h | Scratchpad 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) __le32 MAILBOX1; /* ach | Scratchpad 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) __le32 MAILBOX2; /* b0h | Scratchpad 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __le32 MAILBOX3; /* b4h | Scratchpad 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) __le32 MAILBOX4; /* b8h | Scratchpad 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) __le32 MAILBOX5; /* bch | Scratchpad 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) __le32 MAILBOX6; /* c0h | Scratchpad 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __le32 MAILBOX7; /* c4h | Scratchpad 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __le32 reserved3[12]; /* d0h-ffh | reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define Mailbox0 SaDbCSR.MAILBOX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define Mailbox1 SaDbCSR.MAILBOX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define Mailbox2 SaDbCSR.MAILBOX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define Mailbox3 SaDbCSR.MAILBOX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define Mailbox4 SaDbCSR.MAILBOX4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define Mailbox5 SaDbCSR.MAILBOX5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define Mailbox6 SaDbCSR.MAILBOX6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define Mailbox7 SaDbCSR.MAILBOX7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define DoorbellReg_p SaDbCSR.PRISETIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define DoorbellReg_s SaDbCSR.SECSETIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define DOORBELL_0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define DOORBELL_1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define DOORBELL_2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define DOORBELL_3 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define DOORBELL_4 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define DOORBELL_5 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define DOORBELL_6 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define PrintfReady DOORBELL_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define PrintfDone DOORBELL_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct sa_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define SA_INIT_NUM_MSIXVECTORS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * Rx Message Unit Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct rx_mu_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* Local | PCI*| Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) __le32 reserved0; /* 1304h | 04h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) __le32 AWR; /* 1308h | 08h | APIC Window Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) __le32 reserved1; /* 130Ch | 0Ch | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) __le32 IISR; /* 1324h | 24h | Inbound Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) __le32 OISR; /* 1330h | 30h | Outbound Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) __le32 reserved2; /* 1338h | 38h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) __le32 reserved3; /* 133Ch | 3Ch | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* * Must access through ATU Inbound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) Translation Window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct rx_inbound {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) __le32 Mailbox[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define INBOUNDDOORBELL_0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define INBOUNDDOORBELL_1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define INBOUNDDOORBELL_2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define INBOUNDDOORBELL_3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define INBOUNDDOORBELL_4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define INBOUNDDOORBELL_5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define INBOUNDDOORBELL_6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define OUTBOUNDDOORBELL_0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define OUTBOUNDDOORBELL_1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define OUTBOUNDDOORBELL_2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define OUTBOUNDDOORBELL_3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define OUTBOUNDDOORBELL_4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define InboundDoorbellReg MUnit.IDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define OutboundDoorbellReg MUnit.ODR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct rx_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct rx_mu_registers MUnit; /* 1300h - 1347h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) __le32 reserved1[2]; /* 1348h - 134ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct rx_inbound IndexRegs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define rkt_mu_registers rx_mu_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define rkt_inbound rx_inbound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct rkt_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct rkt_mu_registers MUnit; /* 1300h - 1347h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) __le32 reserved1[1006]; /* 1348h - 22fch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct rkt_inbound IndexRegs; /* 2300h - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * PMC SRC message unit registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define src_inbound rx_inbound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct src_mu_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* PCI*| Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) __le32 reserved0[6]; /* 00h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) __le32 IDR; /* 20h | Inbound Doorbell Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) __le32 IISR; /* 24h | Inbound Int. Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) __le32 reserved1[3]; /* 28h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) __le32 OIMR; /* 34h | Outbound Int. Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) __le32 reserved2[25]; /* 38h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) __le32 reserved3[3]; /* a4h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) __le32 SCR0; /* b0h | Scratchpad 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) __le32 reserved4[2]; /* b4h | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) __le32 OMR; /* bch | Outbound Message Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) __le32 IQ_H; /* c4h | Inbound Queue (High address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) __le32 reserved5; /* cch | Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) __le32 IQN_L; /* d0h | Inbound (native cmd) low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) __le32 IQN_H; /* d4h | Inbound (native cmd) high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct src_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct src_mu_registers MUnit; /* 00h - cbh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) __le32 reserved1[130786]; /* d8h - 7fc5fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct src_inbound IndexRegs; /* 7fc60h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) } tupelo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) __le32 reserved1[970]; /* d8h - fffh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct src_inbound IndexRegs; /* 1000h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) } denali;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define src_writeb(AEP, CSR, value) writeb(value, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) &((AEP)->regs.src.bar0->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define src_writel(AEP, CSR, value) writel(value, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) &((AEP)->regs.src.bar0->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #if defined(writeq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define src_writeq(AEP, CSR, value) writeq(value, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) &((AEP)->regs.src.bar0->CSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define SRC_ODR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define SRC_IDR_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define SRC_MSI_READ_MASK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct aac_fib_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) s16 type; // used for verification of structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) s16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 unique; // unique value representing this context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ulong jiffies; // used for cleanup - dmb changed to ulong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct list_head next; // used to link context's into a linked list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct completion completion; // this is used to wait for the next fib to arrive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) int wait; // Set to true when thread is in WaitForSingleObject
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) unsigned long count; // total number of FIBs on FibList
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct list_head fib_list; // this holds fibs and their attachd hw_fibs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct sense_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) u8 error_code; /* 70h (current errors), 71h(deferred errors) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u8 valid:1; /* A valid bit of one indicates that the information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* field contains valid information as defined in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * SCSI-2 Standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u8 sense_key:4; /* Sense Key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) u8 reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) u8 ILI:1; /* Incorrect Length Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u8 EOM:1; /* End Of Medium - reserved for random access devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u8 filemark:1; /* Filemark - reserved for random access devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u8 information[4]; /* for direct-access devices, contains the unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * logical block address or residue associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * the sense key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u8 add_sense_len; /* number of additional sense bytes to follow this field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u8 cmnd_info[4]; /* not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) u8 ASC; /* Additional Sense Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) u8 ASCQ; /* Additional Sense Code Qualifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) u8 FRUC; /* Field Replaceable Unit Code - not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * was in error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * the bit_ptr field has valid value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) u8 reserved2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * 0- illegal parameter in data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) u8 SKSV:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct fsa_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u64 last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) u32 config_waiting_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) unsigned long config_waiting_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) u16 queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u8 config_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) u8 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u8 ro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) u8 locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u8 deleted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) char devname[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct sense_data sense_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u32 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u8 identifier[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct fib {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) void *next; /* this is used by the allocator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) s16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) s16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * The Adapter that this I/O is destined for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct aac_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * This is the event the sendfib routine will wait on if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * caller did not pass one and this is synch io.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct completion event_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) spinlock_t event_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u32 done; /* gets set to 1 when fib is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) fib_callback callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) void *callback_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 flags; // u32 dmb was ulong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * And for the internal issue/reply queues (we may be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * to merge these two)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct list_head fiblink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) u32 vector_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct hw_fib *hw_fib_va; /* also used for native */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dma_addr_t hw_sgl_pa; /* extra sgl for native */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dma_addr_t hw_error_pa; /* error buffer for native */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) u32 hbacmd_size; /* cmd size for native */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define AAC_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define AAC_RESCAN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define AAC_DEVTYPE_RAID_MEMBER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define AAC_DEVTYPE_ARC_RAW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define AAC_DEVTYPE_NATIVE_RAW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define AAC_RESCAN_DELAY (10 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct aac_hba_map_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) __le32 rmw_nexus; /* nexus for native HBA devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u8 devtype; /* device type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) s8 reset_state; /* 0 - no reset, 1..x - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* after xth TM LUN reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u16 qd_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) u32 scan_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct aac_ciss_identify_pd *safw_identify_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Adapter Information Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * This is returned by the RequestAdapterInfo block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct aac_adapter_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) __le32 platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) __le32 cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) __le32 subcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) __le32 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) __le32 execmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) __le32 buffermem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) __le32 totalmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) __le32 kernelrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) __le32 kernelbuild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) __le32 monitorrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) __le32 monitorbuild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) __le32 hwrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) __le32 hwbuild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) __le32 biosrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) __le32 biosbuild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) __le32 cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) __le32 clusterchannelmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) __le32 serial[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) __le32 battery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) __le32 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) __le32 OEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct aac_supplement_adapter_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) u8 adapter_type_text[17+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) u8 pad[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) __le32 flash_memory_byte_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) __le32 flash_image_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) __le32 max_number_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) __le32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) __le32 feature_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u8 slot_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u8 reserved_pad0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u8 build_date[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) __le32 current_number_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) u8 assembly_pn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u8 fru_pn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u8 battery_fru_pn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u8 ec_version_string[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u8 tsid[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) } vpd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) __le32 flash_firmware_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) __le32 flash_firmware_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) __le32 raid_type_morph_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) __le32 flash_firmware_boot_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) __le32 flash_firmware_boot_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) u8 mfg_pcba_serial_no[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) u8 mfg_wwn_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) __le32 supported_options2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) __le32 struct_expansion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* StructExpansion == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) __le32 feature_bits3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) __le32 supported_performance_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u8 host_bus_width; /* actual width in bits or links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u16 host_bus_speed; /* actual bus speed/link rate in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) u8 cpld_ver_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u8 cpld_ver_in_flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) __le64 max_rrc_capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) __le32 compiled_max_hist_log_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u8 custom_board_name[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u16 supported_cntlr_mode; /* identify supported controller mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) u16 reserved_for_future16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) __le32 supported_options3; /* reserved for future options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) __le16 virt_device_bus; /* virt. SCSI device for Thor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) __le16 virt_device_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) __le16 virt_device_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) __le16 unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) __le32 reserved_for_future_growth[68];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* SupportedOptions2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* 4KB sector size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* 240 simple volume support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * Supports FIB dump sync command send prior to IOP_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define AAC_SIS_VERSION_V3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define AAC_SIS_SLOT_UNKNOWN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define GetBusInfo 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct aac_bus_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) __le32 Command; /* VM_Ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) __le32 ObjType; /* FT_DRIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) __le32 MethodId; /* 1 = SCSI Layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) __le32 ObjectId; /* Handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) __le32 CtlCmd; /* GetBusInfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct aac_bus_info_response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) __le32 Status; /* ST_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) __le32 ObjType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) __le32 MethodId; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) __le32 ObjectId; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) __le32 CtlCmd; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) __le32 ProbeComplete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) __le32 BusCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) __le32 TargetsPerBus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) u8 InitiatorBusId[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) u8 BusValid[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * Battery platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define AAC_BAT_REQ_PRESENT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define AAC_BAT_REQ_NOTPRESENT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define AAC_BAT_OPT_PRESENT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define AAC_BAT_OPT_NOTPRESENT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define AAC_BAT_NOT_SUPPORTED (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * cpu types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define AAC_CPU_SIMULATOR (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define AAC_CPU_I960 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define AAC_CPU_STRONGARM (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * Supported Options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define AAC_OPT_ALARM cpu_to_le32(1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define AAC_COMM_PRODUCER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define AAC_COMM_MESSAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define AAC_COMM_MESSAGE_TYPE1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define AAC_COMM_MESSAGE_TYPE2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define AAC_COMM_MESSAGE_TYPE3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* MSIX context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct aac_msix_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int vector_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct aac_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct aac_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * negotiated FIB settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) unsigned int max_fib_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) unsigned int sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) unsigned int max_num_aif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * Map for 128 fib objects (64k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dma_addr_t hw_fib_pa; /* also used for native cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct hw_fib *hw_fib_va; /* also used for native cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct hw_fib *aif_base_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * Fib Headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct fib *fibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct fib *free_fib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) spinlock_t fib_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct mutex ioctl_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct mutex scan_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct aac_queue_block *queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * The user API will use an IOCTL to register itself to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * FIBs from the adapter. The following list is used to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * track of all the threads that have requested these FIBs. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * mutex is used to synchronize access to all data associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * with the adapter fibs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct list_head fib_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct adapter_ops a_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) unsigned long fsrev; /* Main driver's revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) resource_size_t base_start; /* main IO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) resource_size_t dbg_base; /* address of UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * debug buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) resource_size_t base_size, dbg_size; /* Size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * mapped in region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) * Holds initialization info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * to communicate with adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) union aac_init *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) dma_addr_t init_pa; /* Holds physical address of the init struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) __le32 *host_rrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dma_addr_t host_rrq_pa; /* phys. address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* index into rrq buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u32 host_rrq_idx[AAC_MAX_MSIX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) atomic_t rrq_outstanding[AAC_MAX_MSIX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) u32 fibs_pushed_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct pci_dev *pdev; /* Our PCI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* pointer to buffer used for printf's from the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) void *printfbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) void *comm_addr; /* Base address of Comm area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dma_addr_t comm_phys; /* Physical Address of Comm area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) size_t comm_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct Scsi_Host *scsi_host_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) int maximum_num_containers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) int maximum_num_physicals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int maximum_num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct fsa_dev_info *fsa_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct task_struct *thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct delayed_work safw_rescan_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct delayed_work src_reinit_aif_worker;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) int cardtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) *This lock will protect the two 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) *writes to the Inbound Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) spinlock_t iq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * The following is the device specific extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #ifndef AAC_MIN_FOOTPRINT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) # define AAC_MIN_FOOTPRINT_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) # define AAC_MIN_SRC_BAR0_SIZE 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) # define AAC_MIN_SRC_BAR1_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) # define AAC_MIN_SRCV_BAR0_SIZE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) # define AAC_MIN_SRCV_BAR1_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct sa_registers __iomem *sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct rx_registers __iomem *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) struct rkt_registers __iomem *rkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct src_registers __iomem *bar0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) char __iomem *bar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) } src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) } regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) volatile void __iomem *base, *dbg_base_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) volatile struct rx_inbound __iomem *IndexRegs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 OIMR; /* Mask Register Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * AIF thread states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) u32 aif_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct aac_adapter_info adapter_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct aac_supplement_adapter_info supplement_adapter_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* These are in adapter info but they are in the io flow so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * lets break them out so we don't have to do an AND to check them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) u8 nondasd_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u8 jbod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) u8 cache_protected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) u8 dac_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) u8 needs_dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) u8 raid_scsi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u8 comm_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) u8 raw_io_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u8 raw_io_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u8 printf_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u8 in_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) u8 in_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u8 msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) u8 sa_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) int management_fib_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) spinlock_t manage_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) spinlock_t sync_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) int sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct fib *sync_fib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) struct list_head sync_fib_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) u32 doorbell_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) u32 max_msix; /* max. MSI-X vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) u32 vector_cap; /* MSI-X vector capab.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) int msi_enabled; /* MSI/MSI-X enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) atomic_t msix_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u32 scan_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct msix_entry msixentry[AAC_MAX_MSIX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct aac_ciss_phys_luns_resp *safw_phys_luns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u8 adapter_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u32 handle_pci_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) bool init_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) u8 soft_reset_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define aac_adapter_interrupt(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) (dev)->a_ops.adapter_interrupt(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define aac_adapter_notify(dev, event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) (dev)->a_ops.adapter_notify(dev, event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define aac_adapter_disable_int(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) (dev)->a_ops.adapter_disable_int(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define aac_adapter_enable_int(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) (dev)->a_ops.adapter_enable_int(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define aac_adapter_restart(dev, bled, reset_type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define aac_adapter_start(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ((dev)->a_ops.adapter_start(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define aac_adapter_ioremap(dev, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) (dev)->a_ops.adapter_ioremap(dev, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define aac_adapter_deliver(fib) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ((fib)->dev)->a_ops.adapter_deliver(fib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define aac_adapter_bounds(dev,cmd,lba) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) dev->a_ops.adapter_bounds(dev,cmd,lba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define aac_adapter_read(fib,cmd,lba,count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define aac_adapter_write(fib,cmd,lba,count,fua) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define aac_adapter_scsi(fib,cmd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define aac_adapter_comm(dev,comm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) (dev)->a_ops.adapter_comm(dev, comm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define FIB_CONTEXT_FLAG (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define FIB_CONTEXT_FLAG_WAIT (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define FIB_CONTEXT_FLAG_EH_RESET (0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * Define the command values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define Null 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define GetAttributes 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define SetAttributes 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define Lookup 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define ReadLink 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define Read 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define Write 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define Create 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define MakeDirectory 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define SymbolicLink 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define MakeNode 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define Removex 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define RemoveDirectoryx 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define Rename 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define Link 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define ReadDirectory 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define ReadDirectoryPlus 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define FileSystemStatus 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define FileSystemInfo 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define PathConfigure 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define Commit 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define Mount 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define UnMount 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define Newfs 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define FsCheck 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define FsSync 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define SimReadWrite 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define SetFileSystemStatus 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define BlockRead 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define BlockWrite 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define NvramIoctl 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define FsSyncWait 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define ClearArchiveBit 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define SetAcl 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define GetAcl 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define AssignAcl 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define FaultInsertion 36 /* Fault Insertion Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define CrazyCache 37 /* Crazycache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define MAX_FSACOMMAND_NUM 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * Define the status returns. These are very unixlike although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * most are not in fact used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define ST_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define ST_PERM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define ST_NOENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define ST_IO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define ST_NXIO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define ST_E2BIG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define ST_MEDERR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define ST_ACCES 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define ST_EXIST 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define ST_XDEV 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define ST_NODEV 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define ST_NOTDIR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define ST_ISDIR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define ST_INVAL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define ST_FBIG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define ST_NOSPC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define ST_ROFS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define ST_MLINK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define ST_WOULDBLOCK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define ST_NAMETOOLONG 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define ST_NOTEMPTY 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define ST_DQUOT 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define ST_STALE 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define ST_REMOTE 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define ST_NOT_READY 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define ST_BADHANDLE 10001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define ST_NOT_SYNC 10002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define ST_BAD_COOKIE 10003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define ST_NOTSUPP 10004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define ST_TOOSMALL 10005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define ST_SERVERFAULT 10006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define ST_BADTYPE 10007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define ST_JUKEBOX 10008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define ST_NOTMOUNTED 10009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define ST_MAINTMODE 10010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define ST_STALEACL 10011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * On writes how does the client want the data written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define CACHE_CSTABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define CACHE_UNSTABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * Lets the client know at which level the data was committed on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * a write request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define CMFILE_SYNCH_NVRAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define CMDATA_SYNCH_NVRAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define CMFILE_SYNCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define CMDATA_SYNCH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define CMUNSTABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define RIO_TYPE_WRITE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define RIO_TYPE_READ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define RIO_SUREWRITE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define RIO2_IO_TYPE 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define RIO2_IO_TYPE_WRITE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define RIO2_IO_TYPE_READ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define RIO2_IO_TYPE_VERIFY 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define RIO2_IO_ERROR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define RIO2_IO_SUREWRITE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define RIO2_SGL_CONFORMANT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define RIO2_SG_FORMAT 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define RIO2_SG_FORMAT_ARC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define RIO2_SG_FORMAT_SRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define RIO2_SG_FORMAT_IEEE1212 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct aac_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) __le32 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct sgmap sg; // Must be last in struct because it is variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) struct aac_read64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) __le16 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) __le16 sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) __le32 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) __le16 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct sgmap64 sg; // Must be last in struct because it is variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) struct aac_read_reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) struct aac_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) __le32 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) __le32 stable; // Not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) struct sgmap sg; // Must be last in struct because it is variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct aac_write64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) __le16 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) __le16 sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) __le32 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) __le16 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct sgmap64 sg; // Must be last in struct because it is variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) struct aac_write_reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) __le32 committed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) struct aac_raw_io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) __le32 block[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) __le16 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) __le16 flags; /* 00 W, 01 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) __le16 bpTotal; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) __le16 bpComplete; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct sgmapraw sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) struct aac_raw_io2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) __le32 blockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) __le32 blockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) __le32 byteCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) __le16 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) __le16 flags; /* RIO2 flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) __le32 sgeFirstSize; /* size of first sge el. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) u8 sgeCnt; /* only 8 bits required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) u8 bpTotal; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u8 bpComplete; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) u8 sgeFirstIndex; /* reserved for F/W use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) u8 unused[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct sge_ieee1212 sge[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define CT_FLUSH_CACHE 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) struct aac_synchronize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) __le32 type; /* CT_FLUSH_CACHE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) __le32 parm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) __le32 parm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct aac_synchronize_reply {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) __le32 dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) __le32 dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) __le32 status; /* CT_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) __le32 parm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) __le32 parm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) __le32 parm5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) u8 data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define CT_POWER_MANAGEMENT 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define CT_PM_START_UNIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define CT_PM_STOP_UNIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define CT_PM_UNIT_IMMEDIATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) struct aac_power_management {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) __le32 type; /* CT_POWER_MANAGEMENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) __le32 sub; /* CT_PM_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) __le32 parm; /* CT_PM_sub_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define CT_PAUSE_IO 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define CT_RELEASE_IO 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct aac_pause {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) __le32 type; /* CT_PAUSE_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) __le32 timeout; /* 10ms ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) __le32 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) __le32 noRescan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct aac_srb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) __le32 function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) __le32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) __le32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) __le32 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) __le32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) __le32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) __le32 count; // Data xfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) __le32 retry_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) __le32 cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) u8 cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) struct sgmap sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * This and associated data structs are used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * ioctl caller and are in cpu order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct user_aac_srb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) u32 function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) u32 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) u32 count; // Data xfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) u32 retry_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) u32 cdb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) u8 cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct user_sgmap sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define AAC_SENSE_BUFFERSIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct aac_srb_reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) __le32 srb_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) __le32 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) __le32 data_xfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) __le32 sense_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct aac_srb_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) struct aac_srb srb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct aac_srb_reply srb_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * SRB Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define SRB_NoDataXfer 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define SRB_DisableDisconnect 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define SRB_DisableSynchTransfer 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define SRB_BypassFrozenQueue 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define SRB_DisableAutosense 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define SRB_DataIn 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define SRB_DataOut 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * SRB Functions - set in aac_srb->function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define SRBF_ExecuteScsi 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define SRBF_ClaimDevice 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define SRBF_IO_Control 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define SRBF_ReceiveEvent 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define SRBF_ReleaseQueue 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define SRBF_AttachDevice 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define SRBF_ReleaseDevice 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define SRBF_Shutdown 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define SRBF_Flush 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define SRBF_AbortCommand 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define SRBF_ReleaseRecovery 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define SRBF_ResetBus 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define SRBF_ResetDevice 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define SRBF_TerminateIO 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define SRBF_FlushQueue 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define SRBF_RemoveDevice 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define SRBF_DomainValidation 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * SRB SCSI Status - set in aac_srb->scsi_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define SRB_STATUS_PENDING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define SRB_STATUS_SUCCESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define SRB_STATUS_ABORTED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define SRB_STATUS_ABORT_FAILED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define SRB_STATUS_ERROR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define SRB_STATUS_BUSY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define SRB_STATUS_INVALID_REQUEST 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define SRB_STATUS_INVALID_PATH_ID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define SRB_STATUS_NO_DEVICE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define SRB_STATUS_TIMEOUT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define SRB_STATUS_MESSAGE_REJECTED 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define SRB_STATUS_BUS_RESET 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define SRB_STATUS_PARITY_ERROR 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define SRB_STATUS_NO_HBA 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define SRB_STATUS_DATA_OVERRUN 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define SRB_STATUS_REQUEST_FLUSHED 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define SRB_STATUS_DELAYED_RETRY 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define SRB_STATUS_INVALID_LUN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define SRB_STATUS_INVALID_TARGET_ID 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define SRB_STATUS_BAD_FUNCTION 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define SRB_STATUS_ERROR_RECOVERY 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) #define SRB_STATUS_NOT_STARTED 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define SRB_STATUS_NOT_IN_USE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define SRB_STATUS_FORCE_ABORT 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) * Object-Server / Volume-Manager Dispatch Classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define VM_Null 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define VM_NameServe 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) #define VM_ContainerConfig 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define VM_Ioctl 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define VM_FilesystemIoctl 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define VM_CloseAll 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define VM_CtBlockRead 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define VM_CtBlockWrite 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define VM_SliceBlockWrite 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define VM_DriveBlockRead 10 /* raw access to physical devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #define VM_DriveBlockWrite 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define VM_EnclosureMgt 12 /* enclosure management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define VM_Unused 13 /* used to be diskset management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define VM_CtBlockVerify 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) #define VM_CtPerf 15 /* performance test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define VM_CtBlockRead64 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define VM_CtBlockWrite64 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define VM_CtBlockVerify64 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define VM_CtHostRead64 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define VM_CtHostWrite64 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define VM_DrvErrTblLog 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define VM_NameServe64 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #define VM_NameServeAllBlk 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) * Descriptive information (eg, vital stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * that a content manager might report. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * FileArray filesystem component is one example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * of a content manager. Raw mode might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * another.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) struct aac_fsinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) __le32 fsBlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) __le32 fsFragSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) __le32 fsMaxExtendSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) __le32 fsSpaceUnits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) __le32 fsMaxNumFiles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) __le32 fsNumFreeFiles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) __le32 fsInodeDensity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) struct aac_blockdevinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) __le32 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) __le32 logical_phys_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) u8 identifier[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) union aac_contentinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) struct aac_fsinfo filesys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) struct aac_blockdevinfo bdevinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) * Query for Container Configuration Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define CT_GET_CONFIG_STATUS 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) struct aac_get_config_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) __le32 type; /* CT_GET_CONFIG_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) __le32 parm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) __le32 parm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) __le32 parm5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define CFACT_CONTINUE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define CFACT_PAUSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define CFACT_ABORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) struct aac_get_config_status_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) __le32 response; /* ST_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) __le32 dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) __le32 status; /* CT_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) __le32 parm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) __le32 parm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) __le32 parm5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) __le16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * Accept the configuration as-is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #define CT_COMMIT_CONFIG 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) struct aac_commit_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) __le32 type; /* CT_COMMIT_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * Query for Container Configuration Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #define CT_GET_CONTAINER_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct aac_get_container_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) __le32 type; /* CT_GET_CONTAINER_COUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) struct aac_get_container_count_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) __le32 response; /* ST_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) __le32 dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) __le32 MaxContainers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) __le32 ContainerSwitchEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) __le32 MaxPartitions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) __le32 MaxSimpleVolumes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * Query for "mountable" objects, ie, objects that are typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * associated with a drive letter on the client (host) side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct aac_mntent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) __le32 oid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) u8 name[16]; /* if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct creation_info create_info; /* if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) __le32 capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) __le32 vol; /* substrate structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) __le32 obj; /* FT_FILESYS, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) __le32 state; /* unready for mounting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) readonly, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) union aac_contentinfo fileinfo; /* Info specific to content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) manager (eg, filesystem) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) __le32 altoid; /* != oid <==> snapshot or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) broken mirror exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) __le32 capacityhigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) struct aac_query_mount {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) __le32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) struct aac_mount {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) __le32 type; /* should be same as that requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct aac_mntent mnt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define CT_READ_NAME 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct aac_get_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) __le32 type; /* CT_READ_NAME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) __le32 parm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) __le32 parm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct aac_get_name_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) __le32 dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) __le32 dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) __le32 status; /* CT_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) __le32 parm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) __le32 parm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) __le32 parm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) __le32 parm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) __le32 parm5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) u8 data[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #define CT_CID_TO_32BITS_UID 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) struct aac_get_serial {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) __le32 command; /* VM_ContainerConfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) __le32 type; /* CT_CID_TO_32BITS_UID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) struct aac_get_serial_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) __le32 dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) __le32 dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) __le32 status; /* CT_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) __le32 uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) * The following command is sent to shut down each container.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) struct aac_close {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) __le32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct aac_query_disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) s32 cnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) s32 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) s32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) s32 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) u32 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) u32 locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) u32 deleted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) s32 instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) s8 name[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) u32 unmapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) struct aac_delete_disk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) u32 disknum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) u32 cnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) struct fib_ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) u32 fibctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) s32 wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) char __user *fib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) struct revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) u32 compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) __le32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) __le32 build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) * Ugly - non Linux like ioctl coding for back compat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define CTL_CODE(function, method) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) (4<< 16) | ((function) << 2) | (method) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) * Define the method codes for how buffers are passed for I/O and FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) * controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #define METHOD_BUFFERED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #define METHOD_NEITHER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * Filesystem ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #define FSACTL_DELETE_DISK 0x163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) #define FSACTL_QUERY_DISK 0x173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #define FSACTL_GET_CONTAINERS 2131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* flags defined for IOP & HW SOFT RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) #define HW_IOP_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) #define HW_SOFT_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) #define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /* HW Soft Reset register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) #define IBW_SWR_OFFSET 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #define SOFT_RESET_TIME 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) struct aac_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * If this value is set to 1 then interrupt moderation will occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) * in the base commuication support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) u32 irq_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) u32 peak_fibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) u32 zero_fibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) u32 fib_timeouts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) * Statistical counters in debug mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) #ifdef DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) u32 FibsSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) u32 FibRecved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) u32 NativeSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) u32 NativeRecved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) u32 NoResponseSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) u32 NoResponseRecved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) u32 AsyncSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) u32 AsyncRecved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) u32 NormalSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) u32 NormalRecved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) extern struct aac_common aac_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) * This is for management ioctl purpose only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) struct aac_hba_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) u8 driver_name[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) u8 adapter_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) u8 system_io_bus_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) u8 device_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) u32 function_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) u32 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) u32 sub_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) u32 sub_system_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) u32 mapped_base_address_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) u32 base_physical_address_high_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) u32 base_physical_address_low_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) u32 max_command_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) u32 max_fib_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) u32 max_scatter_gather_from_os;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) u32 max_scatter_gather_to_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) u32 max_outstanding_fibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) u32 queue_start_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) u32 queue_dump_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) u32 max_io_size_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 outstanding_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) u32 firmware_build_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) u32 bios_build_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) u32 driver_build_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) u32 serial_number_high_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) u32 serial_number_low_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) u32 supported_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) u32 feature_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) u32 currentnumber_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) u8 new_comm_interface:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) u8 new_commands_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) u8 disable_passthrough:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) u8 expose_non_dasd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) u8 queue_allowed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) u8 bled_check_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) u8 reserved1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) u8 reserted2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) u32 reserved3[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) * The following macro is used when sending and receiving FIBs. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) * only used for debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #ifdef DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define FIB_COUNTER_INCREMENT(counter) (counter)++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define FIB_COUNTER_INCREMENT(counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * Adapter direct commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) * Monitor/Kernel API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define BREAKPOINT_REQUEST 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) #define INIT_STRUCT_BASE_ADDRESS 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) #define READ_PERMANENT_PARAMETERS 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define WRITE_PERMANENT_PARAMETERS 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #define HOST_CRASHING 0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) #define SEND_SYNCHRONOUS_FIB 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #define COMMAND_POST_RESULTS 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) #define GET_ADAPTER_PROPERTIES 0x00000019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) #define RCV_TEMP_READINGS 0x00000025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #define GET_COMM_PREFERRED_SETTINGS 0x00000026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define IOP_RESET_FW_FIB_DUMP 0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #define DROP_IO 0x00000035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) #define IOP_RESET 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) #define IOP_RESET_ALWAYS 0x00001001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define RE_INIT_ADAPTER 0x000000ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define IOP_SRC_RESET_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) * Adapter Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) * Phase Staus mailbox is 32bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) * <31:16> = Phase Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) * <15:0> = Phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) * The adapter reports is present state through the phase. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) * a single phase should be ever be set. Each phase can have multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) * phase status bits to provide more detailed information about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) * state of the board. Care should be taken to ensure that any phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) * status bits that are set when changing the phase are also valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) * for the new phase or be cleared out. Adapter software (monitor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) * iflash, kernel) is responsible for properly maintining the phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) * status mailbox when it is running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) * MONKER_API Phases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) * Phases are bit oriented. It is NOT valid to have multiple bits set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) #define SELF_TEST_FAILED 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) #define MONITOR_PANIC 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) #define KERNEL_BOOTING 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) #define KERNEL_UP_AND_RUNNING 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) #define KERNEL_PANIC 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) #define FLASH_UPD_PENDING 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #define FLASH_UPD_SUCCESS 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) #define FLASH_UPD_FAILED 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) #define INVALID_OMR 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) #define FWUPD_TIMEOUT (5 * 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) * Doorbell bit defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #define DoorBellAifPending (1<<6) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) /* PMC specific outbound doorbell bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) * For FIB communication, we need all of the following things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) * to send back to the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #define AifCmdEventNotify 1 /* Notify of event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) #define AifEnConfigChange 3 /* Adapter configuration change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #define AifEnContainerChange 4 /* Container configuration change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) #define AifEnDeviceFailure 5 /* SCSI device failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define EM_DRIVE_INSERTION 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #define EM_DRIVE_REMOVAL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) #define EM_SES_DRIVE_INSERTION 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define EM_SES_DRIVE_REMOVAL 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) #define AifEnBatteryEvent 14 /* Change in Battery State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) #define AifEnAddContainer 15 /* A new array was created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) #define AifEnDeleteContainer 16 /* A container was deleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #define AifEnExpEvent 23 /* Firmware Event Log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) #define AifExeFirmwarePanic 3 /* Firmware Event Panic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) #define AifHighPriority 3 /* Highest Priority Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) #define AifEnAddJBOD 30 /* JBOD created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) #define AifEnDeleteJBOD 31 /* JBOD deleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #define AifBuManagerEvent 42 /* Bu management*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #define AifBuCacheDataLoss 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) #define AifBuCacheDataRecover 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) #define AifCmdJobProgress 2 /* Progress report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) #define AifJobCtrZero 101 /* Array Zero progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define AifJobStsSuccess 1 /* Job completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #define AifJobStsRunning 102 /* Job running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) #define AifCmdAPIReport 3 /* Report from other user of API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) #define AifCmdDriverNotify 4 /* Notify host driver of event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) #define AifDenMorphComplete 200 /* A morph operation completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #define AifDenVolumeExtendComplete 201 /* A volume extend completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) #define AifReqJobList 100 /* Gets back complete job list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) #define AifReqTerminateJob 104 /* Terminates job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) #define AifReqSuspendJob 105 /* Suspends a job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) #define AifReqResumeJob 106 /* Resumes a job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) #define AifReqSendAPIReport 107 /* API generic report requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) #define AifReqAPIJobStart 108 /* Start a job from the API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) #define AifReqAPIJobFinish 110 /* Finish a job from the API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) /* PMC NEW COMM: Request the event data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) #define AifReqEvent 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) #define AifRawDeviceRemove 203 /* RAW device deleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) #define AifNativeDeviceAdd 204 /* native HBA device added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) #define AifNativeDeviceRemove 205 /* native HBA device removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * Adapter Initiated FIB command structures. Start with the adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) * initiated FIBs that really come from the adapter, and get responded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) * to by the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) struct aac_aifcmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) __le32 command; /* Tell host what type of notify this is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) __le32 seqnum; /* To allow ordering of reports (if necessary) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) u8 data[1]; /* Undefined length (from kernel viewpoint) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) * Convert capacity to cylinders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) * accounting for the fact capacity could be a 64 bit value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) sector_div(capacity, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) return capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static inline int aac_pci_offline(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) return pci_channel_offline(dev->pdev) || dev->handle_pci_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static inline int aac_adapter_check_health(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (unlikely(aac_pci_offline(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return (dev)->a_ops.adapter_check_health(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) int aac_scan_host(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) static inline void aac_schedule_src_reinit_aif_worker(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static inline void aac_safw_rescan_worker(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) struct aac_dev *dev = container_of(to_delayed_work(work),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) struct aac_dev, safw_rescan_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) wait_event(dev->scsi_host_ptr->host_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) !scsi_host_in_recovery(dev->scsi_host_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) aac_scan_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static inline void aac_cancel_rescan_worker(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) cancel_delayed_work_sync(&dev->safw_rescan_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) cancel_delayed_work_sync(&dev->src_reinit_aif_worker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) /* SCp.phase values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define AAC_OWNER_MIDLEVEL 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #define AAC_OWNER_LOWLEVEL 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) #define AAC_OWNER_ERROR_HANDLER 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) #define AAC_OWNER_FIRMWARE 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) void aac_safw_rescan_worker(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) void aac_src_reinit_aif_worker(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) int aac_acquire_irq(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) void aac_free_irq(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) int aac_setup_safw_adapter(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) const char *aac_driverinfo(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) void aac_fib_vector_assign(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) struct fib *aac_fib_alloc(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) int aac_fib_setup(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) void aac_fib_map_free(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) void aac_fib_free(struct fib * context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) void aac_fib_init(struct fib * context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) void aac_printf(struct aac_dev *dev, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) int aac_hba_send(u8 command, struct fib *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) fib_callback callback, void *ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) int aac_fib_complete(struct fib * context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) void aac_hba_callback(void *context, struct fib *fibptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) struct aac_dev *aac_init_adapter(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) void aac_src_access_devreg(struct aac_dev *dev, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) void aac_set_intx_mode(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) int aac_get_config_status(struct aac_dev *dev, int commit_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) int aac_get_containers(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) int aac_scsi_cmd(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #ifndef shost_to_class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #define shost_to_class(shost) &shost->shost_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) ssize_t aac_get_serial_number(struct device *dev, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) int aac_rx_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) int aac_rkt_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) int aac_nark_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) int aac_sa_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) int aac_src_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) int aac_srcv_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) void aac_define_int_mode(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) unsigned int aac_response_normal(struct aac_queue * q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) unsigned int aac_command_normal(struct aac_queue * q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) int isAif, int isFastResponse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) struct hw_fib *aif_fib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) int aac_check_health(struct aac_dev * dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) int aac_command_thread(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) struct aac_driver_ident* aac_get_driver_ident(int devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) int aac_get_adapter_info(struct aac_dev* dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) int aac_send_shutdown(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) int aac_probe_container(struct aac_dev *dev, int cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) int _aac_rx_init(struct aac_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) int aac_rx_select_comm(struct aac_dev *dev, int comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) int aac_rx_deliver_producer(struct fib * fib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) void aac_reinit_aif(struct aac_dev *aac, unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) static inline int aac_is_src(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) u16 device = dev->pdev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (device == PMC_DEVICE_S6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) device == PMC_DEVICE_S7 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) device == PMC_DEVICE_S8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static inline int aac_supports_2T(struct aac_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) char * get_container_type(unsigned type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) extern int numacb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) extern char aac_driver_version[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) extern int startup_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) extern int aif_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) extern int expose_physicals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) extern int aac_reset_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) extern int aac_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) extern int aac_commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) extern int update_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) extern int check_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) extern int aac_check_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) extern int aac_fib_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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