Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef A3000_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define A3000_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* $Id: a3000.h,v 1.4 1997/01/19 23:07:10 davem Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Header file for the Amiga 3000 built-in SCSI controller for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Written and (C) 1993, Hamish Macdonald, see a3000.c for more info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef CMD_PER_LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CMD_PER_LUN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef CAN_QUEUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CAN_QUEUE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * if the transfer address ANDed with this results in a non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * result, then we can't use DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define A3000_XFER_MASK		(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct a3000_scsiregs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		 unsigned char	pad1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	volatile unsigned short	DAWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	volatile unsigned int	WTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		 unsigned char	pad2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	volatile unsigned short	CNTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	volatile unsigned long	ACR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		 unsigned char	pad3[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	volatile unsigned short	ST_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		 unsigned char	pad4[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	volatile unsigned short	FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		 unsigned char	pad5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	volatile unsigned short	CINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		 unsigned char	pad6[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	volatile unsigned short	ISTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		 unsigned char	pad7[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	volatile unsigned short	SP_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		 unsigned char	pad8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	volatile unsigned char	SASR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		 unsigned char	pad9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	volatile unsigned char	SCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAWR_A3000		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* CNTR bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CNTR_TCEN		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CNTR_PREST		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CNTR_PDMD		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CNTR_INTEN		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CNTR_DDIR		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CNTR_IO_DX		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ISTR bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ISTR_INTX		(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ISTR_INT_F		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ISTR_INTS		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ISTR_E_INT		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ISTR_INT_P		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ISTR_UE_INT		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ISTR_OE_INT		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ISTR_FF_FLG		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ISTR_FE_FLG		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* A3000_H */