^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Initio A100 device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1994-1998 Initio Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2003-2004 Christoph Hellwig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the Free Software Foundation; either version 2, or (at your option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * along with this program; see the file COPYING. If not, write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Revision History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 07/02/98 hl - v.91n Initial drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 09/14/98 hl - v1.01 Support new Kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 09/22/98 hl - v1.01a Support reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 09/24/98 hl - v1.01b Fixed reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 10/05/98 hl - v1.02 split the source code and release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 12/19/98 bv - v1.02a Use spinlocks for 2.1.95 and up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 01/31/99 bv - v1.02b Use mdelay instead of waitForPause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 08/08/99 bv - v1.02c Use waitForPause again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 06/25/02 Doug Ledford <dledford@redhat.com> - v1.02d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * - Remove limit on number of controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - Port to DMA mapping API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * - Clean up interrupt handler registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * - Fix memory leaks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * - Fix allocation of scsi host structs and private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 11/18/03 Christoph Hellwig <hch@lst.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * - Port to new probing API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * - Fix some more leaks in init failure cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 9/28/04 Christoph Hellwig <hch@lst.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * - merge the two source files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * - remove internal queueing code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 14/06/07 Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * - Grand cleanup and Linuxisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include "a100u2w.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct orc_scb *__orc_alloc_scb(struct orc_host * host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct orc_nvram nvram, *nvramp = &nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static u8 default_nvram[64] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*----------header -------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x01, /* 0x00: Sub System Vendor ID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x11, /* 0x01: Sub System Vendor ID 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x60, /* 0x02: Sub System ID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x10, /* 0x03: Sub System ID 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x00, /* 0x04: SubClass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x01, /* 0x05: Vendor ID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x11, /* 0x06: Vendor ID 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x60, /* 0x07: Device ID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x10, /* 0x08: Device ID 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x00, /* 0x09: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x00, /* 0x0A: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x01, /* 0x0B: Revision of Data Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* -- Host Adapter Structure --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x01, /* 0x0C: Number Of SCSI Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x01, /* 0x0D: BIOS Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x00, /* 0x0E: BIOS Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x00, /* 0x0F: BIOS Configuration 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* --- SCSI Channel 0 Configuration --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x07, /* 0x10: H/A ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x83, /* 0x11: Channel Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x20, /* 0x12: MAX TAG per target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x0A, /* 0x13: SCSI Reset Recovering time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x00, /* 0x14: Channel Configuration4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x00, /* 0x15: Channel Configuration5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* SCSI Channel 0 Target Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* 0x16-0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* --- SCSI Channel 1 Configuration --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x07, /* 0x26: H/A ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x83, /* 0x27: Channel Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x20, /* 0x28: MAX TAG per target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x0A, /* 0x29: SCSI Reset Recovering time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x00, /* 0x2A: Channel Configuration4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x00, /* 0x2B: Channel Configuration5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* SCSI Channel 1 Target Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* 0x2C-0x3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x00, /* 0x3C: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x00, /* 0x3D: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x00, /* 0x3E: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x00 /* 0x3F: Checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static u8 wait_chip_ready(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static u8 wait_firmware_ready(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (inb(host->base + ORC_HSTUS) & RREADY) /* Wait READY set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msleep(100); /* wait 100ms before try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u8 wait_scsi_reset_done(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mdelay(100); /* wait 100ms before try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static u8 wait_HDO_off(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!(inb(host->base + ORC_HCTRL) & HDO)) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mdelay(100); /* wait 100ms before try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static u8 wait_hdi_set(struct orc_host * host, u8 * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if ((*data = inb(host->base + ORC_HSTUS)) & HDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 1; /* Wait HDI set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mdelay(100); /* wait 100ms before try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static unsigned short orc_read_fwrev(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outb(ORC_CMD_VERSION, host->base + ORC_HDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) version = inb(host->base + ORC_HDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) outb(data, host->base + ORC_HSTUS); /* Clear HDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) version |= inb(host->base + ORC_HDATA) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) outb(data, host->base + ORC_HSTUS); /* Clear HDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static u8 orc_nv_write(struct orc_host * host, unsigned char address, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) outb(ORC_CMD_SET_NVM, host->base + ORC_HDATA); /* Write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) outb(address, host->base + ORC_HDATA); /* Write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) outb(value, host->base + ORC_HDATA); /* Write value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static u8 orc_nv_read(struct orc_host * host, u8 address, u8 *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) outb(ORC_CMD_GET_NVM, host->base + ORC_HDATA); /* Write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) outb(address, host->base + ORC_HDATA); /* Write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *ptr = inb(host->base + ORC_HDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) outb(data, host->base + ORC_HSTUS); /* Clear HDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * orc_exec_sb - Queue an SCB with the HA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @host: host adapter the SCB belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @scb: SCB to queue for execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void orc_exec_scb(struct orc_host * host, struct orc_scb * scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) scb->status = ORCSCB_POST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) outb(scb->scbidx, host->base + ORC_PQUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * se2_rd_all - read SCSI parameters from EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @host: Host whose EEPROM is being loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Read SCSI H/A configuration parameters from serial EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int se2_rd_all(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 *np, chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) np = (u8 *) nvramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (i = 0; i < 64; i++, np++) { /* <01> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (orc_nv_read(host, (u8) i, np) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*------ Is ckecksum ok ? ------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) np = (u8 *) nvramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < 63; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) chksum += *np++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (nvramp->CheckSum != (u8) chksum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * se2_update_all - update the EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @host: Host whose EEPROM is being updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Update changed bytes in the EEPROM image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void se2_update_all(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { /* setup default pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 *np, *np1, chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Calculate checksum first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) np = (u8 *) default_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (i = 0; i < 63; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) chksum += *np++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *np = chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) np = (u8 *) default_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) np1 = (u8 *) nvramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) for (i = 0; i < 64; i++, np++, np1++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (*np != *np1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) orc_nv_write(host, (u8) i, *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * read_eeprom - load EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @host: Host EEPROM to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Read the EEPROM for a given host. If it is invalid or fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * the restore the defaults and use them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void read_eeprom(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (se2_rd_all(host) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) se2_update_all(host); /* setup default pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) se2_rd_all(host); /* load again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * orc_load_firmware - initialise firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @host: Host to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Load the firmware from the EEPROM into controller SRAM. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * is basically a 4K block copy and then a 4K block read to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * correctness. The rest is convulted by the indirect interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * in the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static u8 orc_load_firmware(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u16 bios_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 *data32_ptr, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Set up the EEPROM for access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) data = inb(host->base + ORC_GCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) outb(data | EEPRG, host->base + ORC_GCFG); /* Enable EEPROM programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) outb(0x00, host->base + ORC_EBIOSADR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) outw(0x0000, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (inb(host->base + ORC_EBIOSDATA) != 0x55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) outw(0x0001, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (inb(host->base + ORC_EBIOSDATA) != 0xAA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) data32_ptr = (u8 *) & data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data32 = cpu_to_le32(0); /* Initial FW address to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) outw(0x0010, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) outw(0x0011, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) outw(0x0012, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) outl(le32_to_cpu(data32), host->base + ORC_FWBASEADR); /* Write FW address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Copy the code from the BIOS to the SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) udelay(500); /* Required on Sun Ultra 5 ... 350 -> failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) bios_addr = (u16) le32_to_cpu(data32); /* FW code locate at BIOS address + ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (i = 0, data32_ptr = (u8 *) & data32; /* Download the code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) i < 0x1000; /* Firmware code size = 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) i++, bios_addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) outw(bios_addr, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if ((i % 4) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) outl(le32_to_cpu(data32), host->base + ORC_RISCRAM); /* Write every 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) data32_ptr = (u8 *) & data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Go back and check they match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bios_addr -= 0x1000; /* Reset the BIOS address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (i = 0, data32_ptr = (u8 *) & data32; /* Check the code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) i < 0x1000; /* Firmware code size = 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) i++, bios_addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) outw(bios_addr, host->base + ORC_EBIOSADR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if ((i % 4) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (inl(host->base + ORC_RISCRAM) != le32_to_cpu(data32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) data32_ptr = (u8 *) & data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void setup_SCBs(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct orc_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct orc_extended_scb *escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dma_addr_t escb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Setup SCB base and SCB Size registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) outb(ORC_MAXQUEUE, host->base + ORC_SCBSIZE); /* Total number of SCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* SCB base address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) outl(host->scb_phys, host->base + ORC_SCBBASE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* SCB base address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) outl(host->scb_phys, host->base + ORC_SCBBASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* setup scatter list address with one buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) scb = host->scb_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) escb = host->escb_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for (i = 0; i < ORC_MAXQUEUE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) escb_phys = (host->escb_phys + (sizeof(struct orc_extended_scb) * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) scb->sg_addr = cpu_to_le32((u32) escb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) scb->sense_addr = cpu_to_le32((u32) escb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) scb->escb = escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) scb->scbidx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) scb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) escb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * init_alloc_map - initialise allocation map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @host: host map to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Initialise the allocation maps for this device. If the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * is not quiescent the caller must hold the allocation lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void init_alloc_map(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for (i = 0; i < MAX_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) host->allocation_map[i][j] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * init_orchid - initialise the host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * @host:host adapter to initialise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Initialise the controller and if necessary load the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Returns -1 if the initialisation fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int init_orchid(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) init_alloc_map(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) revision = orc_read_fwrev(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (revision == 0xFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (wait_chip_ready(host) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) orc_load_firmware(host); /* Download FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) setup_SCBs(host); /* Setup SCB base and SCB Size registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (wait_firmware_ready(host) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Wait for firmware ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) setup_SCBs(host); /* Setup SCB base and SCB Size registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } else { /* Orchid is not Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (wait_chip_ready(host) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) orc_load_firmware(host); /* Download FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) setup_SCBs(host); /* Setup SCB base and SCB Size registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) outb(HDO, host->base + ORC_HCTRL); /* Do Hardware Reset & */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* clear HOSTSTOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (wait_firmware_ready(host) == 0) /* Wait for firmware ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Load an EEProm copy into RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Assumes single threaded at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) read_eeprom(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (nvramp->revision != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) host->scsi_id = nvramp->scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) host->BIOScfg = nvramp->BIOSConfig1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) host->max_targets = MAX_TARGETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ptr = (u8 *) & (nvramp->Target00Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (i = 0; i < 16; ptr++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) host->target_flag[i] = *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) host->max_tags[i] = ORC_MAXTAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (nvramp->SCSI0Config & NCC_BUSRESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) host->flags |= HCF_SCSI_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * orc_reset_scsi_bus - perform bus reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @host: host being reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Perform a full bus reset on the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int orc_reset_scsi_bus(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { /* I need Host Control Block Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) spin_lock_irqsave(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) init_alloc_map(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* reset scsi bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) outb(SCSIRST, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* FIXME: We can spend up to a second with the lock held and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) interrupts off here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (wait_scsi_reset_done(host) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) spin_unlock_irqrestore(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) spin_unlock_irqrestore(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * orc_device_reset - device reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * @host: host to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * @cmd: command causing the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * @target; target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Reset registers, reset a hanging bus and kill active and disconnected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * commands for target w/o soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int orc_device_reset(struct orc_host * host, struct scsi_cmnd *cmd, unsigned int target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { /* I need Host Control Block Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct orc_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct orc_extended_scb *escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct orc_scb *host_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_lock_irqsave(&(host->allocation_lock), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) scb = (struct orc_scb *) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) escb = (struct orc_extended_scb *) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* setup scatter list address with one buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) host_scb = host->scb_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* FIXME: is this safe if we then fail to issue the reset or race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) a completion ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) init_alloc_map(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Find the scb corresponding to the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) for (i = 0; i < ORC_MAXQUEUE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) escb = host_scb->escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (host_scb->status && escb->srb == cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) host_scb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (i == ORC_MAXQUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) printk(KERN_ERR "Unable to Reset - No SCB Found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) spin_unlock_irqrestore(&(host->allocation_lock), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Allocate a new SCB for the reset command to the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if ((scb = __orc_alloc_scb(host)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Can't happen.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spin_unlock_irqrestore(&(host->allocation_lock), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Reset device is handled by the firmware, we fill in an SCB and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fire it at the controller, it does the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) scb->opcode = ORC_BUSDEVRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) scb->target = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) scb->hastat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) scb->tastat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) scb->status = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) scb->link = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) scb->reserved0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) scb->reserved1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) scb->xferlen = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) scb->sg_len = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) escb->srb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) escb->srb = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) orc_exec_scb(host, scb); /* Start execute SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spin_unlock_irqrestore(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * __orc_alloc_scb - allocate an SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * @host: host to allocate from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * Allocate an SCB and return a pointer to the SCB object. NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * is returned if no SCB is free. The caller must already hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * the allocator lock at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static struct orc_scb *__orc_alloc_scb(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned long idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) channel = host->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) for (index = 0; index < 32; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((host->allocation_map[channel][i] >> index) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) host->allocation_map[channel][i] &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) idx = index + 32 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * Translate the index to a structure instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return host->scb_virt + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * orc_alloc_scb - allocate an SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * @host: host to allocate from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * Allocate an SCB and return a pointer to the SCB object. NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * is returned if no SCB is free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct orc_scb *orc_alloc_scb(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct orc_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spin_lock_irqsave(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) scb = __orc_alloc_scb(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spin_unlock_irqrestore(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * orc_release_scb - release an SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @host: host owning the SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @scb: SCB that is now free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Called to return a completed SCB to the allocation pool. Before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * calling the SCB must be out of use on both the host and the HA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void orc_release_scb(struct orc_host *host, struct orc_scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u8 index, i, channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) spin_lock_irqsave(&(host->allocation_lock), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) channel = host->index; /* Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) index = scb->scbidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) i = index / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) index %= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) host->allocation_map[channel][i] |= (1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spin_unlock_irqrestore(&(host->allocation_lock), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * orchid_abort_scb - abort a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * Abort a queued command that has been passed to the firmware layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * if possible. This is all handled by the firmware. We aks the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * and it either aborts the command or fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int orchid_abort_scb(struct orc_host * host, struct orc_scb * scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) unsigned char data, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) outb(ORC_CMD_ABORT_SCB, host->base + ORC_HDATA); /* Write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) outb(scb->scbidx, host->base + ORC_HDATA); /* Write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) outb(HDO, host->base + ORC_HCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (wait_HDO_off(host) == 0) /* Wait HDO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) status = inb(host->base + ORC_HDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) outb(data, host->base + ORC_HSTUS); /* Clear HDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (status == 1) /* 0 - Successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0; /* 1 - Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int inia100_abort_cmd(struct orc_host * host, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct orc_extended_scb *escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct orc_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_lock_irqsave(&(host->allocation_lock), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) scb = host->scb_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Walk the queue until we find the SCB that belongs to the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) block. This isn't a performance critical path so a walk in the park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) here does no harm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) for (i = 0; i < ORC_MAXQUEUE; i++, scb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) escb = scb->escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (scb->status && escb->srb == cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (scb->tag_msg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Issue an ABORT to the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (orchid_abort_scb(host, scb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) escb->srb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) spin_unlock_irqrestore(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) spin_unlock_irqrestore(&host->allocation_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * orc_interrupt - IRQ processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * @host: Host causing the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * This function is called from the IRQ handler and protected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * by the host lock. While the controller reports that there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * scb's for processing we pull them off the controller, turn the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * index into a host address pointer to the scb and call the scb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * Returns IRQ_HANDLED if any SCBs were processed, IRQ_NONE otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static irqreturn_t orc_interrupt(struct orc_host * host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 scb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct orc_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Check if we have an SCB queued for servicing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (inb(host->base + ORC_RQUEUECNT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Get the SCB index of the SCB to service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) scb_index = inb(host->base + ORC_RQUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Translate it back to a host pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) scb = (struct orc_scb *) ((unsigned long) host->scb_virt + (unsigned long) (sizeof(struct orc_scb) * scb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) scb->status = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Process the SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) inia100_scb_handler(host, scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) } while (inb(host->base + ORC_RQUEUECNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) } /* End of I1060Interrupt() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * inia100_build_scb - build SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * @host: host owing the control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * @scb: control block to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * @cmd: Mid layer command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * Build a host adapter control block from the SCSI mid layer command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int inia100_build_scb(struct orc_host * host, struct orc_scb * scb, struct scsi_cmnd * cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) { /* Create corresponding SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct orc_sgent *sgent; /* Pointer to SG list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int i, count_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct orc_extended_scb *escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Links between the escb, scb and Linux scsi midlayer cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) escb = scb->escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) escb->srb = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) sgent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Set up the SCB to do a SCSI command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) scb->opcode = ORC_EXECSCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) scb->flags = SCF_NO_DCHK; /* Clear done bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) scb->target = cmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) scb->lun = cmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) scb->reserved0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) scb->reserved1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) scb->sg_len = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) scb->xferlen = cpu_to_le32((u32) scsi_bufflen(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) sgent = (struct orc_sgent *) & escb->sglist[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) count_sg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (count_sg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return count_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) BUG_ON(count_sg > TOTAL_SG_ENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Build the scatter gather lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (count_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) scb->sg_len = cpu_to_le32((u32) (count_sg * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) scsi_for_each_sg(cmd, sg, count_sg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) sgent->base = cpu_to_le32((u32) sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) sgent->length = cpu_to_le32((u32) sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) sgent++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) scb->sg_len = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) sgent->base = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) sgent->length = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) scb->sg_addr = (u32) scb->sense_addr; /* sense_addr is already little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) scb->hastat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) scb->tastat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) scb->link = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) scb->sense_len = SENSE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) scb->cdb_len = cmd->cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (scb->cdb_len >= IMAX_CDB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) printk("max cdb length= %x\n", cmd->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) scb->cdb_len = IMAX_CDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) scb->ident = (u8)(cmd->device->lun & 0xff) | DISC_ALLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (cmd->device->tagged_supported) { /* Tag Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) scb->tag_msg = SIMPLE_QUEUE_TAG; /* Do simple tag only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) scb->tag_msg = 0; /* No tag support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) memcpy(scb->cdb, cmd->cmnd, scb->cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * inia100_queue - queue command with host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * @cmd: Command block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * @done: Completion function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Called by the mid layer to queue a command. Process the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * block, build the host specific scb structures and if there is room
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * queue the command down to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int inia100_queue_lck(struct scsi_cmnd * cmd, void (*done) (struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct orc_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct orc_host *host; /* Point to Host adapter control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) host = (struct orc_host *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Get free SCSI control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if ((scb = orc_alloc_scb(host)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (inia100_build_scb(host, scb, cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) orc_release_scb(host, scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) orc_exec_scb(host, scb); /* Start execute SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static DEF_SCSI_QCMD(inia100_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) Function name : inia100_abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) Description : Abort a queued command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) (commands that are on the bus can't be aborted easily)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) Input : host - Pointer to host adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) Output : None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) Return : pSRB - Pointer to SCSI request block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int inia100_abort(struct scsi_cmnd * cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct orc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) host = (struct orc_host *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return inia100_abort_cmd(host, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) Function name : inia100_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) Description : Reset registers, reset a hanging bus and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) kill active and disconnected commands for target w/o soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) Input : host - Pointer to host adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) Output : None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) Return : pSRB - Pointer to SCSI request block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static int inia100_bus_reset(struct scsi_cmnd * cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { /* I need Host Control Block Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct orc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) host = (struct orc_host *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return orc_reset_scsi_bus(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) Function name : inia100_device_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) Description : Reset the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) Input : host - Pointer to host adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) Output : None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) Return : pSRB - Pointer to SCSI request block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int inia100_device_reset(struct scsi_cmnd * cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { /* I need Host Control Block Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct orc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) host = (struct orc_host *) cmd->device->host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return orc_device_reset(host, cmd, scmd_id(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * inia100_scb_handler - interrupt callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * @host: Host causing the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * @scb: SCB the controller returned as needing processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * Perform completion processing on a control block. Do the conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * from host to SCSI midlayer error coding, save any sense data and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * the complete with the midlayer and recycle the scb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct scsi_cmnd *cmd; /* Pointer to SCSI request block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct orc_extended_scb *escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) escb = scb->escb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if ((cmd = (struct scsi_cmnd *) escb->srb) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) printk(KERN_ERR "inia100_scb_handler: SRB pointer is empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) orc_release_scb(host, scb); /* Release SCB for current channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) escb->srb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) switch (scb->hastat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case 0xa: /* Linked command complete without error and linked normally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case 0xb: /* Linked command complete without error interrupt generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) scb->hastat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case 0x11: /* Selection time out-The initiator selection or target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) reselection was not complete within the SCSI Time out period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) scb->hastat = DID_TIME_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) phase sequence was requested by the target. The host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) will generate a SCSI Reset Condition, notifying the host with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) a SCRD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) scb->hastat = DID_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case 0x1a: /* SCB Aborted. 07/21/98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) scb->hastat = DID_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case 0x12: /* Data overrun/underrun-The target attempted to transfer more data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) than was allocated by the Data Length field or the sum of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) Scatter / Gather Data Length fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case 0x13: /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) case 0x16: /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) printk(KERN_DEBUG "inia100: %x %x\n", scb->hastat, scb->tastat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) scb->hastat = DID_ERROR; /* Couldn't find any better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (scb->tastat == 2) { /* Check condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) memcpy((unsigned char *) &cmd->sense_buffer[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) (unsigned char *) &escb->sglist[0], SENSE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) cmd->result = scb->tastat | (scb->hastat << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cmd->scsi_done(cmd); /* Notify system DONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) orc_release_scb(host, scb); /* Release SCB for current channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * inia100_intr - interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * @irqno: Interrupt value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * @devid: Host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * Entry point for IRQ handling. All the real work is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * by orc_interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static irqreturn_t inia100_intr(int irqno, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct Scsi_Host *shost = (struct Scsi_Host *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct orc_host *host = (struct orc_host *)shost->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) irqreturn_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) spin_lock_irqsave(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) res = orc_interrupt(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) spin_unlock_irqrestore(shost->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static struct scsi_host_template inia100_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .proc_name = "inia100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .name = inia100_REVID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .queuecommand = inia100_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .eh_abort_handler = inia100_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .eh_bus_reset_handler = inia100_bus_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .eh_device_reset_handler = inia100_device_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .can_queue = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .this_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .sg_tablesize = SG_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int inia100_probe_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct Scsi_Host *shost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct orc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) unsigned long port, bios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int error = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) unsigned long biosaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) char *bios_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (pci_enable_device(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) printk(KERN_WARNING "Unable to set 32bit DMA "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "on inia100 adapter, ignoring.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) goto out_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) port = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!request_region(port, 256, "inia100")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) printk(KERN_WARNING "inia100: io port 0x%lx, is busy.\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto out_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* <02> read from base address + 0x50 offset to get the bios value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) bios = inw(port + 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) shost = scsi_host_alloc(&inia100_template, sizeof(struct orc_host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (!shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto out_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) host = (struct orc_host *)shost->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) host->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) host->base = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) host->BIOScfg = bios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) spin_lock_init(&host->allocation_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Get total memory needed for SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) sz = ORC_MAXQUEUE * sizeof(struct orc_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) host->scb_virt = dma_alloc_coherent(&pdev->dev, sz, &host->scb_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!host->scb_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) printk("inia100: SCB memory allocation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) goto out_host_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Get total memory needed for ESCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) sz = ORC_MAXQUEUE * sizeof(struct orc_extended_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) host->escb_virt = dma_alloc_coherent(&pdev->dev, sz, &host->escb_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!host->escb_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) printk("inia100: ESCB memory allocation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) goto out_free_scb_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) biosaddr = host->BIOScfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) biosaddr = (biosaddr << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) bios_phys = phys_to_virt(biosaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (init_orchid(host)) { /* Initialize orchid chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) printk("inia100: initial orchid fail!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) goto out_free_escb_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) shost->io_port = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) shost->n_io_port = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) shost->can_queue = ORC_MAXQUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) shost->unique_id = shost->io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) shost->max_id = host->max_targets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) shost->max_lun = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) shost->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) shost->this_id = host->scsi_id; /* Assign HCS index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) shost->sg_tablesize = TOTAL_SG_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Initial orc chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) error = request_irq(pdev->irq, inia100_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) "inia100", shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) printk(KERN_WARNING "inia100: unable to get irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto out_free_escb_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pci_set_drvdata(pdev, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) error = scsi_add_host(shost, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) scsi_scan_host(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) free_irq(shost->irq, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) out_free_escb_array:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ORC_MAXQUEUE * sizeof(struct orc_extended_scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) host->escb_virt, host->escb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) out_free_scb_array:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ORC_MAXQUEUE * sizeof(struct orc_scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) host->scb_virt, host->scb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) out_host_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) out_release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) release_region(port, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) out_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static void inia100_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct Scsi_Host *shost = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct orc_host *host = (struct orc_host *)shost->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) scsi_remove_host(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) free_irq(shost->irq, shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ORC_MAXQUEUE * sizeof(struct orc_extended_scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) host->escb_virt, host->escb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ORC_MAXQUEUE * sizeof(struct orc_scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) host->scb_virt, host->scb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) release_region(shost->io_port, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) scsi_host_put(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static struct pci_device_id inia100_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {PCI_VENDOR_ID_INIT, 0x1060, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) MODULE_DEVICE_TABLE(pci, inia100_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct pci_driver inia100_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .name = "inia100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .id_table = inia100_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .probe = inia100_probe_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .remove = inia100_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) module_pci_driver(inia100_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) MODULE_DESCRIPTION("Initio A100U2W SCSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) MODULE_AUTHOR("Initio Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) MODULE_LICENSE("Dual BSD/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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