^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NCR 5380 defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 1993, Drew Eckhardt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Visionary Computing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (Unix consulting and custom programming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * drew@colorado.edu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * +1 (303) 666-5836
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * For more information, please consult
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * NCR 5380 Family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * SCSI Protocol Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Databook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NCR Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 1635 Aeroplaza Drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Colorado Springs, CO 80916
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 1+ (719) 578-3400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 1+ (800) 334-5454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef NCR5380_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NCR5380_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_dbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_eh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi_transport_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NDEBUG_ARBITRATION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NDEBUG_AUTOSENSE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NDEBUG_DMA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NDEBUG_HANDSHAKE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NDEBUG_INFORMATION 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NDEBUG_INIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NDEBUG_INTR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NDEBUG_LINKED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NDEBUG_MAIN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NDEBUG_NO_DATAOUT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NDEBUG_NO_WRITE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NDEBUG_PIO 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NDEBUG_PSEUDO_DMA 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NDEBUG_QUEUES 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NDEBUG_RESELECTION 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NDEBUG_SELECTION 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NDEBUG_USLEEP 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NDEBUG_LAST_BYTE_SENT 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NDEBUG_RESTART_SELECT 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NDEBUG_EXTENDED 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NDEBUG_C400_PREAD 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NDEBUG_C400_PWRITE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NDEBUG_LISTS 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NDEBUG_ABORT 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NDEBUG_TAGS 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NDEBUG_MERGING 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NDEBUG_ANY 0xFFFFFFFFUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The contents of the OUTPUT DATA register are asserted on the bus when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * either arbitration is occurring or the phase-indicating signals (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * bit in the INITIATOR COMMAND register is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CURRENT_SCSI_DATA_REG 0 /* ro same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define INITIATOR_COMMAND_REG 1 /* rw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ICR_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MODE_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * transfer, causing the chip to hog the bus. You probably don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MR_TARGET 0x40 /* rw target mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MR_ARBITRATE 0x01 /* rw start arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MR_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TARGET_COMMAND_REG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STATUS_REG 4 /* ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Note : a set bit indicates an active signal, driven by us or another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SR_RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SR_BSY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SR_REQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SR_MSG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SR_CD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SR_IO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SR_SEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SR_DBP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Setting a bit in this register will cause an interrupt to be generated when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * BSY is false and SEL true and this bit is asserted on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SELECT_ENABLE_REG 4 /* wo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BUS_AND_STATUS_REG 5 /* ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BASR_ATN 0x02 /* ro BUS status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BASR_ACK 0x01 /* ro BUS status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Write any value to this register to start a DMA send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define START_DMA_SEND_REG 5 /* wo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Used in DMA transfer mode, data is latched from the SCSI bus on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * the falling edge of REQ (ini) or ACK (tgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define INPUT_DATA_REG 6 /* ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Write any value to this register to start a DMA receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Read this register to clear interrupt conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Write any value to this register to start an ini mode DMA receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* NCR 53C400(A) Control Status Register bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CSR_RESET 0x80 /* wo Resets 53c400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CSR_BASE CSR_53C80_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Note : PHASE_* macros are based on the values of the STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PHASE_DATAOUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PHASE_DATAIN SR_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PHASE_CMDOUT SR_CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PHASE_STATIN (SR_CD | SR_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PHASE_MSGOUT (SR_MSG | SR_CD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PHASE_UNKNOWN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Convert status register phase to something we can use to set phase in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * the target register so we can get phase mismatch interrupts on DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifndef NO_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define NO_IRQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FLAG_DMA_FIXUP 1 /* Use DMA errata workarounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct NCR5380_hostdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) NCR5380_implementation_fields; /* Board-specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 __iomem *io; /* Remapped 5380 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 __iomem *pdma_io; /* Remapped PDMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long poll_loops; /* Register polling limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spinlock_t lock; /* Protects this struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct scsi_cmnd *connected; /* Currently connected cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct list_head disconnected; /* Waiting for reconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct Scsi_Host *host; /* SCSI host backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct workqueue_struct *work_q; /* SCSI host work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct work_struct main_task; /* Work item for main loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int flags; /* Board-specific quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int dma_len; /* Requested length of DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int read_overruns; /* Transfer size reduction for DMA erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long io_port; /* Device IO port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long base; /* Device base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct list_head unissued; /* Waiting to be issued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct scsi_cmnd *selecting; /* Cmnd to be connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct list_head autosense; /* Priority cmnd queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct scsi_cmnd *sensing; /* Cmnd needing autosense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct scsi_eh_save ses; /* Cmnd state saved for EH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned char busy[8]; /* Index = target, bit = lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned char id_mask; /* 1 << Host ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned char id_higher_mask; /* All bits above id_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned char last_message; /* Last Message Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long region_size; /* Size of address/port range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) char info[168]; /* Host banner message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct NCR5380_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define NCR5380_CMD_SIZE (sizeof(struct NCR5380_cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define NCR5380_PIO_CHUNK_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define NCR5380_REG_POLL_TIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ((struct scsi_cmnd *)ncmd_ptr) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #ifndef NDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define NDEBUG (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define dprintk(flg, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) do { if ((NDEBUG) & (flg)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define dsprintk(flg, host, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) do { if ((NDEBUG) & (flg)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #if NDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define NCR5380_dprint(flg, arg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define NCR5380_dprint_phase(flg, arg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void NCR5380_print_phase(struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void NCR5380_print(struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define NCR5380_dprint(flg, arg) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define NCR5380_dprint_phase(flg, arg) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int NCR5380_init(struct Scsi_Host *instance, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void NCR5380_exit(struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void NCR5380_information_transfer(struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static irqreturn_t NCR5380_intr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void NCR5380_main(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const char *NCR5380_info(struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void NCR5380_reselect(struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int NCR5380_poll_politely2(struct NCR5380_hostdata *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int, u8, u8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int, u8, u8, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int reg, u8 bit, u8 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((NCR5380_read(reg) & bit) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return NCR5380_poll_politely2(hostdata, reg, bit, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) reg, bit, val, wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int NCR5380_dma_send_setup(struct NCR5380_hostdata *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned char *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned char *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int NCR5380_dma_residual(struct NCR5380_hostdata *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned char *data, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif /* NCR5380_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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