^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Linux Driver for BusLogic MultiMaster and FlashPoint SCSI Host Adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright 1995-1998 by Leonard N. Zubkoff <lnz@dandelion.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) The author respectfully requests that any modifications to this software be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) sent directly to him for evaluation and testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Special thanks to Wayne Yen, Jin-Lon Hon, and Alex Win of BusLogic, whose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) advice has been invaluable, to David Gentzel, for writing the original Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) BusLogic driver, and to Paul Gortmaker, for being such a dedicated test site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Finally, special thanks to Mylex/BusLogic for making the FlashPoint SCCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Manager available as freely redistributable source code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef _BUSLOGIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _BUSLOGIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef PACKED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PACKED __attribute__((packed))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Define the maximum number of BusLogic Host Adapters supported by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BLOGIC_MAX_ADAPTERS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Define the maximum number of Target Devices supported by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BLOGIC_MAXDEV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Define the maximum number of Scatter/Gather Segments used by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) For optimal performance, it is important that this limit be at least as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) large as the largest single request generated by the I/O Subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BLOGIC_SG_LIMIT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Define the maximum, maximum automatic, minimum automatic, and default Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Depth to allow for Target Devices depending on whether or not they support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Tagged Queuing and whether or not ISA Bounce Buffers are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BLOGIC_MAX_TAG_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BLOGIC_MAX_AUTO_TAG_DEPTH 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BLOGIC_MIN_AUTO_TAG_DEPTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BLOGIC_TAG_DEPTH_BB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BLOGIC_UNTAG_DEPTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BLOGIC_UNTAG_DEPTH_BB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Define the default amount of time in seconds to wait between a Host Adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Hard Reset which initiates a SCSI Bus Reset and issuing any SCSI commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Some SCSI devices get confused if they receive SCSI commands too soon after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) a SCSI Bus Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BLOGIC_BUS_SETTLE_TIME 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Define the maximum number of Mailboxes that should be used for MultiMaster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Host Adapters. This number is chosen to be larger than the maximum Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Adapter Queue Depth and small enough so that the Host Adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) does not cross an allocation block size boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BLOGIC_MAX_MAILBOX 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Define the number of CCBs that should be allocated as a group to optimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Kernel memory allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BLOGIC_CCB_GRP_ALLOCSIZE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Define the Host Adapter Line and Message Buffer Sizes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BLOGIC_LINEBUF_SIZE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BLOGIC_MSGBUF_SIZE 9700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) Define the Driver Message Levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum blogic_msglevel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BLOGIC_ANNOUNCE_LEVEL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BLOGIC_INFO_LEVEL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) BLOGIC_NOTICE_LEVEL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BLOGIC_WARN_LEVEL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) BLOGIC_ERR_LEVEL = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static char *blogic_msglevelmap[] = { KERN_NOTICE, KERN_NOTICE, KERN_NOTICE, KERN_WARNING, KERN_ERR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Define Driver Message macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define blogic_announce(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) blogic_msg(BLOGIC_ANNOUNCE_LEVEL, format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define blogic_info(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) blogic_msg(BLOGIC_INFO_LEVEL, format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define blogic_notice(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) blogic_msg(BLOGIC_NOTICE_LEVEL, format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define blogic_warn(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) blogic_msg(BLOGIC_WARN_LEVEL, format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define blogic_err(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) blogic_msg(BLOGIC_ERR_LEVEL, format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Define the types of BusLogic Host Adapters that are supported and the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) of I/O Addresses required by each type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum blogic_adapter_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) BLOGIC_MULTIMASTER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BLOGIC_FLASHPOINT = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BLOGIC_MULTIMASTER_ADDR_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BLOGIC_FLASHPOINT_ADDR_COUNT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int blogic_adapter_addr_count[3] = { 0, BLOGIC_MULTIMASTER_ADDR_COUNT, BLOGIC_FLASHPOINT_ADDR_COUNT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) Define macros for testing the Host Adapter Type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_SCSI_FLASHPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define blogic_multimaster_type(adapter) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (adapter->adapter_type == BLOGIC_MULTIMASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define blogic_flashpoint_type(adapter) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (adapter->adapter_type == BLOGIC_FLASHPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define blogic_multimaster_type(adapter) (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define blogic_flashpoint_type(adapter) (false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Define the possible Host Adapter Bus Types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum blogic_adapter_bus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) BLOGIC_UNKNOWN_BUS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) BLOGIC_ISA_BUS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) BLOGIC_EISA_BUS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BLOGIC_PCI_BUS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) BLOGIC_VESA_BUS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BLOGIC_MCA_BUS = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static char *blogic_adapter_busnames[] = { "Unknown", "ISA", "EISA", "PCI", "VESA", "MCA" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static enum blogic_adapter_bus_type blogic_adater_bus_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BLOGIC_VESA_BUS, /* BT-4xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BLOGIC_ISA_BUS, /* BT-5xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BLOGIC_MCA_BUS, /* BT-6xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) BLOGIC_EISA_BUS, /* BT-7xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BLOGIC_UNKNOWN_BUS, /* BT-8xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BLOGIC_PCI_BUS /* BT-9xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) Define the possible Host Adapter BIOS Disk Geometry Translations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum blogic_bios_diskgeometry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BLOGIC_BIOS_NODISK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BLOGIC_BIOS_DISK64x32 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) BLOGIC_BIOS_DISK128x32 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) BLOGIC_BIOS_DISK255x63 = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) Define a 10^18 Statistics Byte Counter data type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct blogic_byte_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int billions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) Define the structure for I/O Address and Bus Probing Information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct blogic_probeinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum blogic_adapter_type adapter_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum blogic_adapter_bus_type adapter_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct pci_dev *pci_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned char bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned char irq_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) Define the Probe Options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct blogic_probe_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool noprobe:1; /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bool noprobe_isa:1; /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bool noprobe_pci:1; /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bool nosort_pci:1; /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bool multimaster_first:1; /* Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bool flashpoint_first:1; /* Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bool limited_isa:1; /* Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bool probe330:1; /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bool probe334:1; /* Bit 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool probe230:1; /* Bit 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bool probe234:1; /* Bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bool probe130:1; /* Bit 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bool probe134:1; /* Bit 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) Define the Global Options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct blogic_global_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bool trace_probe:1; /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bool trace_hw_reset:1; /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bool trace_config:1; /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bool trace_err:1; /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) Define the BusLogic SCSI Host Adapter I/O Register Offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define BLOGIC_CNTRL_REG 0 /* WO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define BLOGIC_STATUS_REG 0 /* RO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define BLOGIC_CMD_PARM_REG 1 /* WO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define BLOGIC_DATAIN_REG 1 /* RO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BLOGIC_INT_REG 2 /* RO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BLOGIC_GEOMETRY_REG 3 /* RO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) Define the structure of the write-only Control Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) union blogic_cntrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned char all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned char:4; /* Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bool bus_reset:1; /* Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bool int_reset:1; /* Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bool soft_reset:1; /* Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bool hard_reset:1; /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) Define the structure of the read-only Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) union blogic_stat_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned char all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bool cmd_invalid:1; /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bool rsvd:1; /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bool datain_ready:1; /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bool cmd_param_busy:1; /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bool adapter_ready:1; /* Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bool init_reqd:1; /* Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) bool diag_failed:1; /* Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bool diag_active:1; /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Define the structure of the read-only Interrupt Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) union blogic_int_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned char all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) bool mailin_loaded:1; /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bool mailout_avail:1; /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bool cmd_complete:1; /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bool ext_busreset:1; /* Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned char rsvd:3; /* Bits 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bool int_valid:1; /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) Define the structure of the read-only Geometry Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) union blogic_geo_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned char all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) enum blogic_bios_diskgeometry d0_geo:2; /* Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) enum blogic_bios_diskgeometry d1_geo:2; /* Bits 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned char:3; /* Bits 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bool ext_trans_enable:1; /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) Define the BusLogic SCSI Host Adapter Command Register Operation Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum blogic_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) BLOGIC_TEST_CMP_COMPLETE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) BLOGIC_INIT_MBOX = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) BLOGIC_EXEC_MBOX_CMD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) BLOGIC_EXEC_BIOS_CMD = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) BLOGIC_GET_BOARD_ID = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) BLOGIC_ENABLE_OUTBOX_AVAIL_INT = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BLOGIC_SET_SELECT_TIMEOUT = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BLOGIC_SET_PREEMPT_TIME = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) BLOGIC_SET_TIMEOFF_BUS = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BLOGIC_SET_TXRATE = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) BLOGIC_INQ_DEV0TO7 = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) BLOGIC_INQ_CONFIG = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) BLOGIC_TGT_MODE = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) BLOGIC_INQ_SETUPINFO = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) BLOGIC_WRITE_LOCALRAM = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) BLOGIC_READ_LOCALRAM = 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) BLOGIC_WRITE_BUSMASTER_FIFO = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) BLOGIC_READ_BUSMASTER_FIFO = 0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) BLOGIC_ECHO_CMDDATA = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) BLOGIC_ADAPTER_DIAG = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) BLOGIC_SET_OPTIONS = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) BLOGIC_INQ_DEV8TO15 = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) BLOGIC_INQ_DEV = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) BLOGIC_DISABLE_INT = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) BLOGIC_INIT_EXT_MBOX = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) BLOGIC_EXEC_SCS_CMD = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) BLOGIC_INQ_FWVER_D3 = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) BLOGIC_INQ_FWVER_LETTER = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) BLOGIC_INQ_PCI_INFO = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BLOGIC_INQ_MODELNO = 0x8B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) BLOGIC_INQ_SYNC_PERIOD = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) BLOGIC_INQ_EXTSETUP = 0x8D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) BLOGIC_STRICT_RR = 0x8F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BLOGIC_STORE_LOCALRAM = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) BLOGIC_FETCH_LOCALRAM = 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) BLOGIC_STORE_TO_EEPROM = 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) BLOGIC_LOAD_AUTOSCSICODE = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) BLOGIC_MOD_IOADDR = 0x95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) BLOGIC_SETCCB_FMT = 0x96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) BLOGIC_WRITE_INQBUF = 0x9A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) BLOGIC_READ_INQBUF = 0x9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BLOGIC_FLASH_LOAD = 0xA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) BLOGIC_READ_SCAMDATA = 0xA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BLOGIC_WRITE_SCAMDATA = 0xA9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) Define the Inquire Board ID reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct blogic_board_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned char type; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned char custom_features; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned char fw_ver_digit1; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned char fw_ver_digit2; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) Define the Inquire Configuration reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct blogic_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char:5; /* Byte 0 Bits 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bool dma_ch5:1; /* Byte 0 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bool dma_ch6:1; /* Byte 0 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bool dma_ch7:1; /* Byte 0 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bool irq_ch9:1; /* Byte 1 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool irq_ch10:1; /* Byte 1 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bool irq_ch11:1; /* Byte 1 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool irq_ch12:1; /* Byte 1 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned char:1; /* Byte 1 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bool irq_ch14:1; /* Byte 1 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) bool irq_ch15:1; /* Byte 1 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned char:1; /* Byte 1 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned char id:4; /* Byte 2 Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned char:4; /* Byte 2 Bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) Define the Inquire Setup Information reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct blogic_syncval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned char offset:4; /* Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned char tx_period:3; /* Bits 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bool sync:1; /* Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct blogic_setup_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bool sync:1; /* Byte 0 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) bool parity:1; /* Byte 0 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned char:6; /* Byte 0 Bits 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned char tx_rate; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned char preempt_time; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned char timeoff_bus; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned char mbox_count; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned char mbox_addr[3]; /* Bytes 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct blogic_syncval sync0to7[8]; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned char disconnect_ok0to7; /* Byte 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned char sig; /* Byte 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned char char_d; /* Byte 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned char bus_type; /* Byte 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned char wide_tx_ok0to7; /* Byte 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned char wide_tx_active0to7; /* Byte 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct blogic_syncval sync8to15[8]; /* Bytes 22-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned char disconnect_ok8to15; /* Byte 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned char:8; /* Byte 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned char wide_tx_ok8to15; /* Byte 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned char wide_tx_active8to15; /* Byte 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) Define the Initialize Extended Mailbox request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct blogic_extmbox_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned char mbox_count; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 base_mbox_addr; /* Bytes 1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) Define the Inquire PCI Host Adapter Information reply type. The ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) Compatible I/O Port values are defined here and are also used with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) the Modify I/O Address command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) enum blogic_isa_ioport {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) BLOGIC_IO_330 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) BLOGIC_IO_334 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) BLOGIC_IO_230 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) BLOGIC_IO_234 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) BLOGIC_IO_130 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BLOGIC_IO_134 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) BLOGIC_IO_DISABLE = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) BLOGIC_IO_DISABLE2 = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct blogic_adapter_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) enum blogic_isa_ioport isa_port; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned char irq_ch; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) bool low_term:1; /* Byte 2 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) bool high_term:1; /* Byte 2 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned char:2; /* Byte 2 Bits 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) bool JP1:1; /* Byte 2 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bool JP2:1; /* Byte 2 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bool JP3:1; /* Byte 2 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bool genericinfo_valid:1; /* Byte 2 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned char:8; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) Define the Inquire Extended Setup Information reply structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct blogic_ext_setup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned char bus_type; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned char bios_addr; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned short sg_limit; /* Bytes 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned char mbox_count; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 base_mbox_addr; /* Bytes 5-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned char:2; /* Byte 9 Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool fast_on_eisa:1; /* Byte 9 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned char:3; /* Byte 9 Bits 3-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bool level_int:1; /* Byte 9 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned char:1; /* Byte 9 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned char fw_rev[3]; /* Bytes 10-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bool wide:1; /* Byte 13 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bool differential:1; /* Byte 13 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bool scam:1; /* Byte 13 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bool ultra:1; /* Byte 13 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bool smart_term:1; /* Byte 13 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned char:3; /* Byte 13 Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) Define the Enable Strict Round Robin Mode request type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) enum blogic_rr_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) BLOGIC_AGGRESSIVE_RR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) BLOGIC_STRICT_RR_MODE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) Define the Fetch Host Adapter Local RAM request type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define BLOGIC_BIOS_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define BLOGIC_AUTOSCSI_BASE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct blogic_fetch_localram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned char offset; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned char count; /* Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) Define the Host Adapter Local RAM AutoSCSI structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct blogic_autoscsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned char factory_sig[2]; /* Bytes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned char info_bytes; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned char adapter_type[6]; /* Bytes 3-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned char:8; /* Byte 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) bool floppy:1; /* Byte 10 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bool floppy_sec:1; /* Byte 10 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) bool level_int:1; /* Byte 10 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned char:2; /* Byte 10 Bits 3-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned char systemram_bios:3; /* Byte 10 Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned char dma_ch:7; /* Byte 11 Bits 0-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool dma_autoconf:1; /* Byte 11 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned char irq_ch:7; /* Byte 12 Bits 0-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) bool irq_autoconf:1; /* Byte 12 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned char dma_tx_rate; /* Byte 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned char scsi_id; /* Byte 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bool low_term:1; /* Byte 15 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bool parity:1; /* Byte 15 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bool high_term:1; /* Byte 15 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bool noisy_cable:1; /* Byte 15 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) bool fast_sync_neg:1; /* Byte 15 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) bool reset_enabled:1; /* Byte 15 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bool:1; /* Byte 15 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) bool active_negation:1; /* Byte 15 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned char bus_on_delay; /* Byte 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned char bus_off_delay; /* Byte 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bool bios_enabled:1; /* Byte 18 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bool int19_redir_enabled:1; /* Byte 18 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) bool ext_trans_enable:1; /* Byte 18 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) bool removable_as_fixed:1; /* Byte 18 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bool:1; /* Byte 18 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bool morethan2_drives:1; /* Byte 18 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bool bios_int:1; /* Byte 18 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) bool floptical:1; /* Byte 19 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned short dev_enabled; /* Bytes 19-20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned short wide_ok; /* Bytes 21-22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned short fast_ok; /* Bytes 23-24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned short sync_ok; /* Bytes 25-26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned short discon_ok; /* Bytes 27-28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned short send_start_unit; /* Bytes 29-30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned short ignore_bios_scan; /* Bytes 31-32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned char pci_int_pin:2; /* Byte 33 Bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned char adapter_ioport:2; /* Byte 33 Bits 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) bool strict_rr_enabled:1; /* Byte 33 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) bool vesabus_33mhzplus:1; /* Byte 33 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bool vesa_burst_write:1; /* Byte 33 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bool vesa_burst_read:1; /* Byte 33 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned short ultra_ok; /* Bytes 34-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int:32; /* Bytes 36-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned char:8; /* Byte 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned char autoscsi_maxlun; /* Byte 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) bool:1; /* Byte 42 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bool scam_dominant:1; /* Byte 42 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bool scam_enabled:1; /* Byte 42 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bool scam_lev2:1; /* Byte 42 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned char:4; /* Byte 42 Bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) bool int13_exten:1; /* Byte 43 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) bool:1; /* Byte 43 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bool cd_boot:1; /* Byte 43 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned char:5; /* Byte 43 Bits 3-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned char boot_id:4; /* Byte 44 Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned char boot_ch:4; /* Byte 44 Bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned char force_scan_order:1; /* Byte 45 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned char:7; /* Byte 45 Bits 1-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned short nontagged_to_alt_ok; /* Bytes 46-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned short reneg_sync_on_check; /* Bytes 48-49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned char rsvd[10]; /* Bytes 50-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned char manuf_diag[2]; /* Bytes 60-61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned short cksum; /* Bytes 62-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) Define the Host Adapter Local RAM Auto SCSI Byte 45 structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct blogic_autoscsi_byte45 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned char force_scan_order:1; /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned char:7; /* Bits 1-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) Define the Host Adapter Local RAM BIOS Drive Map Byte structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define BLOGIC_BIOS_DRVMAP 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct blogic_bios_drvmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned char tgt_idbit3:1; /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned char:2; /* Bits 1-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) enum blogic_bios_diskgeometry diskgeom:2; /* Bits 3-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned char tgt_id:3; /* Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) Define the Set CCB Format request type. Extended LUN Format CCBs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) necessary to support more than 8 Logical Units per Target Device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) enum blogic_setccb_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) BLOGIC_LEGACY_LUN_CCB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) BLOGIC_EXT_LUN_CCB = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) Define the Outgoing Mailbox Action Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) enum blogic_action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) BLOGIC_OUTBOX_FREE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) BLOGIC_MBOX_START = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) BLOGIC_MBOX_ABORT = 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) Define the Incoming Mailbox Completion Codes. The MultiMaster Firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) only uses codes 0 - 4. The FlashPoint SCCB Manager has no mailboxes, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) completion codes are stored in the CCB; it only uses codes 1, 2, 4, and 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) enum blogic_cmplt_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) BLOGIC_INBOX_FREE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) BLOGIC_CMD_COMPLETE_GOOD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) BLOGIC_CMD_ABORT_BY_HOST = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) BLOGIC_CMD_NOTFOUND = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) BLOGIC_CMD_COMPLETE_ERROR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) BLOGIC_INVALID_CCB = 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) Define the Command Control Block (CCB) Opcodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) enum blogic_ccb_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) BLOGIC_INITIATOR_CCB = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) BLOGIC_TGT_CCB = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) BLOGIC_INITIATOR_CCB_SG = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) BLOGIC_INITIATOR_CCBB_RESIDUAL = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) BLOGIC_INITIATOR_CCB_SG_RESIDUAL = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) BLOGIC_BDR = 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) Define the CCB Data Direction Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) enum blogic_datadir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) BLOGIC_UNCHECKED_TX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) BLOGIC_DATAIN_CHECKED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) BLOGIC_DATAOUT_CHECKED = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) BLOGIC_NOTX = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) Define the Host Adapter Status Codes. The MultiMaster Firmware does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return status code 0x0C; it uses 0x12 for both overruns and underruns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) enum blogic_adapter_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) BLOGIC_CMD_CMPLT_NORMAL = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) BLOGIC_LINK_CMD_CMPLT = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) BLOGIC_LINK_CMD_CMPLT_FLAG = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) BLOGIC_DATA_UNDERRUN = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) BLOGIC_SELECT_TIMEOUT = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) BLOGIC_DATA_OVERRUN = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) BLOGIC_NOEXPECT_BUSFREE = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) BLOGIC_INVALID_BUSPHASE = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) BLOGIC_INVALID_OUTBOX_CODE = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) BLOGIC_INVALID_CMD_CODE = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) BLOGIC_LINKCCB_BADLUN = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) BLOGIC_BAD_CMD_PARAM = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) BLOGIC_AUTOREQSENSE_FAIL = 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) BLOGIC_TAGQUEUE_REJECT = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BLOGIC_BAD_MSG_RCVD = 0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BLOGIC_HW_FAIL = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BLOGIC_NORESPONSE_TO_ATN = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) BLOGIC_HW_RESET = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) BLOGIC_RST_FROM_OTHERDEV = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) BLOGIC_BAD_RECONNECT = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) BLOGIC_HW_BDR = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) BLOGIC_ABRT_QUEUE = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) BLOGIC_ADAPTER_SW_ERROR = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) BLOGIC_HW_TIMEOUT = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) BLOGIC_PARITY_ERR = 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) Define the SCSI Target Device Status Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) enum blogic_tgt_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) BLOGIC_OP_GOOD = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) BLOGIC_CHECKCONDITION = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) BLOGIC_DEVBUSY = 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) Define the Queue Tag Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) enum blogic_queuetag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) BLOGIC_SIMPLETAG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) BLOGIC_HEADTAG = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) BLOGIC_ORDEREDTAG = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) BLOGIC_RSVDTAG = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) Define the SCSI Command Descriptor Block (CDB).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define BLOGIC_CDB_MAXLEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) Define the Scatter/Gather Segment structure required by the MultiMaster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) Firmware Interface and the FlashPoint SCCB Manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct blogic_sg_seg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u32 segbytes; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 segdata; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) Define the Driver CCB Status Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) enum blogic_ccb_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) BLOGIC_CCB_FREE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) BLOGIC_CCB_ACTIVE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BLOGIC_CCB_COMPLETE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) BLOGIC_CCB_RESET = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) Define the 32 Bit Mode Command Control Block (CCB) structure. The first 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) bytes are defined by and common to both the MultiMaster Firmware and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) FlashPoint SCCB Manager. The next 60 bytes are defined by the FlashPoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SCCB Manager. The remaining components are defined by the Linux BusLogic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) Driver. Extended LUN Format CCBs differ from Legacy LUN Format 32 Bit Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) CCBs only in having the TagEnable and QueueTag fields moved from byte 17 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) byte 1, and the Logical Unit field in byte 17 expanded to 6 bits. In theory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) Extended LUN Format CCBs can support up to 64 Logical Units, but in practice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) many devices will respond improperly to Logical Units between 32 and 63, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) the SCSI-2 specification defines Bit 5 as LUNTAR. Extended LUN Format CCBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) are used by recent versions of the MultiMaster Firmware, as well as by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) FlashPoint SCCB Manager; the FlashPoint SCCB Manager only supports 32 Logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) Units. Since 64 Logical Units are unlikely to be needed in practice, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) since they are problematic for the above reasons, and since limiting them to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 5 bits simplifies the CCB structure definition, this driver only supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 32 Logical Units per Target Device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct blogic_ccb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) MultiMaster Firmware and FlashPoint SCCB Manager Common Portion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) enum blogic_ccb_opcode opcode; /* Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned char:3; /* Byte 1 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) enum blogic_datadir datadir:2; /* Byte 1 Bits 3-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) bool tag_enable:1; /* Byte 1 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) enum blogic_queuetag queuetag:2; /* Byte 1 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned char cdblen; /* Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) unsigned char sense_datalen; /* Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 datalen; /* Bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 data; /* Bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned char:8; /* Byte 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned char:8; /* Byte 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) enum blogic_adapter_status adapter_status; /* Byte 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) enum blogic_tgt_status tgt_status; /* Byte 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned char tgt_id; /* Byte 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned char lun:5; /* Byte 17 Bits 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) bool legacytag_enable:1; /* Byte 17 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) enum blogic_queuetag legacy_tag:2; /* Byte 17 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned char cdb[BLOGIC_CDB_MAXLEN]; /* Bytes 18-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned char:8; /* Byte 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned char:8; /* Byte 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 rsvd_int; /* Bytes 32-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 sensedata; /* Bytes 36-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) FlashPoint SCCB Manager Defined Portion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) void (*callback) (struct blogic_ccb *); /* Bytes 40-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u32 base_addr; /* Bytes 44-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) enum blogic_cmplt_code comp_code; /* Byte 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_SCSI_FLASHPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned char:8; /* Byte 49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u16 os_flags; /* Bytes 50-51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned char private[24]; /* Bytes 52-99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) void *rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) void *rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned char private2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) BusLogic Linux Driver Defined Portion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dma_addr_t allocgrp_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned int allocgrp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) enum blogic_ccb_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned long serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct scsi_cmnd *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct blogic_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct blogic_ccb *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct blogic_ccb *next_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct blogic_sg_seg sglist[BLOGIC_SG_LIMIT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) Define the 32 Bit Mode Outgoing Mailbox structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct blogic_outbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 ccb; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32:24; /* Bytes 4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) enum blogic_action action; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) Define the 32 Bit Mode Incoming Mailbox structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct blogic_inbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 ccb; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) enum blogic_adapter_status adapter_status; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) enum blogic_tgt_status tgt_status; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) unsigned char:8; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) enum blogic_cmplt_code comp_code; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) Define the BusLogic Driver Options structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct blogic_drvr_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned short tagq_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned short tagq_ok_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned short bus_settle_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) unsigned short stop_tgt_inquiry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned char common_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unsigned char qdepth[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) Define the Host Adapter Target Flags structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct blogic_tgt_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) bool tgt_exists:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) bool tagq_ok:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) bool wide_ok:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) bool tagq_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) bool wide_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bool cmd_good:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) bool tgt_info_in:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) Define the Host Adapter Target Statistics structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define BLOGIC_SZ_BUCKETS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct blogic_tgt_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned int cmds_tried;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned int cmds_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int read_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) unsigned int write_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct blogic_byte_count bytesread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct blogic_byte_count byteswritten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned int read_sz_buckets[BLOGIC_SZ_BUCKETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) unsigned int write_sz_buckets[BLOGIC_SZ_BUCKETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned short aborts_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned short aborts_tried;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned short aborts_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) unsigned short bdr_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned short bdr_tried;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) unsigned short bdr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned short adapter_reset_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned short adapter_reset_attempt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned short adapter_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) Define the FlashPoint Card Handle data type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define FPOINT_BADCARD_HANDLE 0xFFFFFFFFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) Define the FlashPoint Information structure. This structure is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) by the FlashPoint SCCB Manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct fpoint_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u32 base_addr; /* Bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) bool present; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned char irq_ch; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) unsigned char scsi_id; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) unsigned char scsi_lun; /* Byte 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u16 fw_rev; /* Bytes 8-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u16 sync_ok; /* Bytes 10-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u16 fast_ok; /* Bytes 12-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u16 ultra_ok; /* Bytes 14-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u16 discon_ok; /* Bytes 16-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u16 wide_ok; /* Bytes 18-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) bool parity:1; /* Byte 20 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) bool wide:1; /* Byte 20 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) bool softreset:1; /* Byte 20 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bool ext_trans_enable:1; /* Byte 20 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) bool low_term:1; /* Byte 20 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) bool high_term:1; /* Byte 20 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) bool report_underrun:1; /* Byte 20 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) bool scam_enabled:1; /* Byte 20 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) bool scam_lev2:1; /* Byte 21 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) unsigned char:7; /* Byte 21 Bits 1-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned char family; /* Byte 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unsigned char bus_type; /* Byte 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned char model[3]; /* Bytes 24-26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) unsigned char relative_cardnum; /* Byte 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) unsigned char rsvd[4]; /* Bytes 28-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 os_rsvd; /* Bytes 32-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned char translation_info[4]; /* Bytes 36-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u32 rsvd2[5]; /* Bytes 40-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 sec_range; /* Bytes 60-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) Define the BusLogic Driver Host Adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct blogic_adapter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct Scsi_Host *scsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct pci_dev *pci_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) enum blogic_adapter_type adapter_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) enum blogic_adapter_bus_type adapter_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned long io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned long pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) unsigned short addr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned char host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned char model[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned char fw_ver[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) unsigned char full_model[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned char bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) unsigned char dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned char irq_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned char dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned char scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) bool irq_acquired:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) bool dma_chan_acquired:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) bool ext_trans_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) bool parity:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) bool reset_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) bool level_int:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) bool wide:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) bool differential:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) bool scam:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) bool ultra:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) bool ext_lun:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) bool terminfo_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) bool low_term:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) bool high_term:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) bool need_bouncebuf:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) bool strict_rr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) bool scam_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) bool scam_lev2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bool adapter_initd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) bool adapter_extreset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bool adapter_intern_err:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bool processing_ccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) volatile bool adapter_cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) unsigned short adapter_sglimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) unsigned short drvr_sglimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned short maxdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned short maxlun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned short mbox_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) unsigned short initccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) unsigned short inc_ccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) unsigned short alloc_ccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned short drvr_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned short adapter_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) unsigned short untag_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned short common_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) unsigned short bus_settle_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) unsigned short sync_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) unsigned short fast_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned short ultra_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) unsigned short wide_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unsigned short discon_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unsigned short tagq_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned short ext_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) unsigned short adapter_intern_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) unsigned short tgt_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned short msgbuflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 bios_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct blogic_drvr_options *drvr_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct fpoint_info fpinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) void *cardhandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct list_head host_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct blogic_ccb *all_ccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct blogic_ccb *free_ccbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct blogic_ccb *firstccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct blogic_ccb *lastccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct blogic_ccb *bdr_pend[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct blogic_tgt_flags tgt_flags[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned char qdepth[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned char sync_period[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned char sync_offset[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) unsigned char active_cmds[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned int cmds_since_rst[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned long last_seqpoint[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) unsigned long last_resettried[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) unsigned long last_resetdone[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct blogic_outbox *first_outbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct blogic_outbox *last_outbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct blogic_outbox *next_outbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct blogic_inbox *first_inbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct blogic_inbox *last_inbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct blogic_inbox *next_inbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct blogic_tgt_stats tgt_stats[BLOGIC_MAXDEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) unsigned char *mbox_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dma_addr_t mbox_space_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned int mbox_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) unsigned long ccb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) char msgbuf[BLOGIC_MSGBUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) Define a structure for the BIOS Disk Parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct bios_diskparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int cylinders;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) Define a structure for the SCSI Inquiry command results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct scsi_inquiry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) unsigned char devtype:5; /* Byte 0 Bits 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) unsigned char dev_qual:3; /* Byte 0 Bits 5-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) unsigned char dev_modifier:7; /* Byte 1 Bits 0-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) bool rmb:1; /* Byte 1 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) unsigned char ansi_ver:3; /* Byte 2 Bits 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned char ecma_ver:3; /* Byte 2 Bits 3-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) unsigned char iso_ver:2; /* Byte 2 Bits 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) unsigned char resp_fmt:4; /* Byte 3 Bits 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) unsigned char:2; /* Byte 3 Bits 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) bool TrmIOP:1; /* Byte 3 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) bool AENC:1; /* Byte 3 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) unsigned char addl_len; /* Byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) unsigned char:8; /* Byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) unsigned char:8; /* Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) bool SftRe:1; /* Byte 7 Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) bool CmdQue:1; /* Byte 7 Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) bool:1; /* Byte 7 Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) bool linked:1; /* Byte 7 Bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) bool sync:1; /* Byte 7 Bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) bool WBus16:1; /* Byte 7 Bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) bool WBus32:1; /* Byte 7 Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) bool RelAdr:1; /* Byte 7 Bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) unsigned char vendor[8]; /* Bytes 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned char product[16]; /* Bytes 16-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) unsigned char product_rev[4]; /* Bytes 32-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) Define functions to provide an abstraction for reading and writing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) Host Adapter I/O Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static inline void blogic_busreset(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) union blogic_cntrl_reg cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) cr.all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) cr.cr.bus_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) outb(cr.all, adapter->io_addr + BLOGIC_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static inline void blogic_intreset(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) union blogic_cntrl_reg cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) cr.all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) cr.cr.int_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) outb(cr.all, adapter->io_addr + BLOGIC_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static inline void blogic_softreset(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) union blogic_cntrl_reg cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) cr.all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) cr.cr.soft_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) outb(cr.all, adapter->io_addr + BLOGIC_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static inline void blogic_hardreset(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) union blogic_cntrl_reg cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) cr.all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) cr.cr.hard_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) outb(cr.all, adapter->io_addr + BLOGIC_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static inline unsigned char blogic_rdstatus(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return inb(adapter->io_addr + BLOGIC_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static inline void blogic_setcmdparam(struct blogic_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) outb(value, adapter->io_addr + BLOGIC_CMD_PARM_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static inline unsigned char blogic_rddatain(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return inb(adapter->io_addr + BLOGIC_DATAIN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static inline unsigned char blogic_rdint(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return inb(adapter->io_addr + BLOGIC_INT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static inline unsigned char blogic_rdgeom(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return inb(adapter->io_addr + BLOGIC_GEOMETRY_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) blogic_execmbox issues an Execute Mailbox Command, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) notifies the Host Adapter that an entry has been made in an Outgoing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) Mailbox.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static inline void blogic_execmbox(struct blogic_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) blogic_setcmdparam(adapter, BLOGIC_EXEC_MBOX_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) blogic_delay waits for Seconds to elapse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static inline void blogic_delay(int seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mdelay(1000 * seconds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) virt_to_32bit_virt maps between Kernel Virtual Addresses and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) 32 bit Kernel Virtual Addresses. This avoids compilation warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) on 64 bit architectures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static inline u32 virt_to_32bit_virt(void *virt_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return (u32) (unsigned long) virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) blogic_inc_count increments counter by 1, stopping at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) 65535 rather than wrapping around to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static inline void blogic_inc_count(unsigned short *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (*count < 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) (*count)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) blogic_addcount increments Byte Counter by Amount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static inline void blogic_addcount(struct blogic_byte_count *bytecount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned int amount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) bytecount->units += amount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (bytecount->units > 999999999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) bytecount->units -= 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) bytecount->billions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) blogic_incszbucket increments the Bucket for Amount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static inline void blogic_incszbucket(unsigned int *cmdsz_buckets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) unsigned int amount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (amount < 8 * 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (amount < 2 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) index = (amount < 1 * 1024 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) index = (amount < 4 * 1024 ? 2 : 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) } else if (amount < 128 * 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (amount < 32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) index = (amount < 16 * 1024 ? 4 : 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) index = (amount < 64 * 1024 ? 6 : 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) index = (amount < 256 * 1024 ? 8 : 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) cmdsz_buckets[index]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) Define the version number of the FlashPoint Firmware (SCCB Manager).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define FLASHPOINT_FW_VER "5.02"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) Define the possible return values from FlashPoint_HandleInterrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define FPOINT_NORMAL_INT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define FPOINT_INTERN_ERR 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define FPOINT_EXT_RESET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) Define prototypes for the forward referenced BusLogic Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) Internal Functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const char *blogic_drvr_info(struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int blogic_qcmd(struct Scsi_Host *h, struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int blogic_diskparam(struct scsi_device *, struct block_device *, sector_t, int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int blogic_slaveconfig(struct scsi_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static void blogic_qcompleted_ccb(struct blogic_ccb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static irqreturn_t blogic_inthandler(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int blogic_resetadapter(struct blogic_adapter *, bool hard_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static void blogic_msg(enum blogic_msglevel, char *, struct blogic_adapter *, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int __init blogic_setup(char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #endif /* _BUSLOGIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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