^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* -*- mode: c; c-basic-offset: 8 -*- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _53C700_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _53C700_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Turn on for general debugging---too verbose for normal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #undef NCR_700_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Debug the tag queues, checking hash queue allocation and deallocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * and search for duplicate tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #undef NCR_700_TAG_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef NCR_700_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DEBUG(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DDEBUG(prefix, sdev, fmt, a...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) sdev_printk(prefix, sdev, fmt, ##a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CDEBUG(prefix, scmd, fmt, a...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) scmd_printk(prefix, scmd, fmt, ##a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DEBUG(x) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* The number of available command slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NCR_700_COMMAND_SLOTS_PER_HOST 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* The maximum number of Scatter Gathers we allow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NCR_700_SG_SEGMENTS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* The maximum number of luns (make this of the form 2^n) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NCR_700_MAX_LUNS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Maximum number of tags the driver ever allows per device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NCR_700_MAX_TAGS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Tag depth the driver starts out with (can be altered in sysfs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NCR_700_DEFAULT_TAGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* This is the default number of commands per LUN in the untagged case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * two is a good value because it means we can have one command active and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * one command fully prepared and waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NCR_700_CMD_PER_LUN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* magic byte identifying an internally generated REQUEST_SENSE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NCR_700_INTERNAL_SENSE_MAGIC 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct NCR_700_Host_Parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* These are the externally used routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct NCR_700_Host_Parameters *, struct device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int NCR_700_release(struct Scsi_Host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) irqreturn_t NCR_700_intr(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum NCR_700_Host_State {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) NCR_700_HOST_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NCR_700_HOST_FREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct NCR_700_SG_List {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* The following is a script fragment to move the buffer onto the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * bus and then link the next fragment or return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCRIPT_MOVE_DATA_IN 0x09000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCRIPT_MOVE_DATA_OUT 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __u32 ins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __u32 pAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCRIPT_NOP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCRIPT_RETURN 0x90080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct NCR_700_Device_Parameters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* space for creating a request sense command. Really, except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * for the annoying SCSI-2 requirement for LUN information in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * cmnd[1], this could be in static storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned char cmnd[MAX_COMMAND_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __u8 depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct scsi_cmnd *current_cmnd; /* currently active command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* The SYNC negotiation sequence looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTIATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * If we get an SDTR reply, work out the SXFER parameters, squirrel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 0:7 SXFER_REG negotiated value for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 8:15 Current queue depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 16 negotiated SYNC flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 17 begin SYNC negotiation flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 18 device supports tag queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return hostdata->cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hostdata->depth = depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline __u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) NCR_700_get_depth(struct scsi_device *SDp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return hostdata->depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return (spi_flags(SDp->sdev_target) & flag) == flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return (spi_flags(SDp->sdev_target) & flag) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spi_flags(SDp->sdev_target) |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spi_flags(SDp->sdev_target) &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum NCR_700_tag_neg_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) NCR_700_START_TAG_NEGOTIATION = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) NCR_700_DURING_TAG_NEGOTIATION = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) NCR_700_FINISHED_TAG_NEGOTIATION = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline enum NCR_700_tag_neg_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) NCR_700_get_tag_neg_state(struct scsi_device *SDp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) NCR_700_set_tag_neg_state(struct scsi_device *SDp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum NCR_700_tag_neg_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* clear the slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct NCR_700_command_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct NCR_700_SG_List *pSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define NCR_700_SLOT_MASK 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NCR_700_SLOT_MAGIC 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define NCR_700_FLAG_AUTOSENSE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __u32 resume_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct scsi_cmnd *cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* The pci_mapped address of the actual command in cmnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dma_addr_t pCmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* if this command is a pci_single mapping, holds the dma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * for later unmapping in the done routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* historical remnant, now used to link free commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct NCR_700_command_slot *ITL_forw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct NCR_700_Host_Parameters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* These must be filled in by the calling driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int clock; /* board clock speed in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void __iomem *base; /* the base for the port (copied to host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __u32 dmode_extra; /* adjustable bus settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __u32 dcntl_extra; /* adjustable bus settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __u32 ctest7_extra; /* adjustable bus settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __u32 differential:1; /* if we are differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_53C700_LE_ON_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* This option is for HP only. Set it if your chip is wired for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * little endian on this platform (which is big endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __u32 force_le_on_be:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __u32 chip710:1; /* set if really a 710 not 700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __u32 burst_length:4; /* set to 0 to disable 710 bursting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __u32 noncoherent:1; /* needs to use non-coherent DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* NOTHING BELOW HERE NEEDS ALTERING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __u32 fast:1; /* if we can alter the SCSI bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) speed (so can negiotiate sync) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int sync_clock; /* The speed of the SYNC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __u32 *script; /* pointer to script location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __u32 pScript; /* physical mem addr of script */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enum NCR_700_Host_State state; /* protected by state lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Note: pScript contains the single consistent block of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * memory. All the msgin, msgout and status are allocated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * this memory too (at separate cache lines). TOTAL_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * represents the total size of this area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MSG_ARRAY_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __u8 *msgout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __u8 *msgin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __u8 *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct NCR_700_command_slot *slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int saved_slot_position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int command_slot_count; /* protected by state lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __u8 tag_negotiated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __u8 reselection_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __u8 min_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Free list, singly linked by ITL_forw elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct NCR_700_command_slot *free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Completion for waited for ops, like reset, abort or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * device reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * NOTE: relies on single threading in the error handler to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * have only one outstanding at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct completion *eh_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * 53C700 Register Interface - the offset from the Selected base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #ifdef CONFIG_53C700_LE_ON_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define bE (hostdata->force_le_on_be ? 0 : 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define bSWAP (hostdata->force_le_on_be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define bEBus (!hostdata->force_le_on_be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #elif defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define bE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define bSWAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #elif defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define bE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define bSWAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifndef bEBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_53C700_BE_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define bEBus 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define bEBus 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* NOTE: These registers are in the LE register space only, the required byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * swapping is done by the NCR_700_{read|write}[b] functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SCNTL0_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define FULL_ARBITRATION 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PARITY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ENABLE_PARITY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AUTO_ATN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SCNTL1_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SLOW_BUS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ENABLE_SELECT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ASSERT_RST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ASSERT_EVEN_PARITY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SDID_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SIEN_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PHASE_MM_INT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define FUNC_COMP_INT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SEL_TIMEOUT_INT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SELECT_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GROSS_ERR_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define UX_DISC_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define RST_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PAR_ERR_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SCID_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SXFER_REG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ASYNC_OPERATION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SODL_REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SOCL_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SFBR_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SIDL_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SBDL_REG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SBCL_REG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* read bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SBCL_IO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*write bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SYNC_DIV_AS_ASYNC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SYNC_DIV_1_0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SYNC_DIV_1_5 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SYNC_DIV_2_0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DSTAT_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ILGL_INST_DETECTED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define WATCH_DOG_INTERRUPT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SCRIPT_INT_RECEIVED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ABORTED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SSTAT0_REG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PARITY_ERROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SCSI_RESET_DETECTED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define UNEXPECTED_DISCONNECT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SCSI_GROSS_ERROR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SELECTED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SELECTION_TIMEOUT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define FUNCTION_COMPLETE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PHASE_MISMATCH 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SSTAT1_REG 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SIDL_REG_FULL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SODR_REG_FULL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SODL_REG_FULL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SSTAT2_REG 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CTEST0_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define BTB_TIMER_DISABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CTEST1_REG 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CTEST2_REG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CTEST3_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CTEST4_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DISABLE_FIFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SLBE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SFWR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define BYTE_LANE0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BYTE_LANE1 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define BYTE_LANE2 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define BYTE_LANE3 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SCSI_ZMODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ZMODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CTEST5_REG 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MASTER_CONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DMA_DIRECTION 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CTEST7_REG 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BURST_DISABLE 0x80 /* 710 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DFP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EVP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CTEST7_TT1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DIFF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CTEST6_REG 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TEMP_REG 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DFIFO_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FLUSH_DMA_FIFO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CLR_FIFO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ISTAT_REG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ABORT_OPERATION 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SOFTWARE_RESET_710 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DMA_INT_PENDING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SCSI_INT_PENDING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CONNECTED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CTEST8_REG 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define LAST_DIS_ENBL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SHORTEN_FILTERING 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ENABLE_ACTIVE_NEGATION 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define GENERATE_RECEIVE_PARITY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLR_FIFO_710 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define FLUSH_DMA_FIFO_710 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CTEST9_REG 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DBC_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DCMD_REG 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DNAD_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define DIEN_REG 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define BUS_FAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ABORT_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define INT_INST_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define WD_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ILGL_INST_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DCNTL_REG 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SOFTWARE_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define COMPAT_700_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SCRPTS_16BITS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define EA_710 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define ASYNC_DIV_2_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ASYNC_DIV_1_5 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ASYNC_DIV_1_0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ASYNC_DIV_3_0 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DMODE_710_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DMODE_700_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define BURST_LENGTH_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define BURST_LENGTH_2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define BURST_LENGTH_4 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BURST_LENGTH_8 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DMODE_FC1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DMODE_FC2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BW16 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MODE_286 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IO_XFER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define FIXED_ADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DSP_REG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DSPS_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Parameters to begin SDTR negotiations. Empirically, I find that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * the 53c700-66 cannot handle an offset >8, so don't change this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define NCR_700_MAX_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Was hoping the max offset would be greater for the 710, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * empirically it seems to be 8 also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define NCR_710_MAX_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define NCR_700_MIN_XFERP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define NCR_710_MIN_XFERP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define script_patch_32(h, script, symbol, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_addr_t da = value; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) (script)[A_##symbol##_used[i]] = bS_to_host(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DEBUG((" script, patching %s at %d to %pad\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #symbol, A_##symbol##_used[i], &da)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define script_patch_32_abs(h, script, symbol, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dma_addr_t da = value; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (script)[A_##symbol##_used[i]] = bS_to_host(da); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DEBUG((" script, patching %s at %d to %pad\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #symbol, A_##symbol##_used[i], &da)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Used for patching the SCSI ID in the SELECT instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define script_patch_ID(h, script, symbol, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val &= 0xff00ffff; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) val |= ((value) & 0xff) << 16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (script)[A_##symbol##_used[i]] = bS_to_host(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #symbol, A_##symbol##_used[i], val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define script_patch_16(h, script, symbol, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val &= 0xffff0000; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) val |= ((value) & 0xffff); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) (script)[A_##symbol##_used[i]] = bS_to_host(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DEBUG((" script, patching short field %s at %d to 0x%x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #symbol, A_##symbol##_used[i], val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static inline __u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) NCR_700_readb(struct Scsi_Host *host, __u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) const struct NCR_700_Host_Parameters *hostdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) = (struct NCR_700_Host_Parameters *)host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ioread8(hostdata->base + (reg^bE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static inline __u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) NCR_700_readl(struct Scsi_Host *host, __u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) const struct NCR_700_Host_Parameters *hostdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) = (struct NCR_700_Host_Parameters *)host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __u32 value = bEBus ? ioread32be(hostdata->base + reg) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ioread32(hostdata->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* sanity check the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BUG_ON((reg & 0x3) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) const struct NCR_700_Host_Parameters *hostdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) = (struct NCR_700_Host_Parameters *)host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) iowrite8(value, hostdata->base + (reg^bE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const struct NCR_700_Host_Parameters *hostdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) = (struct NCR_700_Host_Parameters *)host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* sanity check the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) BUG_ON((reg & 0x3) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bEBus ? iowrite32be(value, hostdata->base + reg):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) iowrite32(value, hostdata->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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