^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) 3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Written By: Adam Radford <aradford@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Modifications By: Joel Jacobson <linux@3ware.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Arnaldo Carvalho de Melo <acme@conectiva.com.br>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Brad Strand <linux@3ware.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Copyright (C) 1999-2010 3ware Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Kernel compatibility By: Andre Hedrick <andre@suse.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Non-Copyright (C) 2000 Andre Hedrick <andre@suse.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Bugs/Comments/Suggestions should be mailed to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) aradford@gmail.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) For more information, goto:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) http://www.lsi.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifndef _3W_XXXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define _3W_XXXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* AEN strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static char *tw_aen_string[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [0x000] = "INFO: AEN queue empty",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [0x001] = "INFO: Soft reset occurred",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [0x002] = "ERROR: Unit degraded: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [0x003] = "ERROR: Controller error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [0x004] = "ERROR: Rebuild failed: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [0x005] = "INFO: Rebuild complete: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [0x006] = "ERROR: Incomplete unit detected: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [0x007] = "INFO: Initialization complete: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [0x008] = "WARNING: Unclean shutdown detected: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [0x009] = "WARNING: ATA port timeout: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [0x00A] = "ERROR: Drive error: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [0x00B] = "INFO: Rebuild started: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [0x00C] = "INFO: Initialization started: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [0x00D] = "ERROR: Logical unit deleted: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [0x00F] = "WARNING: SMART threshold exceeded: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [0x021] = "WARNING: ATA UDMA downgrade: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [0x022] = "WARNING: ATA UDMA upgrade: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [0x023] = "WARNING: Sector repair occurred: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [0x024] = "ERROR: SBUF integrity check failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [0x025] = "ERROR: Lost cached write: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [0x026] = "ERROR: Drive ECC error detected: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [0x027] = "ERROR: DCB checksum error: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [0x028] = "ERROR: DCB unsupported version: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [0x029] = "INFO: Verify started: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [0x02A] = "ERROR: Verify failed: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [0x02B] = "INFO: Verify complete: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [0x02E] = "ERROR: Replacement drive is too small: Port #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [0x030] = "ERROR: Drive not supported: Port #"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Sense key lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static unsigned char tw_sense_table[][4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Codes for newer firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) // ATA Error SCSI Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0x01, 0x03, 0x13, 0x00}, // Address mark not found Address mark not found for data field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0x04, 0x0b, 0x00, 0x00}, // Aborted command Aborted command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {0x10, 0x0b, 0x14, 0x00}, // ID not found Recorded entity not found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error Unrecovered read error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {0x61, 0x04, 0x00, 0x00}, // Device fault Hardware error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {0x84, 0x0b, 0x47, 0x00}, // Data CRC error SCSI parity error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0xd0, 0x0b, 0x00, 0x00}, // Device busy Aborted command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0xd1, 0x0b, 0x00, 0x00}, // Device busy Aborted command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {0x37, 0x02, 0x04, 0x00}, // Unit offline Not ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error Not ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Codes for older firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) // 3ware Error SCSI Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {0x51, 0x0b, 0x00, 0x00} // Unspecified Aborted command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Control register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Status register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TW_STATUS_PCI_PARITY_ERROR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TW_STATUS_QUEUE_ERROR 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TW_STATUS_PCI_ABORT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TW_STATUS_HOST_INTERRUPT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TW_STATUS_COMMAND_INTERRUPT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TW_STATUS_MICROCONTROLLER_READY 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TW_STATUS_ALL_INTERRUPTS 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TW_STATUS_CLEARABLE_BITS 0x00D00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TW_STATUS_EXPECTED_BITS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TW_STATUS_UNEXPECTED_BITS 0x00F00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TW_STATUS_VALID_INTERRUPT 0x00DF0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* RESPONSE QUEUE BIT DEFINITIONS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TW_RESPONSE_ID_MASK 0x00000FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* PCI related defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TW_IO_ADDRESS_RANGE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TW_DEVICE_NAME "3ware Storage Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TW_VENDOR_ID (0x13C1) /* 3ware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TW_DEVICE_ID (0x1000) /* Storage Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TW_DEVICE_ID2 (0x1001) /* 7000 series controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TW_NUMDEVICES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TW_PCI_CLEAR_PCI_ABORT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Command packet opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TW_OP_NOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TW_OP_INIT_CONNECTION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TW_OP_READ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TW_OP_WRITE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TW_OP_VERIFY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TW_OP_GET_PARAM 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TW_OP_SET_PARAM 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TW_OP_SECTOR_INFO 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TW_OP_AEN_LISTEN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TW_OP_FLUSH_CACHE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TW_CMD_PACKET 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TW_CMD_PACKET_WITH_DATA 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Asynchronous Event Notification (AEN) Codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TW_AEN_QUEUE_EMPTY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TW_AEN_SOFT_RESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TW_AEN_DEGRADED_MIRROR 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TW_AEN_CONTROLLER_ERROR 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TW_AEN_REBUILD_FAIL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TW_AEN_REBUILD_DONE 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TW_AEN_QUEUE_FULL 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TW_AEN_TABLE_UNDEFINED 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TW_AEN_APORT_TIMEOUT 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TW_AEN_DRIVE_ERROR 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TW_AEN_SMART_FAIL 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TW_AEN_SBUF_FAIL 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Misc defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TW_ALIGNMENT_6000 64 /* 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TW_ALIGNMENT_7000 4 /* 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TW_MAX_UNITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TW_COMMAND_ALIGNMENT_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TW_INIT_MESSAGE_CREDITS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TW_INIT_COMMAND_PACKET_SIZE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TW_POLL_MAX_RETRIES 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TW_MAX_SGL_LENGTH 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TW_ATA_PASS_SGL_MAX 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TW_Q_LENGTH 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TW_Q_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TW_MAX_SLOT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TW_MAX_PCI_BUSES 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TW_MAX_RESET_TRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TW_UNIT_INFORMATION_TABLE_BASE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TW_MAX_CMDS_PER_LUN 254 /* 254 for io, 1 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) chrdev ioctl, one for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) internal aen post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TW_BLOCK_SIZE 0x200 /* 512-byte blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TW_IOCTL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TW_UNIT_ONLINE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TW_IN_INTR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TW_IN_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TW_IN_CHRDEV_IOCTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TW_MAX_SECTORS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TW_MAX_IOCTL_SECTORS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TW_AEN_WAIT_TIME 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TW_ISR_DONT_COMPLETE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TW_ISR_DONT_RESULT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TW_IOCTL_TIMEOUT 25 /* 25 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TW_IOCTL_CHRDEV_FREE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TW_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Bitmask macros to eliminate bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* opcode: 5, sgloffset: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* reserved_1: 4, response_id: 8, reserved_2: 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* unit: 4, host_id: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TW_UNIT_OUT(x) (x & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) TW_CONTROL_CLEAR_HOST_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) TW_CONTROL_MASK_COMMAND_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) TW_CONTROL_CLEAR_ERROR_STATUS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TW_STATUS_ERRORS(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) (((x & TW_STATUS_PCI_ABORT) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (x & TW_STATUS_PCI_PARITY_ERROR) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (x & TW_STATUS_QUEUE_ERROR) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (x & TW_STATUS_MICROCONTROLLER_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #ifdef TW_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define dprintk(msg...) printk(msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define dprintk(msg...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Scatter Gather List Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) typedef struct TAG_TW_SG_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } TW_SG_Entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) typedef unsigned char TW_Sector[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Command Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) typedef struct TW_Command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned char opcode__sgloffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned char request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned char unit__hostid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Second DWORD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned short block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned short parameter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned short message_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } byte6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 padding; /* pad to 512 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 padding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 response_queue_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 padding[125];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } init_connection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) char version[504];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } ioctl_miniport_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } byte8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } TW_Command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) typedef struct TAG_TW_Ioctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned char opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned short table_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned char parameter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned char parameter_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned char unit_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned char data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } TW_Ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Structure for new chardev ioctls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) typedef struct TAG_TW_New_Ioctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int data_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned char padding [508];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) TW_Command firmware_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) char data_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } TW_New_Ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* GetParam descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned short table_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned char parameter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned char parameter_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned char data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } TW_Param, *PTW_Param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) typedef union TAG_TW_Response_Queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 response_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } TW_Response_Queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) typedef int TW_Cmd_State;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TW_S_INITIAL 0x1 /* Initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TW_S_STARTED 0x2 /* Id in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TW_S_POSTED 0x4 /* Posted to the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TW_S_COMPLETED 0x10 /* Completed by isr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TW_S_FINISHED 0x20 /* I/O completely done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Command header for ATA pass-thru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) typedef struct TAG_TW_Passthru
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned char opcode__sgloffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned char request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned char aport__hostid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned short param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned short features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned short sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned short sector_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned short cylinder_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned short cylinder_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned char drive_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned char command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned char padding[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } TW_Passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) typedef struct TAG_TW_Device_Extension {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long *alignment_virtual_address[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned long alignment_physical_address[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int is_unit_present[TW_MAX_UNITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned long *command_packet_virtual_address[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long command_packet_physical_address[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct pci_dev *tw_pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct scsi_cmnd *srb[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned char free_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned char free_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned char free_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned char pending_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned char pending_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char pending_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) TW_Cmd_State state[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 posted_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 max_posted_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 request_count_marked_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 pending_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 max_pending_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 max_sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 max_sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 aen_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct mutex ioctl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned short aen_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned char aen_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned char aen_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) volatile long flags; /* long req'd for set_bit --RR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int reset_print;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) volatile int chrdev_request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) wait_queue_head_t ioctl_wqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } TW_Device_Extension;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif /* _3W_XXXX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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