^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) 3w-sas.h -- LSI 3ware SAS/SATA-RAID Controller device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Written By: Adam Radford <aradford@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2009 LSI Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Bugs/Comments/Suggestions should be mailed to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) aradford@gmail.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef _3W_SAS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define _3W_SAS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* AEN severity table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static char *twl_aen_severity_table[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "None", "ERROR", "WARNING", "INFO", "DEBUG", NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Liberator register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TWL_STATUS 0x0 /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TWL_HIBDB 0x20 /* Inbound doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TWL_HISTAT 0x30 /* Host interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TWL_HIMASK 0x34 /* Host interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TWL_HOBDB 0x9C /* Outbound doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TWL_HOBDBC 0xA0 /* Outbound doorbell clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TWL_SCRPD3 0xBC /* Scratchpad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TWL_HIBQPL 0xC0 /* Host inbound Q low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TWL_HIBQPH 0xC4 /* Host inbound Q high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TWL_HOBQPL 0xC8 /* Host outbound Q low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TWL_HOBQPH 0xCC /* Host outbound Q high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TWL_HISTATUS_VALID_INTERRUPT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TWL_HISTATUS_ATTENTION_INTERRUPT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TWL_HISTATUS_RESPONSE_INTERRUPT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TWL_STATUS_OVERRUN_SUBMIT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TWL_ISSUE_SOFT_RESET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TWL_CONTROLLER_READY 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TWL_DOORBELL_CONTROLLER_ERROR 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TWL_DOORBELL_ATTENTION_INTERRUPT 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TWL_PULL_MODE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Command packet opcodes used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TW_OP_INIT_CONNECTION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TW_OP_GET_PARAM 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TW_OP_SET_PARAM 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TW_OP_EXECUTE_SCSI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Asynchronous Event Notification (AEN) codes used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TW_AEN_QUEUE_EMPTY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TW_AEN_SOFT_RESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TW_AEN_SYNC_TIME_WITH_HOST 0x031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TW_AEN_SEVERITY_ERROR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TW_AEN_SEVERITY_DEBUG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TW_AEN_NOT_RETRIEVED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Command state defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TW_S_INITIAL 0x1 /* Initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TW_S_STARTED 0x2 /* Id in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TW_S_POSTED 0x4 /* Posted to the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TW_S_COMPLETED 0x8 /* Completed by isr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TW_S_FINISHED 0x10 /* I/O completely done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Compatibility defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TW_9750_ARCH_ID 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TW_CURRENT_DRIVER_SRL 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TW_CURRENT_DRIVER_BUILD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TW_CURRENT_DRIVER_BRANCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Misc defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TW_SECTOR_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TW_MAX_UNITS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TW_INIT_MESSAGE_CREDITS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TW_INIT_COMMAND_PACKET_SIZE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TW_EXTENDED_INIT_CONNECT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TW_BASE_FW_SRL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TW_BASE_FW_BRANCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TW_BASE_FW_BUILD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TW_Q_LENGTH 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TW_Q_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TW_MAX_SLOT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TW_MAX_RESET_TRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TW_MAX_CMDS_PER_LUN 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TW_MAX_AEN_DRAIN 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TW_IN_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TW_USING_MSI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TW_IN_ATTENTION_LOOP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TW_MAX_SECTORS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TW_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TW_IOCTL_CHRDEV_FREE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TW_COMMAND_OFFSET 128 /* 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TW_VERSION_TABLE 0x0402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TW_TIMEKEEP_TABLE 0x040A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TW_INFORMATION_TABLE 0x0403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TW_PARAM_FWVER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TW_PARAM_FWVER_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TW_PARAM_BIOSVER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TW_PARAM_BIOSVER_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TW_PARAM_MODEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TW_PARAM_MODEL_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TW_PARAM_PHY_SUMMARY_TABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TW_PARAM_PHYCOUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TW_PARAM_PHYCOUNT_LENGTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 // Used by smartmontools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TW_ALLOCATION_LENGTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TW_SENSE_DATA_LENGTH 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TW_ERROR_INVALID_FIELD_IN_CDB 0x10d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TW_ERROR_UNIT_OFFLINE 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TW_DRIVER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifndef PCI_DEVICE_ID_3WARE_9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCI_DEVICE_ID_3WARE_9750 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Bitmask macros to eliminate bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* opcode: 5, reserved: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TW_OP_OUT(x) (x & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* opcode: 5, sgloffset: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* severity: 3, reserved: 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TW_SEV_OUT(x) (x & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* not_mfa: 1, reserved: 7, status: 8, request_id: 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TW_RESID_OUT(x) ((x >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TW_NOTMFA_OUT(x) (x & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* request_id: 12, lun: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TW_LUN_OUT(lun) ((lun >> 12) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Register access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TWL_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TWL_HOBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TWL_HOBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TWL_HOBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TWL_HOBDBC_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDBC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TWL_HIMASK_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TWL_HISTAT_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HISTAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TWL_HIBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TWL_HIBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TWL_HIBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBDB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TWL_SCRPD3_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_SCRPD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TWL_MASK_INTERRUPTS(x) (writel(~0, TWL_HIMASK_REG_ADDR(tw_dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TWL_UNMASK_INTERRUPTS(x) (writel(~TWL_HISTATUS_VALID_INTERRUPT, TWL_HIMASK_REG_ADDR(tw_dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TWL_CLEAR_DB_INTERRUPT(x) (writel(~0, TWL_HOBDBC_REG_ADDR(tw_dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TWL_SOFT_RESET(x) (writel(TWL_ISSUE_SOFT_RESET, TWL_HIBDB_REG_ADDR(tw_dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TW_PRINTK(h,a,b,c) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) printk(KERN_WARNING "3w-sas: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) printk(KERN_WARNING "3w-sas: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TW_MAX_LUNS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 6 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TW_LIBERATOR_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 46 : 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TW_LIBERATOR_MAX_SGL_LENGTH_OLD (sizeof(dma_addr_t) > 4 ? 47 : 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TW_PADDING_LENGTH_LIBERATOR 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TW_PADDING_LENGTH_LIBERATOR_OLD 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* SGL entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) typedef struct TAG_TW_SG_Entry_ISO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dma_addr_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dma_addr_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } TW_SG_Entry_ISO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Old Command Packet with ISO SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) typedef struct TW_Command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned char opcode__sgloffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned char request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned char unit__hostid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Second DWORD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned short block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned short parameter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } byte6_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) TW_SG_Entry_ISO sgl[TW_LIBERATOR_MAX_SGL_LENGTH_OLD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char padding[TW_PADDING_LENGTH_LIBERATOR_OLD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) TW_SG_Entry_ISO sgl[TW_LIBERATOR_MAX_SGL_LENGTH_OLD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned char padding2[TW_PADDING_LENGTH_LIBERATOR_OLD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } byte8_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } TW_Command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* New Command Packet with ISO SGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) typedef struct TAG_TW_Command_Apache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char opcode__reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned char unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned short request_id__lunl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned char sgl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned short sgl_entries__lunh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned char cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TW_SG_Entry_ISO sg_list[TW_LIBERATOR_MAX_SGL_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned char padding[TW_PADDING_LENGTH_LIBERATOR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } TW_Command_Apache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* New command packet header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) typedef struct TAG_TW_Command_Apache_Header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned char sense_data[TW_SENSE_DATA_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) char reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned short error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned char padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned char severity__reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } status_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned char err_specific_desc[98];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned char size_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned short request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned char size_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } header_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } TW_Command_Apache_Header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* This struct is a union of the 2 command packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) typedef struct TAG_TW_Command_Full {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) TW_Command_Apache_Header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) TW_Command oldcommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) TW_Command_Apache newcommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } TW_Command_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Initconnection structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) typedef struct TAG_TW_Initconnect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned char opcode__reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned char request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned char res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned short message_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned short fw_srl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned short fw_arch_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned short fw_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned short fw_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } TW_Initconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Event info structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) typedef struct TAG_TW_Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int time_stamp_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned short aen_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned char severity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned char retrieved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned char repeat_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned char parameter_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned char parameter_data[98];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } TW_Event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) typedef struct TAG_TW_Ioctl_Driver_Command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int control_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int unique_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int os_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } TW_Ioctl_Driver_Command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) typedef struct TAG_TW_Ioctl_Apache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) TW_Ioctl_Driver_Command driver_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) char padding[488];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) TW_Command_Full firmware_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) char data_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } TW_Ioctl_Buf_Apache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* GetParam descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned short table_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned short parameter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned short parameter_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned short actual_parameter_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned char data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } TW_Param_Apache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Compatibility information structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) typedef struct TAG_TW_Compatibility_Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) char driver_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned short working_srl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned short working_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned short working_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned short driver_srl_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned short driver_branch_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned short driver_build_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned short driver_srl_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned short driver_branch_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned short driver_build_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned short fw_on_ctlr_srl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned short fw_on_ctlr_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned short fw_on_ctlr_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } TW_Compatibility_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) typedef struct TAG_TW_Device_Extension {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long *generic_buffer_virt[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dma_addr_t generic_buffer_phys[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) TW_Command_Full *command_packet_virt[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dma_addr_t command_packet_phys[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) TW_Command_Apache_Header *sense_buffer_virt[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dma_addr_t sense_buffer_phys[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct pci_dev *tw_pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct scsi_cmnd *srb[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned char free_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned char free_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned char free_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int state[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int posted_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int max_posted_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned int max_sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int max_sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int aen_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) TW_Event *event_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned char error_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int error_sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int chrdev_request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) wait_queue_head_t ioctl_wqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mutex ioctl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) TW_Compatibility_Info tw_compat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) char online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } TW_Device_Extension;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #endif /* _3W_SAS_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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