^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) 3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Written By: Adam Radford <aradford@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Modifications By: Tom Couch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (C) 2004-2009 Applied Micro Circuits Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Copyright (C) 2010 LSI Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Bugs/Comments/Suggestions should be mailed to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) aradford@gmail.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef _3W_9XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define _3W_9XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* AEN string type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) typedef struct TAG_twa_message_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) char* text;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } twa_message_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* AEN strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static twa_message_type twa_aen_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {0x0000, "AEN queue empty"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {0x0001, "Controller reset occurred"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {0x0002, "Degraded unit detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {0x0003, "Controller error occurred"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {0x0004, "Background rebuild failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {0x0005, "Background rebuild done"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {0x0006, "Incomplete unit detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {0x0007, "Background initialize done"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {0x0008, "Unclean shutdown detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {0x0009, "Drive timeout detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {0x000A, "Drive error detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {0x000B, "Rebuild started"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {0x000C, "Background initialize started"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {0x000D, "Entire logical unit was deleted"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {0x000E, "Background initialize failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {0x000F, "SMART attribute exceeded threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {0x0010, "Power supply reported AC under range"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {0x0011, "Power supply reported DC out of range"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0x0012, "Power supply reported a malfunction"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {0x0013, "Power supply predicted malfunction"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {0x0014, "Battery charge is below threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {0x0015, "Fan speed is below threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {0x0016, "Temperature sensor is above threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {0x0017, "Power supply was removed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {0x0018, "Power supply was inserted"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {0x0019, "Drive was removed from a bay"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {0x001A, "Drive was inserted into a bay"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {0x001B, "Drive bay cover door was opened"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {0x001C, "Drive bay cover door was closed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {0x001D, "Product case was opened"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {0x0020, "Prepare for shutdown (power-off)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {0x0021, "Downgrade UDMA mode to lower speed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {0x0022, "Upgrade UDMA mode to higher speed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {0x0023, "Sector repair completed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {0x0024, "Sbuf memory test failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0x0025, "Error flushing cached write data to array"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0x0026, "Drive reported data ECC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0x0027, "DCB has checksum error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0x0028, "DCB version is unsupported"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0x0029, "Background verify started"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0x002A, "Background verify failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0x002B, "Background verify done"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {0x002C, "Bad sector overwritten during rebuild"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {0x002D, "Background rebuild error on source drive"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {0x002E, "Replace failed because replacement drive too small"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0x002F, "Verify failed because array was never initialized"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0x0030, "Unsupported ATA drive"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {0x0031, "Synchronize host/controller time"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0x0032, "Spare capacity is inadequate for some units"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {0x0033, "Background migration started"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {0x0034, "Background migration failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0x0035, "Background migration done"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0x0036, "Verify detected and fixed data/parity mismatch"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {0x0037, "SO-DIMM incompatible"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {0x0038, "SO-DIMM not detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {0x0039, "Corrected Sbuf ECC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {0x003A, "Drive power on reset detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {0x003B, "Background rebuild paused"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {0x003C, "Background initialize paused"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {0x003D, "Background verify paused"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {0x003E, "Background migration paused"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {0x003F, "Corrupt flash file system detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0x0040, "Flash file system repaired"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0x0041, "Unit number assignments were lost"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0x0042, "Error during read of primary DCB"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0x0043, "Latent error found in backup DCB"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0x00FC, "Recovered/finished array membership update"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0x00FD, "Handler lockup"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0x00FE, "Retrying PCI transfer"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0x00FF, "AEN queue is full"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0xFFFFFFFF, (char*) 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* AEN severity table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static char *twa_aen_severity_table[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "None", "ERROR", "WARNING", "INFO", "DEBUG", (char*) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Error strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static twa_message_type twa_error_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x0100, "SGL entry contains zero data"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x0101, "Invalid command opcode"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x0102, "SGL entry has unaligned address"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x0103, "SGL size does not match command"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x0104, "SGL entry has illegal length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x0105, "Command packet is not aligned"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0106, "Invalid request ID"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0107, "Duplicate request ID"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x0108, "ID not locked"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x0109, "LBA out of range"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x010A, "Logical unit not supported"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x010B, "Parameter table does not exist"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x010C, "Parameter index does not exist"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x010D, "Invalid field in CDB"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x010E, "Specified port has invalid drive"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x010F, "Parameter item size mismatch"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x0110, "Failed memory allocation"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x0111, "Memory request too large"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0112, "Out of memory segments"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x0113, "Invalid address to deallocate"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x0114, "Out of memory"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x0115, "Out of heap"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x0120, "Double degrade"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x0121, "Drive not degraded"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x0122, "Reconstruct error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x0123, "Replace not accepted"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x0124, "Replace drive capacity too small"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x0125, "Sector count not allowed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x0126, "No spares left"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x0127, "Reconstruct error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x0128, "Unit is offline"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x0129, "Cannot update status to DCB"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0130, "Invalid stripe handle"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x0131, "Handle that was not locked"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x0132, "Handle that was not empty"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x0133, "Handle has different owner"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x0140, "IPR has parent"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x0150, "Illegal Pbuf address alignment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x0151, "Illegal Pbuf transfer length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x0152, "Illegal Sbuf address alignment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x0153, "Illegal Sbuf transfer length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x0160, "Command packet too large"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x0161, "SGL exceeds maximum length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x0162, "SGL has too many entries"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x0170, "Insufficient resources for rebuilder"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x0171, "Verify error (data != parity)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x0180, "Requested segment not in directory of this DCB"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x0181, "DCB segment has unsupported version"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x0182, "DCB segment has checksum error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x0183, "DCB support (settings) segment invalid"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x0184, "DCB UDB (unit descriptor block) segment invalid"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0185, "DCB GUID (globally unique identifier) segment invalid"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x01A0, "Could not clear Sbuf"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x01C0, "Flash identify failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x01C1, "Flash out of bounds"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x01C2, "Flash verify error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x01C3, "Flash file object not found"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x01C4, "Flash file already present"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x01C5, "Flash file system full"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x01C6, "Flash file not present"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x01C7, "Flash file size error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x01C8, "Bad flash file checksum"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x01CA, "Corrupt flash file system detected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x01D0, "Invalid field in parameter list"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x01D1, "Parameter list length error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x01D2, "Parameter item is not changeable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x01D3, "Parameter item is not saveable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x0200, "UDMA CRC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x0201, "Internal CRC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x0202, "Data ECC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x0203, "ADP level 1 error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x0204, "Port timeout"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x0205, "Drive power on reset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x0206, "ADP level 2 error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x0207, "Soft reset failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x0208, "Drive not ready"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x0209, "Unclassified port error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x020A, "Drive aborted command"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x0210, "Internal CRC error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x0211, "PCI abort error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x0212, "PCI parity error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x0213, "Port handler error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x0214, "Token interrupt count error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x0215, "Timeout waiting for PCI transfer"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x0216, "Corrected buffer ECC"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x0217, "Uncorrected buffer ECC"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x0230, "Unsupported command during flash recovery"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x0231, "Next image buffer expected"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x0232, "Binary image architecture incompatible"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x0233, "Binary image has no signature"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x0234, "Binary image has bad checksum"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x0235, "Image downloaded overflowed buffer"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x0240, "I2C device not found"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x0241, "I2C transaction aborted"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x0242, "SO-DIMM parameter(s) incompatible using defaults"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x0243, "SO-DIMM unsupported"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x0248, "SPI transfer status error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x0249, "SPI transfer timeout error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x0250, "Invalid unit descriptor size in CreateUnit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x0251, "Unit descriptor size exceeds data buffer in CreateUnit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0252, "Invalid value in CreateUnit descriptor"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0253, "Inadequate disk space to support descriptor in CreateUnit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x0254, "Unable to create data channel for this unit descriptor"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x0255, "CreateUnit descriptor specifies a drive already in use"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x0256, "Unable to write configuration to all disks during CreateUnit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x0257, "CreateUnit does not support this descriptor version"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x0258, "Invalid subunit for RAID 0 or 5 in CreateUnit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x0259, "Too many descriptors in CreateUnit"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x025A, "Invalid configuration specified in CreateUnit descriptor"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x025B, "Invalid LBA offset specified in CreateUnit descriptor"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x025C, "Invalid stripelet size specified in CreateUnit descriptor"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0260, "SMART attribute exceeded threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0xFFFFFFFF, (char*) 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Control register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Status register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TW_STATUS_PCI_PARITY_ERROR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TW_STATUS_QUEUE_ERROR 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TW_STATUS_PCI_ABORT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TW_STATUS_HOST_INTERRUPT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TW_STATUS_COMMAND_INTERRUPT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TW_STATUS_MICROCONTROLLER_READY 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TW_STATUS_EXPECTED_BITS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TW_STATUS_UNEXPECTED_BITS 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TW_STATUS_VALID_INTERRUPT 0x00DF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PCI related defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TW_PCI_CLEAR_PCI_ABORT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Command packet opcodes used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TW_OP_INIT_CONNECTION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TW_OP_GET_PARAM 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TW_OP_SET_PARAM 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TW_OP_EXECUTE_SCSI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TW_OP_DOWNLOAD_FIRMWARE 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TW_OP_RESET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Asynchronous Event Notification (AEN) codes used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TW_AEN_QUEUE_EMPTY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TW_AEN_SOFT_RESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TW_AEN_SYNC_TIME_WITH_HOST 0x031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TW_AEN_SEVERITY_ERROR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TW_AEN_SEVERITY_DEBUG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TW_AEN_NOT_RETRIEVED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TW_AEN_RETRIEVED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Command state defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TW_S_INITIAL 0x1 /* Initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TW_S_STARTED 0x2 /* Id in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TW_S_POSTED 0x4 /* Posted to the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TW_S_COMPLETED 0x10 /* Completed by isr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TW_S_FINISHED 0x20 /* I/O completely done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Compatibility defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TW_9000_ARCH_ID 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TW_CURRENT_DRIVER_SRL 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TW_CURRENT_DRIVER_BUILD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TW_CURRENT_DRIVER_BRANCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Misc defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TW_9550SX_DRAIN_COMPLETED 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TW_SECTOR_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TW_ALIGNMENT_9000 4 /* 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TW_ALIGNMENT_9000_SGL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TW_MAX_UNITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TW_MAX_UNITS_9650SE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TW_INIT_MESSAGE_CREDITS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TW_INIT_COMMAND_PACKET_SIZE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TW_EXTENDED_INIT_CONNECT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TW_BUNDLED_FW_SAFE_TO_FLASH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TW_CTLR_FW_RECOMMENDS_FLASH 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TW_CTLR_FW_COMPATIBLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TW_BASE_FW_SRL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TW_BASE_FW_BRANCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TW_BASE_FW_BUILD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TW_FW_SRL_LUNS_SUPPORTED 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TW_Q_LENGTH 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TW_Q_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TW_MAX_SLOT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TW_MAX_RESET_TRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TW_MAX_CMDS_PER_LUN 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TW_MAX_RESPONSE_DRAIN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TW_MAX_AEN_DRAIN 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TW_IN_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TW_USING_MSI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TW_IN_ATTENTION_LOOP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TW_MAX_SECTORS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TW_AEN_WAIT_TIME 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TW_MAX_CDB_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TW_ISR_DONT_COMPLETE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define TW_ISR_DONT_RESULT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TW_IOCTL_CHRDEV_FREE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TW_COMMAND_OFFSET 128 /* 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TW_VERSION_TABLE 0x0402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TW_TIMEKEEP_TABLE 0x040A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TW_INFORMATION_TABLE 0x0403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TW_PARAM_FWVER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TW_PARAM_FWVER_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TW_PARAM_BIOSVER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TW_PARAM_BIOSVER_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TW_PARAM_PORTCOUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TW_PARAM_PORTCOUNT_LENGTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TW_MAX_SENSE_LENGTH 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TW_EVENT_SOURCE_AEN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TW_EVENT_SOURCE_COMMAND 0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TW_EVENT_SOURCE_PCHIP 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TW_EVENT_SOURCE_DRIVER 0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TW_IOCTL_GET_LAST_EVENT 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TW_IOCTL_GET_FIRST_EVENT 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TW_IOCTL_GET_NEXT_EVENT 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TW_IOCTL_GET_PREVIOUS_EVENT 0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define TW_IOCTL_GET_LOCK 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TW_IOCTL_RELEASE_LOCK 0x107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001 // Not locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003 // No more events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004 // AEN clobber occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TW_IOCTL_ERROR_OS_EFAULT -EFAULT // Bad address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TW_IOCTL_ERROR_OS_EINTR -EINTR // Interrupted system call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define TW_IOCTL_ERROR_OS_EINVAL -EINVAL // Invalid argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define TW_IOCTL_ERROR_OS_ENOMEM -ENOMEM // Out of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define TW_IOCTL_ERROR_OS_ERESTARTSYS -ERESTARTSYS // Restart system call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define TW_IOCTL_ERROR_OS_EIO -EIO // I/O error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TW_IOCTL_ERROR_OS_ENOTTY -ENOTTY // Not a typewriter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TW_IOCTL_ERROR_OS_ENODEV -ENODEV // No such device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TW_ALLOCATION_LENGTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TW_SENSE_DATA_LENGTH 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TW_STATUS_CHECK_CONDITION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define TW_ERROR_UNIT_OFFLINE 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TW_MESSAGE_SOURCE_LINUX_DRIVER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TW_MESSAGE_SOURCE_LINUX_OS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TW_OS TW_MESSAGE_SOURCE_LINUX_OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #ifndef PCI_DEVICE_ID_3WARE_9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PCI_DEVICE_ID_3WARE_9000 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifndef PCI_DEVICE_ID_3WARE_9550SX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PCI_DEVICE_ID_3WARE_9550SX 0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #ifndef PCI_DEVICE_ID_3WARE_9650SE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PCI_DEVICE_ID_3WARE_9650SE 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #ifndef PCI_DEVICE_ID_3WARE_9690SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PCI_DEVICE_ID_3WARE_9690SA 0x1005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Bitmask macros to eliminate bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* opcode: 5, reserved: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define TW_OP_OUT(x) (x & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* opcode: 5, sgloffset: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* severity: 3, reserved: 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define TW_SEV_OUT(x) (x & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* reserved_1: 4, response_id: 8, reserved_2: 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* request_id: 12, lun: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TW_LUN_OUT(lun) ((lun >> 12) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) TW_CONTROL_CLEAR_HOST_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) TW_CONTROL_MASK_COMMAND_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) TW_CONTROL_CLEAR_ERROR_STATUS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TW_PRINTK(h,a,b,c) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define TW_MAX_LUNS(srl) (srl < TW_FW_SRL_LUNS_SUPPORTED ? 1 : 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 5 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Scatter Gather List Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) typedef struct TAG_TW_SG_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dma_addr_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } TW_SG_Entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Command Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) typedef struct TW_Command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned char opcode__sgloffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned char request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned char unit__hostid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Second DWORD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned short block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned short parameter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } byte6_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dma_addr_t padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dma_addr_t padding2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } byte8_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } TW_Command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Command Packet for 9000+ controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) typedef struct TAG_TW_Command_Apache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned char opcode__reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned char unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned short request_id__lunl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned char sgl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned short sgl_entries__lunh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned char cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned char padding[TW_PADDING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } TW_Command_Apache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* New command packet header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) typedef struct TAG_TW_Command_Apache_Header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned char sense_data[TW_SENSE_DATA_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) char reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned short error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned char padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned char severity__reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } status_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned char err_specific_desc[98];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned char size_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned short reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned char size_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } header_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } TW_Command_Apache_Header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* This struct is a union of the 2 command packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) typedef struct TAG_TW_Command_Full {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TW_Command_Apache_Header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) TW_Command oldcommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) TW_Command_Apache newcommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } TW_Command_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Initconnection structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) typedef struct TAG_TW_Initconnect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned char opcode__reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned char request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned char res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned short message_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned short fw_srl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned short fw_arch_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned short fw_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned short fw_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } TW_Initconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Event info structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) typedef struct TAG_TW_Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int time_stamp_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned short aen_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned char severity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned char retrieved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned char repeat_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned char parameter_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned char parameter_data[98];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } TW_Event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) typedef struct TAG_TW_Ioctl_Driver_Command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int control_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int unique_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int os_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned int buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } TW_Ioctl_Driver_Command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) typedef struct TAG_TW_Ioctl_Apache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) TW_Ioctl_Driver_Command driver_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) char padding[488];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) TW_Command_Full firmware_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) char data_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) } TW_Ioctl_Buf_Apache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Lock structure for ioctl get/release lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) typedef struct TAG_TW_Lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned long timeout_msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned long time_remaining_msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned long force_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } TW_Lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* GetParam descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned short table_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned short parameter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned short parameter_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned short actual_parameter_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned char data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) } TW_Param_Apache, *PTW_Param_Apache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) typedef union TAG_TW_Response_Queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u32 response_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } TW_Response_Queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Compatibility information structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) typedef struct TAG_TW_Compatibility_Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) char driver_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned short working_srl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned short working_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned short working_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned short driver_srl_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned short driver_branch_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned short driver_build_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned short driver_srl_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned short driver_branch_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned short driver_build_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned short fw_on_ctlr_srl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned short fw_on_ctlr_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned short fw_on_ctlr_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } TW_Compatibility_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) typedef struct TAG_TW_Device_Extension {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned long *generic_buffer_virt[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dma_addr_t generic_buffer_phys[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) TW_Command_Full *command_packet_virt[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma_addr_t command_packet_phys[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct pci_dev *tw_pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct scsi_cmnd *srb[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned char free_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned char free_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned char free_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned char pending_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned char pending_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned char pending_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int state[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int posted_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int max_posted_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned int pending_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned int max_pending_request_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned int max_sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int sgl_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned int num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned int sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) unsigned int max_sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unsigned int aen_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int reset_print;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) TW_Event *event_queue[TW_Q_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned char error_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned char event_queue_wrapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned int error_sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int ioctl_sem_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ktime_t ioctl_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int chrdev_request_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) wait_queue_head_t ioctl_wqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct mutex ioctl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) char aen_clobber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) TW_Compatibility_Info tw_compat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } TW_Device_Extension;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #endif /* _3W_9XXX_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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