^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 1999 Derrick J Brashear (shadow@dementia.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/openprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define dprintk(x) printk x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define dprintk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct uctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 uctrl_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 uctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 uctrl_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 uctrl_xxx[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ts102_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 card_a_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 card_a_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 card_a_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 card_a_xxx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 card_b_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 card_b_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 card_b_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 card_b_xxx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 uctrl_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 uctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 uctrl_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 uctrl_xxx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 ts102_xxx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Bits for uctrl_intr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Bits for uctrl_stat register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UCTRL_STAT_TXNF_STA 0x02 /* transmit FIFO not full status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UCTRL_STAT_RXNE_STA 0x04 /* receive FIFO not empty status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UCTRL_STAT_RXO_STA 0x08 /* receive FIFO overflow status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static DEFINE_MUTEX(uctrl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char *uctrl_extstatus[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "main power available",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "internal battery attached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "external battery attached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "external VGA attached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "external keyboard attached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "external mouse attached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "lid down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "internal battery currently charging",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "external battery currently charging",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "internal battery currently discharging",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "external battery currently discharging",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Everything required for one transaction with the uctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct uctrl_txn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 inbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 outbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 *inbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 *outbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct uctrl_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 current_temp; /* 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 reset_status; /* 0x0b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 event_status; /* 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 error_status; /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 external_status; /* 0x11, 0x1b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 internal_charge; /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 external_charge; /* 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 control_lcd; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 control_bitport; /* 0x21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 speaker_volume; /* 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 control_tft_brightness; /* 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 control_kbd_repeat_delay; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 control_kbd_repeat_period; /* 0x29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 control_screen_contrast; /* 0x2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum uctrl_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) READ_SERIAL_NUMBER=0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) READ_ETHERNET_ADDRESS=0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) READ_HARDWARE_VERSION=0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) READ_MICROCONTROLLER_VERSION=0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) READ_MAX_TEMPERATURE=0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) READ_MIN_TEMPERATURE=0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) READ_CURRENT_TEMPERATURE=0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) READ_SYSTEM_VARIANT=0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) READ_POWERON_CYCLES=0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) READ_POWERON_SECONDS=0xA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) READ_RESET_STATUS=0xB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) READ_EVENT_STATUS=0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) READ_REAL_TIME_CLOCK=0xD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) READ_EXTERNAL_VGA_PORT=0xE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) READ_ERROR_STATUS=0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) READ_EXTERNAL_STATUS=0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) READ_USER_CONFIGURATION_AREA=0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) READ_MICROCONTROLLER_VOLTAGE=0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) READ_INTERNAL_BATTERY_VOLTAGE=0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) READ_DCIN_VOLTAGE=0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) READ_VERTICAL_POINTER_VOLTAGE=0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) READ_REAL_TIME_CLOCK_ALARM=0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) READ_EVENT_STATUS_NO_RESET=0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) READ_EEPROM_STATUS=0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CONTROL_LCD=0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CONTROL_BITPORT=0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SPEAKER_VOLUME=0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CONTROL_TFT_BRIGHTNESS=0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CONTROL_WATCHDOG=0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CONTROL_FACTORY_EEPROM_AREA=0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CONTROL_TIMEZONE=0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CONTROL_MARK_SPACE_RATIO=0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CONTROL_DIAGNOSTIC_MODE=0x2E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CONTROL_SCREEN_CONTRAST=0x2F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RING_BELL=0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SET_DIAGNOSTIC_STATUS=0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLEAR_KEY_COMBINATION_TABLE=0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PERFORM_SOFTWARE_RESET=0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SET_REAL_TIME_CLOCK=0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RECALIBRATE_POINTING_STICK=0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SET_BELL_FREQUENCY=0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SET_REAL_TIME_CLOCK_ALARM=0x3B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) READ_EEPROM=0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) WRITE_EEPROM=0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) WRITE_TO_STATUS_DISPLAY=0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEFINE_SPECIAL_CHARACTER=0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEFINE_KEY_COMBINATION_ENTRY=0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE_STRING_TABLE_ENTRY=0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_STATUS_SCREEN_DISPLAY=0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PERFORM_EMU_COMMANDS=0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) READ_EMU_REGISTER=0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) WRITE_EMU_REGISTER=0x66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) READ_EMU_RAM=0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) WRITE_EMU_RAM=0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) READ_BQ_REGISTER=0x69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) WRITE_BQ_REGISTER=0x6A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SET_USER_PASSWORD=0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) VERIFY_USER_PASSWORD=0x71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GET_SYSTEM_PASSWORD_KEY=0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) VERIFY_SYSTEM_PASSWORD=0x73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) POWER_OFF=0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) POWER_RESTART=0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct uctrl_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct uctrl_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct uctrl_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } *global_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void uctrl_get_event_status(struct uctrl_driver *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void uctrl_get_external_status(struct uctrl_driver *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) uctrl_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mutex_lock(&uctrl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) uctrl_get_event_status(global_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uctrl_get_external_status(global_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mutex_unlock(&uctrl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static irqreturn_t uctrl_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct file_operations uctrl_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .llseek = no_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .unlocked_ioctl = uctrl_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .open = uctrl_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct miscdevice uctrl_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) UCTRL_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "uctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) &uctrl_fops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Wait for space to write, then write to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define WRITEUCTLDATA(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 0; i < 10000; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dprintk(("write data 0x%02x\n", value)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sbus_writel(value, &driver->regs->uctrl_data); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Wait for something to read, read it, then clear the bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define READUCTLDATA(value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) value = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < 10000; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) udelay(1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) value = sbus_readl(&driver->regs->uctrl_data); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dprintk(("read data 0x%02x\n", value)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int stat, incnt, outcnt, bytecnt, intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) stat = sbus_readl(&driver->regs->uctrl_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) intr = sbus_readl(&driver->regs->uctrl_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sbus_writel(stat, &driver->regs->uctrl_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) incnt = txn->inbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) outcnt = txn->outbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) byte = (txn->opcode << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) WRITEUCTLDATA(byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bytecnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) while (incnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) byte = (txn->inbuf[bytecnt] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) WRITEUCTLDATA(byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) incnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) bytecnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Get the ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) READUCTLDATA(byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dprintk(("ack was %x\n", (byte >> 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bytecnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) while (outcnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) READUCTLDATA(byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) txn->outbuf[bytecnt] = (byte >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dprintk(("set byte to %02x\n", byte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) outcnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bytecnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void uctrl_get_event_status(struct uctrl_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct uctrl_txn txn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 outbits[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) txn.opcode = READ_EVENT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) txn.inbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) txn.outbits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) txn.inbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) txn.outbuf = outbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) uctrl_do_txn(driver, &txn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) driver->status.event_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dprintk(("ev is %x\n", driver->status.event_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void uctrl_get_external_status(struct uctrl_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct uctrl_txn txn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 outbits[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int i, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) txn.opcode = READ_EXTERNAL_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) txn.inbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) txn.outbits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) txn.inbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) txn.outbuf = outbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) uctrl_do_txn(driver, &txn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) driver->status.external_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ((outbits[0] * 256) + (outbits[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dprintk(("ex is %x\n", driver->status.external_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) v = driver->status.external_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) for (i = 0; v != 0; i++, v >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (v & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dprintk(("%s%s", " ", uctrl_extstatus[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dprintk(("\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int uctrl_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct uctrl_driver *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) p = kzalloc(sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) printk(KERN_ERR "uctrl: Unable to allocate device struct.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) p->regs = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) resource_size(&op->resource[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "uctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!p->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) printk(KERN_ERR "uctrl: Unable to map registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) p->irq = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) printk(KERN_ERR "uctrl: Unable to register irq.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) err = misc_register(&uctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) printk(KERN_ERR "uctrl: Unable to register misc device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) op->dev.of_node, p->regs, p->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) uctrl_get_event_status(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uctrl_get_external_status(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_set_drvdata(&op->dev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) global_driver = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) free_irq(p->irq, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int uctrl_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct uctrl_driver *p = dev_get_drvdata(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) misc_deregister(&uctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) free_irq(p->irq, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct of_device_id uctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "uctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_DEVICE_TABLE(of, uctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct platform_driver uctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .name = "uctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .of_match_table = uctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .probe = uctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .remove = uctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) module_platform_driver(uctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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