^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef S390_ISM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define S390_ISM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <net/smc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/pci_insn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UTIL_STR_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Do not use the first word of the DMB bits to ensure 8 byte aligned access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ISM_DMB_WORD_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ISM_DMB_BIT_OFFSET (ISM_DMB_WORD_OFFSET * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ISM_NR_DMBS 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ISM_IDENT_MASK 0x00FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ISM_REG_SBA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ISM_REG_IEQ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ISM_READ_GID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ISM_ADD_VLAN_ID 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ISM_DEL_VLAN_ID 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ISM_SET_VLAN 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ISM_RESET_VLAN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ISM_QUERY_INFO 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISM_QUERY_RGID 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ISM_REG_DMB 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISM_UNREG_DMB 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ISM_SIGNAL_IEQ 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ISM_UNREG_SBA 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ISM_UNREG_IEQ 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ism_req_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct ism_resp_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) union ism_reg_sba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 sba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) union ism_reg_ieq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u64 ieq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u64 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) union ism_read_gid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u64 gid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) union ism_qi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u64 ism_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u64 my_gid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u64 sba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u64 ieq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 ieq_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 dmbs_owned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 dmbs_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 vlan_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 vlan_nr_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 vlan_id[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } __aligned(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) union ism_query_rgid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u64 rgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 vlan_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) union ism_reg_dmb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u64 dmb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 dmb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 sba_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 vlan_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 rgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u64 dmb_tok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) union ism_sig_ieq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u64 rgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 trigger_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 event_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u64 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) union ism_unreg_dmb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u64 dmb_tok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) union ism_cmd_simple {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) union ism_set_vlan_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ism_req_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u64 vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ism_resp_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct ism_eq_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u64 ieq_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 entry_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u64 : 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ism_eq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct ism_eq_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct smcd_event entry[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ism_sba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 s : 1; /* summary bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 e : 1; /* event bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 : 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 dmb_bits[ISM_NR_DMBS / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 dmbe_mask[ISM_NR_DMBS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ism_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct smcd_dev *smcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct ism_sba *sba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dma_addr_t sba_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DECLARE_BITMAP(sba_bitmap, ISM_NR_DMBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ism_eq *ieq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dma_addr_t ieq_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ieq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ISM_CREATE_REQ(dmb, idx, sf, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ((dmb) | (idx) << 24 | (sf) << 23 | (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ism_systemeid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 seid_string[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 serial_number[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 type[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline void __ism_read_cmd(struct ism_dev *ism, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long offset, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct zpci_dev *zdev = to_zpci(ism->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u64 req = ZPCI_CREATE_REQ(zdev->fh, 2, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __zpci_load(data, req, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) offset += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) len -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline void __ism_write_cmd(struct ism_dev *ism, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long offset, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct zpci_dev *zdev = to_zpci(ism->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 req = ZPCI_CREATE_REQ(zdev->fh, 2, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __zpci_store_block(data, req, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline int __ism_move(struct ism_dev *ism, u64 dmb_req, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct zpci_dev *zdev = to_zpci(ism->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return __zpci_store_block(data, req, dmb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif /* S390_ISM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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