Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *    Copyright IBM Corp. 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *    Author(s): Cornelia Huck (cornelia.huck@de.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *		 Martin Schwidefsky (schwidefsky@de.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Status accumulation and basic sense functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/ccwdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "cio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "cio_debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "css.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "ioasm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "io_sch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Check for any kind of channel or interface control check but don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * issue the message for the console device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) ccw_device_msg_control_check(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct subchannel *sch = to_subchannel(cdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	char dbf_text[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (!scsw_is_valid_cstat(&irb->scsw) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	    !(scsw_cstat(&irb->scsw) & (SCHN_STAT_CHN_DATA_CHK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	      SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	CIO_MSG_EVENT(0, "Channel-Check or Interface-Control-Check "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		      "received"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		      " ... device %04x on subchannel 0.%x.%04x, dev_stat "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		      ": %02X sch_stat : %02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		      cdev->private->dev_id.devno, sch->schid.ssid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		      sch->schid.sch_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		      scsw_dstat(&irb->scsw), scsw_cstat(&irb->scsw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	sprintf(dbf_text, "chk%x", sch->schid.sch_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	CIO_TRACE_EVENT(0, dbf_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	CIO_HEX_EVENT(0, irb, sizeof(struct irb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Some paths became not operational (pno bit in scsw is set).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) ccw_device_path_notoper(struct ccw_device *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct subchannel *sch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	sch = to_subchannel(cdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (cio_update_schib(sch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		goto doverify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	CIO_MSG_EVENT(0, "%s(0.%x.%04x) - path(s) %02x are "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		      "not operational \n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		      sch->schid.ssid, sch->schid.sch_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		      sch->schib.pmcw.pnom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	sch->lpm &= ~sch->schib.pmcw.pnom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) doverify:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	cdev->private->flags.doverify = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * Copy valid bits from the extended control word to device irb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) ccw_device_accumulate_ecw(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * Copy extended control bit if it is valid... yes there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * are condition that have to be met for the extended control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * bit to have meaning. Sick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	cdev->private->dma_area->irb.scsw.cmd.ectl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if ((irb->scsw.cmd.stctl & SCSW_STCTL_ALERT_STATUS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	    !(irb->scsw.cmd.stctl & SCSW_STCTL_INTER_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		cdev->private->dma_area->irb.scsw.cmd.ectl = irb->scsw.cmd.ectl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* Check if extended control word is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (!cdev->private->dma_area->irb.scsw.cmd.ectl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Copy concurrent sense / model dependent information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	memcpy(&cdev->private->dma_area->irb.ecw, irb->ecw, sizeof(irb->ecw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Check if extended status word is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) ccw_device_accumulate_esw_valid(struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!irb->scsw.cmd.eswf &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	    (irb->scsw.cmd.stctl == SCSW_STCTL_STATUS_PEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (irb->scsw.cmd.stctl ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			(SCSW_STCTL_INTER_STATUS|SCSW_STCTL_STATUS_PEND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	    !(irb->scsw.cmd.actl & SCSW_ACTL_SUSPENDED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * Copy valid bits from the extended status word to device irb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ccw_device_accumulate_esw(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct irb *cdev_irb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct sublog *cdev_sublog, *sublog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (!ccw_device_accumulate_esw_valid(irb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	cdev_irb = &cdev->private->dma_area->irb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Copy last path used mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	cdev_irb->esw.esw1.lpum = irb->esw.esw1.lpum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Copy subchannel logout information if esw is of format 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (irb->scsw.cmd.eswf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		cdev_sublog = &cdev_irb->esw.esw0.sublog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		sublog = &irb->esw.esw0.sublog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		/* Copy extended status flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		cdev_sublog->esf = sublog->esf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		 * Copy fields that have a meaning for channel data check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		 * channel control check and interface control check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (irb->scsw.cmd.cstat & (SCHN_STAT_CHN_DATA_CHK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				       SCHN_STAT_CHN_CTRL_CHK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				       SCHN_STAT_INTF_CTRL_CHK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			/* Copy ancillary report bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			cdev_sublog->arep = sublog->arep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			/* Copy field-validity-flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			cdev_sublog->fvf = sublog->fvf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			/* Copy storage access code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			cdev_sublog->sacc = sublog->sacc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			/* Copy termination code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			cdev_sublog->termc = sublog->termc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			/* Copy sequence code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			cdev_sublog->seqc = sublog->seqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		/* Copy device status check. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		cdev_sublog->devsc = sublog->devsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* Copy secondary error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		cdev_sublog->serr = sublog->serr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		/* Copy i/o-error alert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		cdev_sublog->ioerr = sublog->ioerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/* Copy channel path timeout bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (irb->scsw.cmd.cstat & SCHN_STAT_INTF_CTRL_CHK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			cdev_irb->esw.esw0.erw.cpt = irb->esw.esw0.erw.cpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		/* Copy failing storage address validity flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		cdev_irb->esw.esw0.erw.fsavf = irb->esw.esw0.erw.fsavf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (cdev_irb->esw.esw0.erw.fsavf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			/* ... and copy the failing storage address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			memcpy(cdev_irb->esw.esw0.faddr, irb->esw.esw0.faddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			       sizeof (irb->esw.esw0.faddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			/* ... and copy the failing storage address format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			cdev_irb->esw.esw0.erw.fsaf = irb->esw.esw0.erw.fsaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		/* Copy secondary ccw address validity bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		cdev_irb->esw.esw0.erw.scavf = irb->esw.esw0.erw.scavf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (irb->esw.esw0.erw.scavf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			/* ... and copy the secondary ccw address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			cdev_irb->esw.esw0.saddr = irb->esw.esw0.saddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* FIXME: DCTI for format 2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* Copy authorization bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	cdev_irb->esw.esw0.erw.auth = irb->esw.esw0.erw.auth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Copy path verification required flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	cdev_irb->esw.esw0.erw.pvrf = irb->esw.esw0.erw.pvrf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (irb->esw.esw0.erw.pvrf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		cdev->private->flags.doverify = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Copy concurrent sense bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	cdev_irb->esw.esw0.erw.cons = irb->esw.esw0.erw.cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (irb->esw.esw0.erw.cons)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		cdev_irb->esw.esw0.erw.scnt = irb->esw.esw0.erw.scnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * Accumulate status from irb to devstat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ccw_device_accumulate_irb(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct irb *cdev_irb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * Check if the status pending bit is set in stctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * If not, the remaining bit have no meaning and we must ignore them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * The esw is not meaningful as well...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!(scsw_stctl(&irb->scsw) & SCSW_STCTL_STATUS_PEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* Check for channel checks and interface control checks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ccw_device_msg_control_check(cdev, irb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* Check for path not operational. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (scsw_is_valid_pno(&irb->scsw) && scsw_pno(&irb->scsw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		ccw_device_path_notoper(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* No irb accumulation for transport mode irbs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (scsw_is_tm(&irb->scsw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		memcpy(&cdev->private->dma_area->irb, irb, sizeof(struct irb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * Don't accumulate unsolicited interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!scsw_is_solicited(&irb->scsw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	cdev_irb = &cdev->private->dma_area->irb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 * If the clear function had been performed, all formerly pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * status at the subchannel has been cleared and we must not pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * intermediate accumulated status to the device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (irb->scsw.cmd.fctl & SCSW_FCTL_CLEAR_FUNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		memset(&cdev->private->dma_area->irb, 0, sizeof(struct irb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* Copy bits which are valid only for the start function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (irb->scsw.cmd.fctl & SCSW_FCTL_START_FUNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		/* Copy key. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		cdev_irb->scsw.cmd.key = irb->scsw.cmd.key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		/* Copy suspend control bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		cdev_irb->scsw.cmd.sctl = irb->scsw.cmd.sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		/* Accumulate deferred condition code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		cdev_irb->scsw.cmd.cc |= irb->scsw.cmd.cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		/* Copy ccw format bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		cdev_irb->scsw.cmd.fmt = irb->scsw.cmd.fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		/* Copy prefetch bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		cdev_irb->scsw.cmd.pfch = irb->scsw.cmd.pfch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		/* Copy initial-status-interruption-control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		cdev_irb->scsw.cmd.isic = irb->scsw.cmd.isic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		/* Copy address limit checking control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		cdev_irb->scsw.cmd.alcc = irb->scsw.cmd.alcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		/* Copy suppress suspend bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		cdev_irb->scsw.cmd.ssi = irb->scsw.cmd.ssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Take care of the extended control bit and extended control word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ccw_device_accumulate_ecw(cdev, irb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	    
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Accumulate function control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	cdev_irb->scsw.cmd.fctl |= irb->scsw.cmd.fctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Copy activity control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	cdev_irb->scsw.cmd.actl = irb->scsw.cmd.actl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* Accumulate status control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	cdev_irb->scsw.cmd.stctl |= irb->scsw.cmd.stctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * Copy ccw address if it is valid. This is a bit simplified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * but should be close enough for all practical purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if ((irb->scsw.cmd.stctl & SCSW_STCTL_PRIM_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	    ((irb->scsw.cmd.stctl ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	      (SCSW_STCTL_INTER_STATUS|SCSW_STCTL_STATUS_PEND)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	     (irb->scsw.cmd.actl & SCSW_ACTL_DEVACT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	     (irb->scsw.cmd.actl & SCSW_ACTL_SCHACT)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	    (irb->scsw.cmd.actl & SCSW_ACTL_SUSPENDED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		cdev_irb->scsw.cmd.cpa = irb->scsw.cmd.cpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Accumulate device status, but not the device busy flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	cdev_irb->scsw.cmd.dstat &= ~DEV_STAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* dstat is not always valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (irb->scsw.cmd.stctl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	    (SCSW_STCTL_PRIM_STATUS | SCSW_STCTL_SEC_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	     | SCSW_STCTL_INTER_STATUS | SCSW_STCTL_ALERT_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		cdev_irb->scsw.cmd.dstat |= irb->scsw.cmd.dstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Accumulate subchannel status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	cdev_irb->scsw.cmd.cstat |= irb->scsw.cmd.cstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* Copy residual count if it is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if ((irb->scsw.cmd.stctl & SCSW_STCTL_PRIM_STATUS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	    (irb->scsw.cmd.cstat & ~(SCHN_STAT_PCI | SCHN_STAT_INCORR_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	     == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		cdev_irb->scsw.cmd.count = irb->scsw.cmd.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Take care of bits in the extended status word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ccw_device_accumulate_esw(cdev, irb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 * Check whether we must issue a SENSE CCW ourselves if there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 * concurrent sense facility installed for the subchannel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 * No sense is required if no delayed sense is pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 * and we did not get a unit check without sense information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * Note: We should check for ioinfo[irq]->flags.consns but VM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 *	 violates the ESA/390 architecture and doesn't present an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 *	 operand exception for virtual devices without concurrent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 *	 sense facility available/supported when enabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 *	 concurrent sense facility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if ((cdev_irb->scsw.cmd.dstat & DEV_STAT_UNIT_CHECK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	    !(cdev_irb->esw.esw0.erw.cons))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		cdev->private->flags.dosense = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * Do a basic sense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ccw_device_do_sense(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct subchannel *sch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct ccw1 *sense_ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	sch = to_subchannel(cdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/* A sense is required, can we do it now ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (scsw_actl(&irb->scsw) & (SCSW_ACTL_DEVACT | SCSW_ACTL_SCHACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		 * we received an Unit Check but we have no final
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		 *  status yet, therefore we must delay the SENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		 *  processing. We must not report this intermediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		 *  status to the device interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 * We have ending status but no sense information. Do a basic sense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	sense_ccw = &to_io_private(sch)->dma_area->sense_ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	sense_ccw->cmd_code = CCW_CMD_BASIC_SENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	sense_ccw->cda = (__u32) __pa(cdev->private->dma_area->irb.ecw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	sense_ccw->count = SENSE_MAX_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	sense_ccw->flags = CCW_FLAG_SLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	rc = cio_start(sch, sense_ccw, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (rc == -ENODEV || rc == -EACCES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		dev_fsm_event(cdev, DEV_EVENT_VERIFY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)  * Add information from basic sense to devstat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ccw_device_accumulate_basic_sense(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	 * Check if the status pending bit is set in stctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 * If not, the remaining bit have no meaning and we must ignore them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 * The esw is not meaningful as well...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!(scsw_stctl(&irb->scsw) & SCSW_STCTL_STATUS_PEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/* Check for channel checks and interface control checks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	ccw_device_msg_control_check(cdev, irb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* Check for path not operational. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (scsw_is_valid_pno(&irb->scsw) && scsw_pno(&irb->scsw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		ccw_device_path_notoper(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (!(irb->scsw.cmd.dstat & DEV_STAT_UNIT_CHECK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	    (irb->scsw.cmd.dstat & DEV_STAT_CHN_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		cdev->private->dma_area->irb.esw.esw0.erw.cons = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		cdev->private->flags.dosense = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* Check if path verification is required. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ccw_device_accumulate_esw_valid(irb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	    irb->esw.esw0.erw.pvrf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		cdev->private->flags.doverify = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  * This function accumulates the status into the private devstat and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  * starts a basic sense if one is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ccw_device_accumulate_and_sense(struct ccw_device *cdev, struct irb *irb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ccw_device_accumulate_irb(cdev, irb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if ((irb->scsw.cmd.actl  & (SCSW_ACTL_DEVACT | SCSW_ACTL_SCHACT)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* Check for basic sense. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (cdev->private->flags.dosense &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	    !(irb->scsw.cmd.dstat & DEV_STAT_UNIT_CHECK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		cdev->private->dma_area->irb.esw.esw0.erw.cons = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		cdev->private->flags.dosense = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (cdev->private->flags.dosense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		ccw_device_do_sense(cdev, irb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)