Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* RTC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define RTC_SET_TM_WR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define RTC_SET_TM_RD		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define RTC_CALIB_WR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define RTC_CALIB_RD		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define RTC_CUR_TM		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RTC_CUR_TICK		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RTC_ALRM		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RTC_INT_STS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RTC_INT_MASK		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RTC_INT_EN		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RTC_INT_DIS		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RTC_CTRL		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RTC_FR_EN		BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RTC_FR_DATSHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RTC_TICK_MASK		0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RTC_INT_SEC		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RTC_INT_ALRM		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RTC_OSC_EN		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RTC_BATT_EN		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RTC_CALIB_DEF		0x198233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RTC_CALIB_MASK		0x1FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTC_ALRM_MASK          BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RTC_MSEC               1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct xlnx_rtc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct rtc_device	*rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	void __iomem		*reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int			alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int			sec_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int		calibval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long new_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * The value written will be updated after 1 sec into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * seconds read register, so we need to program time +1 sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * to get the correct time on read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	new_time = rtc_tm_to_time64(tm) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * Writing into calibration register will clear the Tick Counter and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * force the next second to be signaled exactly in 1 second period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	xrtcdev->calibval &= RTC_CALIB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * Clear the rtc interrupt status register after setting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * time. During a read_time function, the code should read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * RTC_INT_STATUS register and if bit 0 is still 0, it means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * that one second has not elapsed yet since RTC was set and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * the current time should be read from SET_TIME_READ register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * otherwise, CURRENT_TIME register is read to report the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned long read_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	status = readl(xrtcdev->reg_base + RTC_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (status & RTC_INT_SEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * RTC has updated the CURRENT_TIME with the time written into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 * SET_TIME_WRITE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 * Time written in SET_TIME_WRITE has not yet updated into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		 * the seconds read register, so read the time from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		 * SET_TIME_WRITE instead of CURRENT_TIME register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		 * Since we add +1 sec while writing, we need to -1 sec while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 * reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	rtc_time64_to_tm(read_time, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ulong timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			status = readl(xrtcdev->reg_base + RTC_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				dev_err(dev, "Time out occur, while clearing alarm status bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned long alarm_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	alarm_time = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 rtc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Enable RTC switch to battery when VCC_PSAUX is not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	rtc_ctrl |= RTC_BATT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * Based on crystal freq of 33.330 KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * set the seconds counter and enable, set fractions counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * to default value suggested as per design spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * to correct RTC delay in frequency over period of time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	xrtcdev->calibval &= RTC_CALIB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct rtc_class_ops xlnx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.set_time	  = xlnx_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.read_time	  = xlnx_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.read_alarm	  = xlnx_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.set_alarm	  = xlnx_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	status = readl(xrtcdev->reg_base + RTC_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* Check if interrupt asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* Disable RTC_INT_ALRM interrupt only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (status & RTC_INT_ALRM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int xlnx_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct xlnx_rtc_dev *xrtcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!xrtcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	platform_set_drvdata(pdev, xrtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (IS_ERR(xrtcdev->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return PTR_ERR(xrtcdev->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	xrtcdev->rtc->ops = &xlnx_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	xrtcdev->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (IS_ERR(xrtcdev->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return PTR_ERR(xrtcdev->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (xrtcdev->alarm_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return xrtcdev->alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			       xlnx_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			       dev_name(&pdev->dev), xrtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		dev_err(&pdev->dev, "request irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (xrtcdev->sec_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return xrtcdev->sec_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			       xlnx_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			       dev_name(&pdev->dev), xrtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_err(&pdev->dev, "request irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = of_property_read_u32(pdev->dev.of_node, "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				   &xrtcdev->calibval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		xrtcdev->calibval = RTC_CALIB_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	xlnx_init_rtc(xrtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return rtc_register_device(xrtcdev->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int xlnx_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	device_init_wakeup(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		enable_irq_wake(xrtcdev->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		xlnx_rtc_alarm_irq_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int __maybe_unused xlnx_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		disable_irq_wake(xrtcdev->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		xlnx_rtc_alarm_irq_enable(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct of_device_id xlnx_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{.compatible = "xlnx,zynqmp-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct platform_driver xlnx_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.probe		= xlnx_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.remove		= xlnx_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.name	= KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.pm	= &xlnx_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.of_match_table	= xlnx_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) module_platform_driver(xlnx_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_AUTHOR("Xilinx Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_LICENSE("GPL v2");