Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * APM X-Gene SoC Real Time Clock Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *         Loc Ho <lho@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* RTC CSR Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define RTC_CCVR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define RTC_CMR			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RTC_CLR			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RTC_CCR			0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define  RTC_CCR_IE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  RTC_CCR_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  RTC_CCR_EN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  RTC_CCR_WEN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RTC_STAT		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define  RTC_STAT_BIT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RTC_RSTAT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RTC_EOI			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RTC_VER			0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct xgene_rtc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int irq_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * NOTE: After the following write, the RTC_CCVR is only reflected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 *       after the update cycle of 1 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* If possible, CMR should be read here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	rtc_time64_to_tm(0, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ccr = readl(pdata->csr_base + RTC_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		ccr &= ~RTC_CCR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		ccr |= RTC_CCR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		ccr &= ~RTC_CCR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		ccr |= RTC_CCR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	writel(ccr, pdata->csr_base + RTC_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int xgene_rtc_alarm_irq_enabled(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct rtc_class_ops xgene_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.read_time	= xgene_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.set_time	= xgene_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.read_alarm	= xgene_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.set_alarm	= xgene_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.alarm_irq_enable = xgene_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct xgene_rtc_dev *pdata = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* Check if interrupt asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	readl(pdata->csr_base + RTC_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int xgene_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct xgene_rtc_dev *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (IS_ERR(pdata->csr_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return PTR_ERR(pdata->csr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (IS_ERR(pdata->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return PTR_ERR(pdata->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			       dev_name(&pdev->dev), pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dev_err(&pdev->dev, "Could not request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	pdata->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ret = clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Turn on the clock and the crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* HW does not support update faster than 1 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	pdata->rtc->uie_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pdata->rtc->ops = &xgene_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	pdata->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ret = rtc_register_device(pdata->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int xgene_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	device_init_wakeup(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int __maybe_unused xgene_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * If this RTC alarm will be used for waking the system up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * don't disable it of course. Else we just disable the alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * and await suspension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (device_may_wakeup(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (!enable_irq_wake(irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			pdata->irq_wake = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		xgene_rtc_alarm_irq_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int __maybe_unused xgene_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (device_may_wakeup(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (pdata->irq_wake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			disable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			pdata->irq_wake = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		rc = clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			dev_err(dev, "Unable to enable clock error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct of_device_id xgene_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{.compatible = "apm,xgene-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_driver xgene_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.probe		= xgene_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.remove		= xgene_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.name	= "xgene-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.pm = &xgene_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.of_match_table	= of_match_ptr(xgene_rtc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) module_platform_driver(xgene_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_AUTHOR("Rameshwar Sahu <rsahu@apm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_LICENSE("GPL");