Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * An i2c driver for the Xicor/Intersil X1205 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2004 Karen Spearel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2005 Alessandro Zummo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * please send all reports to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Karen Spearel <kas111 at gmail dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	Alessandro Zummo <a.zummo@towertech.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * based on a lot of other RTC drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Information and datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* offsets into CCR area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CCR_SEC			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CCR_MIN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CCR_HOUR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CCR_MDAY		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CCR_MONTH		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CCR_YEAR		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CCR_WDAY		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CCR_Y2K			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define X1205_REG_SR		0x3F	/* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define X1205_REG_Y2K		0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define X1205_REG_DW		0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define X1205_REG_YR		0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define X1205_REG_MO		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define X1205_REG_DT		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define X1205_REG_HR		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define X1205_REG_MN		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define X1205_REG_SC		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define X1205_REG_DTR		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define X1205_REG_ATR		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define X1205_REG_INT		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define X1205_REG_0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define X1205_REG_Y2K1		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define X1205_REG_DWA1		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define X1205_REG_YRA1		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define X1205_REG_MOA1		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define X1205_REG_DTA1		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define X1205_REG_HRA1		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define X1205_REG_MNA1		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define X1205_REG_SCA1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define X1205_REG_Y2K0		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define X1205_REG_DWA0		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define X1205_REG_YRA0		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define X1205_REG_MOA0		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define X1205_REG_DTA0		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define X1205_REG_HRA0		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define X1205_REG_MNA0		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define X1205_REG_SCA0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define X1205_CCR_BASE		0x30	/* Base address of CCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define X1205_SR_RTCF		0x01	/* Clock failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define X1205_SR_WEL		0x02	/* Write Enable Latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define X1205_SR_RWEL		0x04	/* Register Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define X1205_SR_AL0		0x20	/* Alarm 0 match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define X1205_DTR_DTR0		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define X1205_DTR_DTR1		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define X1205_DTR_DTR2		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define X1205_INT_AL0E		0x20	/* Alarm 0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static struct i2c_driver x1205_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * In the routines that deal directly with the x1205 hardware, we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * Epoch is initialized as 2000. Time is set to UTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				unsigned char reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned char dt_addr[2] = { 0, reg_base };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned char buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		{/* setup read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			.buf = dt_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		{/* read date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			.len = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			.buf = buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* read date registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		dev_err(&client->dev, "%s: read error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		__func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		buf[0], buf[1], buf[2], buf[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		buf[4], buf[5], buf[6], buf[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Mask out the enable bits if these are alarm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (reg_base < X1205_CCR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		for (i = 0; i <= 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			buf[i] &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	tm->tm_min = bcd2bin(buf[CCR_MIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tm->tm_year = bcd2bin(buf[CCR_YEAR])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	tm->tm_wday = buf[CCR_WDAY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		"mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		__func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		tm->tm_sec, tm->tm_min, tm->tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		{     /* setup read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			.buf = sr_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		{    /* read status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			.buf = sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* read status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dev_err(&client->dev, "%s: read error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			u8 reg_base, unsigned char alm_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int i, xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned char rdata[10] = { 0, reg_base };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned char *buf = rdata + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	static const unsigned char wel[3] = { 0, X1205_REG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 						X1205_SR_WEL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 						X1205_SR_WEL | X1205_SR_RWEL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	buf[CCR_MIN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* set hour and 24hr bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* month, 1 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* year, since the rtc epoch*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	buf[CCR_WDAY] = tm->tm_wday & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* If writing alarm registers, set compare bits on registers 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (reg_base < X1205_CCR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		for (i = 0; i <= 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			buf[i] |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* this sequence is required to unlock the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	xfer = i2c_master_send(client, wel, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (xfer != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	xfer = i2c_master_send(client, rwel, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (xfer != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	xfer = i2c_master_send(client, rdata, sizeof(rdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (xfer != sizeof(rdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			"%s: result=%d addr=%02x, data=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			__func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			 xfer, rdata[1], rdata[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (reg_base < X1205_CCR_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		/* ...and set or clear the AL0E bit in the INT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		/* Need to set RWEL again as the write has cleared it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		xfer = i2c_master_send(client, rwel, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		if (xfer != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				"%s: aloe rwel - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 				__func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (alm_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			al0e[2] = X1205_INT_AL0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		xfer = i2c_master_send(client, al0e, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		if (xfer != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				"%s: al0e - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				__func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		/* and wait 10msec again for this write to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* disable further writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	xfer = i2c_master_send(client, diswe, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (xfer != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int x1205_fix_osc(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	memset(&tm, 0, sizeof(tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		dev_err(&client->dev, "unable to restart the oscillator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int x1205_get_dtrim(struct i2c_client *client, int *trim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	unsigned char dtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		{	/* setup read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			.buf = dtr_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		{      /* read dtr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			.buf = &dtr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* read dtr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		dev_err(&client->dev, "%s: read error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	*trim = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (dtr & X1205_DTR_DTR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		*trim += 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (dtr & X1205_DTR_DTR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		*trim += 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (dtr & X1205_DTR_DTR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		*trim = -*trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int x1205_get_atrim(struct i2c_client *client, int *trim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	s8 atr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		{/* setup read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			.buf = atr_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		{/* read atr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			.buf = &atr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/* read atr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		dev_err(&client->dev, "%s: read error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* atr is a two's complement value on 6 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 * perform sign extension. The formula is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	 * Catr = (atr * 0.25pF) + 11.00pF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	atr = sign_extend32(atr, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	*trim = (atr * 250) + 11000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct x1205_limit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	unsigned char reg, mask, min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int x1205_validate_client(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	int i, xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* Probe array. We will read the register at the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	 * address and check if the given bits are zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	static const unsigned char probe_zero_pattern[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		/* register, mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		X1205_REG_SR,	0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		X1205_REG_DTR,	0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		X1205_REG_ATR,	0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		X1205_REG_INT,	0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		X1205_REG_0,	0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	static const struct x1205_limit probe_limits_pattern[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		/* register, mask, min, max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		{ X1205_REG_Y2K,	0xFF,	19,	20	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		{ X1205_REG_DW,		0xFF,	0,	6	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		{ X1205_REG_YR,		0xFF,	0,	99	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		{ X1205_REG_MO,		0xFF,	0,	12	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		{ X1205_REG_DT,		0xFF,	0,	31	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		{ X1205_REG_HR,		0x7F,	0,	23	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		{ X1205_REG_MN,		0xFF,	0,	59	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		{ X1205_REG_SC,		0xFF,	0,	59	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		{ X1205_REG_Y2K1,	0xFF,	19,	20	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		{ X1205_REG_Y2K0,	0xFF,	19,	20	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	/* check that registers have bits a 0 where expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		unsigned char buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		unsigned char addr[2] = { 0, probe_zero_pattern[i] };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 				.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 				.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 				.buf = addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 				.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 				.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 				.buf = &buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		xfer = i2c_transfer(client->adapter, msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		if (xfer != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 				"%s: could not read register %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 				__func__, probe_zero_pattern[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		if ((buf & probe_zero_pattern[i+1]) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 				"%s: register=%02x, zero pattern=%d, value=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 				__func__, probe_zero_pattern[i], i, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	/* check limits (only registers with bcd values) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		unsigned char reg, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 				.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 				.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 				.buf = addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 				.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 				.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 				.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 				.buf = &reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		xfer = i2c_transfer(client->adapter, msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		if (xfer != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 				"%s: could not read register %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 				__func__, probe_limits_pattern[i].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		value = bcd2bin(reg & probe_limits_pattern[i].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		if (value > probe_limits_pattern[i].max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 			value < probe_limits_pattern[i].min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 			dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 				"%s: register=%x, lim pattern=%d, value=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 				__func__, probe_limits_pattern[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 				i, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	unsigned char intreg, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		{ /* setup read ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 			.buf = int_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		{/* read INT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 			.buf = &intreg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	/* read interrupt register and status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		dev_err(&client->dev, "%s: read error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	err = x1205_get_status(client, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	return x1205_set_datetime(to_i2c_client(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		&alrm->time, X1205_ALM0_BASE, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	return x1205_get_datetime(to_i2c_client(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		tm, X1205_CCR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	return x1205_set_datetime(to_i2c_client(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		tm, X1205_CCR_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	int err, dtrim, atrim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 			atrim / 1000, atrim % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct rtc_class_ops x1205_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	.proc		= x1205_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	.read_time	= x1205_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	.set_time	= x1205_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	.read_alarm	= x1205_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	.set_alarm	= x1205_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static ssize_t x1205_sysfs_show_atrim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 				struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	int err, atrim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 				struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	int err, dtrim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	return sprintf(buf, "%d ppm\n", dtrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int x1205_sysfs_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	err = device_create_file(dev, &dev_attr_atrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	err = device_create_file(dev, &dev_attr_dtrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 		device_remove_file(dev, &dev_attr_atrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void x1205_sysfs_unregister(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	device_remove_file(dev, &dev_attr_atrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	device_remove_file(dev, &dev_attr_dtrim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int x1205_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	unsigned char sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	if (x1205_validate_client(client) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 					&x1205_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 		return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	i2c_set_clientdata(client, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	/* Check for power failures and eventually enable the osc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	err = x1205_get_status(client, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 		if (sr & X1205_SR_RTCF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 				"power failure detected, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 				"please set the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 			udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 			x1205_fix_osc(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		dev_err(&client->dev, "couldn't read status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	err = x1205_sysfs_register(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 		dev_err(&client->dev, "Unable to create sysfs entries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int x1205_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	x1205_sysfs_unregister(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct i2c_device_id x1205_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	{ "x1205", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MODULE_DEVICE_TABLE(i2c, x1205_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct of_device_id x1205_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	{ .compatible = "xircom,x1205", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_DEVICE_TABLE(of, x1205_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct i2c_driver x1205_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 		.name	= "rtc-x1205",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 		.of_match_table = x1205_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	.probe		= x1205_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	.remove		= x1205_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	.id_table	= x1205_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) module_i2c_driver(x1205_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MODULE_AUTHOR(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	"Karen Spearel <kas111 at gmail dot com>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	"Alessandro Zummo <a.zummo@towertech.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MODULE_LICENSE("GPL");