^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Real Time Clock driver for Wolfson Microelectronics WM8350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Liam Girdwood
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * linux@wolfsonmicro.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/wm8350/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/wm8350/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WM8350_SET_ALM_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM8350_SET_TIME_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM8350_GET_TIME_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Read current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int wm8350_rtc_readtime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 time1[4], time2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int retries = WM8350_GET_TIME_RETRIES, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Read the time twice and compare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * If time1 == time2, then time is valid else retry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ret = wm8350_block_read(wm8350, WM8350_RTC_SECONDS_MINUTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 4, time1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = wm8350_block_read(wm8350, WM8350_RTC_SECONDS_MINUTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 4, time2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (memcmp(time1, time2, sizeof(time1)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) tm->tm_sec = time1[0] & WM8350_RTC_SECS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tm->tm_min = (time1[0] & WM8350_RTC_MINS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) >> WM8350_RTC_MINS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) tm->tm_hour = time1[1] & WM8350_RTC_HRS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tm->tm_wday = ((time1[1] >> WM8350_RTC_DAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) & 0x7) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tm->tm_mon = ((time1[2] & WM8350_RTC_MTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) >> WM8350_RTC_MTH_SHIFT) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tm->tm_mday = (time1[2] & WM8350_RTC_DATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tm->tm_year = ((time1[3] & WM8350_RTC_YHUNDREDS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) >> WM8350_RTC_YHUNDREDS_SHIFT) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tm->tm_year += time1[3] & WM8350_RTC_YUNITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tm->tm_year -= 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_dbg(dev, "Read (%d left): %04x %04x %04x %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) retries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) time1[0], time1[1], time1[2], time1[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } while (retries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(dev, "timed out reading RTC time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Set current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int wm8350_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 time[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 rtc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret, retries = WM8350_SET_TIME_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) time[0] = tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) time[0] |= tm->tm_min << WM8350_RTC_MINS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) time[1] = tm->tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) time[1] |= (tm->tm_wday + 1) << WM8350_RTC_DAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) time[2] = tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) time[2] |= (tm->tm_mon + 1) << WM8350_RTC_MTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) time[3] = ((tm->tm_year + 1900) / 100) << WM8350_RTC_YHUNDREDS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) time[3] |= (tm->tm_year + 1900) % 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_dbg(dev, "Setting: %04x %04x %04x %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) time[0], time[1], time[2], time[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Set RTC_SET to stop the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL, WM8350_RTC_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Wait until confirmation of stopping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) schedule_timeout_uninterruptible(msecs_to_jiffies(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } while (--retries && !(rtc_ctrl & WM8350_RTC_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(dev, "timed out on set confirmation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Write time to RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = wm8350_block_write(wm8350, WM8350_RTC_SECONDS_MINUTES, 4, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Clear RTC_SET to start the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) WM8350_RTC_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Read alarm time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int wm8350_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 time[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = wm8350_block_read(wm8350, WM8350_ALARM_SECONDS_MINUTES, 4, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tm->tm_sec = time[0] & WM8350_RTC_ALMSECS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (tm->tm_sec == WM8350_RTC_ALMSECS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tm->tm_sec = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tm->tm_min = time[0] & WM8350_RTC_ALMMINS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (tm->tm_min == WM8350_RTC_ALMMINS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tm->tm_min = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tm->tm_min >>= WM8350_RTC_ALMMINS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tm->tm_hour = time[1] & WM8350_RTC_ALMHRS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (tm->tm_hour == WM8350_RTC_ALMHRS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tm->tm_hour = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tm->tm_wday = ((time[1] >> WM8350_RTC_ALMDAY_SHIFT) & 0x7) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (tm->tm_wday > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tm->tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tm->tm_mon = time[2] & WM8350_RTC_ALMMTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (tm->tm_mon == WM8350_RTC_ALMMTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tm->tm_mon = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tm->tm_mon = (tm->tm_mon >> WM8350_RTC_ALMMTH_SHIFT) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tm->tm_mday = (time[2] & WM8350_RTC_ALMDATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (tm->tm_mday == WM8350_RTC_ALMDATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tm->tm_mday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tm->tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) alrm->enabled = !(time[3] & WM8350_RTC_ALMSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int wm8350_rtc_stop_alarm(struct wm8350 *wm8350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int retries = WM8350_SET_ALM_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u16 rtc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Set RTC_SET to stop the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) WM8350_RTC_ALMSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Wait until confirmation of stopping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) schedule_timeout_uninterruptible(msecs_to_jiffies(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } while (retries-- && !(rtc_ctrl & WM8350_RTC_ALMSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!(rtc_ctrl & WM8350_RTC_ALMSTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int wm8350_rtc_start_alarm(struct wm8350 *wm8350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int retries = WM8350_SET_ALM_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 rtc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) WM8350_RTC_ALMSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Wait until confirmation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) schedule_timeout_uninterruptible(msecs_to_jiffies(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } while (retries-- && rtc_ctrl & WM8350_RTC_ALMSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (rtc_ctrl & WM8350_RTC_ALMSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int wm8350_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return wm8350_rtc_start_alarm(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return wm8350_rtc_stop_alarm(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int wm8350_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u16 time[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) memset(time, 0, sizeof(time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (tm->tm_sec != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) time[0] |= tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) time[0] |= WM8350_RTC_ALMSECS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (tm->tm_min != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) time[0] |= tm->tm_min << WM8350_RTC_ALMMINS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) time[0] |= WM8350_RTC_ALMMINS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (tm->tm_hour != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) time[1] |= tm->tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) time[1] |= WM8350_RTC_ALMHRS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (tm->tm_wday != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) time[1] |= (tm->tm_wday + 1) << WM8350_RTC_ALMDAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) time[1] |= WM8350_RTC_ALMDAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (tm->tm_mday != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) time[2] |= tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) time[2] |= WM8350_RTC_ALMDATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (tm->tm_mon != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) time[2] |= (tm->tm_mon + 1) << WM8350_RTC_ALMMTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) time[2] |= WM8350_RTC_ALMMTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = wm8350_rtc_stop_alarm(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Write time to RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = wm8350_block_write(wm8350, WM8350_ALARM_SECONDS_MINUTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 3, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (alrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = wm8350_rtc_start_alarm(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static irqreturn_t wm8350_rtc_alarm_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct wm8350 *wm8350 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct rtc_device *rtc = wm8350->rtc.rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Make it one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) WM8350_RTC_ALMSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&(wm8350->rtc.pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "Failed to disable alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static irqreturn_t wm8350_rtc_update_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct wm8350 *wm8350 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct rtc_device *rtc = wm8350->rtc.rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rtc_update_irq(rtc, 1, RTC_IRQF | RTC_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct rtc_class_ops wm8350_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .read_time = wm8350_rtc_readtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .set_time = wm8350_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .read_alarm = wm8350_rtc_readalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .set_alarm = wm8350_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .alarm_irq_enable = wm8350_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int wm8350_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (device_may_wakeup(&wm8350->rtc.pdev->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg & WM8350_RTC_ALMSTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = wm8350_rtc_stop_alarm(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(dev, "Failed to stop RTC alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int wm8350_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct wm8350 *wm8350 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (wm8350->rtc.alarm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = wm8350_rtc_start_alarm(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(dev, "Failed to restart RTC alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int wm8350_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct wm8350 *wm8350 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct wm8350_rtc *wm_rtc = &wm8350->rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u16 timectl, power5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) timectl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (timectl & WM8350_RTC_BCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&pdev->dev, "RTC BCD mode not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (timectl & WM8350_RTC_12HR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(&pdev->dev, "RTC 12 hour mode not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* enable the RTC if it's not already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) power5 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!(power5 & WM8350_RTC_TICK_ENA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_info(wm8350->dev, "Starting RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) wm8350_reg_unlock(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) WM8350_RTC_TICK_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(&pdev->dev, "failed to enable RTC: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) wm8350_reg_lock(wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (timectl & WM8350_RTC_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) WM8350_RTC_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&pdev->dev, "failed to start: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) retries = WM8350_SET_TIME_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) timectl = wm8350_reg_read(wm8350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) WM8350_RTC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } while (timectl & WM8350_RTC_STS && --retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (retries == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(&pdev->dev, "failed to start: timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) wm_rtc->rtc = devm_rtc_device_register(&pdev->dev, "wm8350",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &wm8350_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (IS_ERR(wm_rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = PTR_ERR(wm_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(&pdev->dev, "failed to register RTC: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) wm8350_register_irq(wm8350, WM8350_IRQ_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wm8350_rtc_update_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "RTC Seconds", wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) wm8350_register_irq(wm8350, WM8350_IRQ_RTC_ALM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) wm8350_rtc_alarm_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "RTC Alarm", wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int wm8350_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct wm8350 *wm8350 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) wm8350_free_irq(wm8350, WM8350_IRQ_RTC_SEC, wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) wm8350_free_irq(wm8350, WM8350_IRQ_RTC_ALM, wm8350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static SIMPLE_DEV_PM_OPS(wm8350_rtc_pm_ops, wm8350_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) wm8350_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct platform_driver wm8350_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .probe = wm8350_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .remove = wm8350_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = "wm8350-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .pm = &wm8350_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) module_platform_driver(wm8350_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_DESCRIPTION("RTC driver for the WM8350");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_ALIAS("platform:wm8350-rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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