^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Real Time Clock driver for Wolfson Microelectronics WM831x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/wm831x/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * R16416 (0x4020) - RTC Write Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM831X_RTC_WR_CNT_MASK 0xFFFF /* RTC_WR_CNT - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM831X_RTC_WR_CNT_SHIFT 0 /* RTC_WR_CNT - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM831X_RTC_WR_CNT_WIDTH 16 /* RTC_WR_CNT - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * R16417 (0x4021) - RTC Time 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WM831X_RTC_TIME_MASK 0xFFFF /* RTC_TIME - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WM831X_RTC_TIME_SHIFT 0 /* RTC_TIME - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WM831X_RTC_TIME_WIDTH 16 /* RTC_TIME - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * R16418 (0x4022) - RTC Time 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WM831X_RTC_TIME_MASK 0xFFFF /* RTC_TIME - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WM831X_RTC_TIME_SHIFT 0 /* RTC_TIME - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WM831X_RTC_TIME_WIDTH 16 /* RTC_TIME - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * R16419 (0x4023) - RTC Alarm 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WM831X_RTC_ALM_MASK 0xFFFF /* RTC_ALM - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WM831X_RTC_ALM_SHIFT 0 /* RTC_ALM - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WM831X_RTC_ALM_WIDTH 16 /* RTC_ALM - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * R16420 (0x4024) - RTC Alarm 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM831X_RTC_ALM_MASK 0xFFFF /* RTC_ALM - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM831X_RTC_ALM_SHIFT 0 /* RTC_ALM - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WM831X_RTC_ALM_WIDTH 16 /* RTC_ALM - [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * R16421 (0x4025) - RTC Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM831X_RTC_VALID 0x8000 /* RTC_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WM831X_RTC_VALID_MASK 0x8000 /* RTC_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WM831X_RTC_VALID_SHIFT 15 /* RTC_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WM831X_RTC_VALID_WIDTH 1 /* RTC_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WM831X_RTC_SYNC_BUSY 0x4000 /* RTC_SYNC_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WM831X_RTC_SYNC_BUSY_MASK 0x4000 /* RTC_SYNC_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WM831X_RTC_SYNC_BUSY_SHIFT 14 /* RTC_SYNC_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WM831X_RTC_SYNC_BUSY_WIDTH 1 /* RTC_SYNC_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WM831X_RTC_ALM_ENA 0x0400 /* RTC_ALM_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WM831X_RTC_ALM_ENA_MASK 0x0400 /* RTC_ALM_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WM831X_RTC_ALM_ENA_SHIFT 10 /* RTC_ALM_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WM831X_RTC_ALM_ENA_WIDTH 1 /* RTC_ALM_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WM831X_RTC_PINT_FREQ_MASK 0x0070 /* RTC_PINT_FREQ - [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WM831X_RTC_PINT_FREQ_SHIFT 4 /* RTC_PINT_FREQ - [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WM831X_RTC_PINT_FREQ_WIDTH 3 /* RTC_PINT_FREQ - [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * R16422 (0x4026) - RTC Trim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WM831X_RTC_TRIM_MASK 0x03FF /* RTC_TRIM - [9:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WM831X_RTC_TRIM_SHIFT 0 /* RTC_TRIM - [9:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WM831X_RTC_TRIM_WIDTH 10 /* RTC_TRIM - [9:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WM831X_SET_TIME_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WM831X_GET_TIME_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct wm831x_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct wm831x *wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int alarm_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void wm831x_rtc_add_randomness(struct wm831x *wm831x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * The write counter contains a pseudo-random number which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * regenerated every time we set the RTC so it should be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * useful per-system source of entropy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = wm831x_reg_read(wm831x, WM831X_RTC_WRITE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) add_device_randomness(®, sizeof(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_warn(wm831x->dev, "Failed to read RTC write counter: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Read current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int wm831x_rtc_readtime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct wm831x *wm831x = wm831x_rtc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 time1[2], time2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Has the RTC been programmed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_err(dev, "Failed to read RTC control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!(ret & WM831X_RTC_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_dbg(dev, "RTC not yet configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Read twice to make sure we don't read a corrupt, partially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * incremented, value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = wm831x_bulk_read(wm831x, WM831X_RTC_TIME_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 2, time1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = wm831x_bulk_read(wm831x, WM831X_RTC_TIME_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 2, time2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (memcmp(time1, time2, sizeof(time1)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 time = (time1[0] << 16) | time1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rtc_time64_to_tm(time, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } while (++count < WM831X_GET_TIME_RETRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev, "Timed out reading current time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Set current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int wm831x_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct wm831x *wm831x = wm831x_rtc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct rtc_time new_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long time, new_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) time = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = wm831x_reg_write(wm831x, WM831X_RTC_TIME_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (time >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(dev, "Failed to write TIME_1: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = wm831x_reg_write(wm831x, WM831X_RTC_TIME_2, time & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_err(dev, "Failed to write TIME_2: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Wait for the update to complete - should happen first time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * round but be conservative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = WM831X_RTC_SYNC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } while (!(ret & WM831X_RTC_SYNC_BUSY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ++count < WM831X_SET_TIME_RETRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret & WM831X_RTC_SYNC_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(dev, "Timed out writing RTC update\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Check that the update was accepted; security features may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * have caused the update to be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = wm831x_rtc_readtime(dev, &new_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) new_time = rtc_tm_to_time64(&new_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Allow a second of change in case of tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (new_time - time > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(dev, "RTC update not permitted by hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Read alarm time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int wm831x_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = wm831x_bulk_read(wm831x_rtc->wm831x, WM831X_RTC_ALARM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(dev, "Failed to read alarm time: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) time = (data[0] << 16) | data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rtc_time64_to_tm(time, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = wm831x_reg_read(wm831x_rtc->wm831x, WM831X_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(dev, "Failed to read RTC control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret & WM831X_RTC_ALM_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) alrm->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int wm831x_rtc_stop_alarm(struct wm831x_rtc *wm831x_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) wm831x_rtc->alarm_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) WM831X_RTC_ALM_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int wm831x_rtc_start_alarm(struct wm831x_rtc *wm831x_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) wm831x_rtc->alarm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) WM831X_RTC_ALM_ENA, WM831X_RTC_ALM_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int wm831x_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct wm831x *wm831x = wm831x_rtc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) time = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = wm831x_rtc_stop_alarm(wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(dev, "Failed to stop alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = wm831x_reg_write(wm831x, WM831X_RTC_ALARM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (time >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(dev, "Failed to write ALARM_1: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = wm831x_reg_write(wm831x, WM831X_RTC_ALARM_2, time & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "Failed to write ALARM_2: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = wm831x_rtc_start_alarm(wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(dev, "Failed to start alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int wm831x_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return wm831x_rtc_start_alarm(wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return wm831x_rtc_stop_alarm(wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static irqreturn_t wm831x_alm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct wm831x_rtc *wm831x_rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) rtc_update_irq(wm831x_rtc->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct rtc_class_ops wm831x_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .read_time = wm831x_rtc_readtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .set_time = wm831x_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .read_alarm = wm831x_rtc_readalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .set_alarm = wm831x_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .alarm_irq_enable = wm831x_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Turn off the alarm if it should not be a wake source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int wm831x_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ret, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (wm831x_rtc->alarm_enabled && device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) enable = WM831X_RTC_ALM_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) WM831X_RTC_ALM_ENA, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(dev, "Failed to update RTC alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Enable the alarm if it should be enabled (in case it was disabled to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * prevent use as a wake source).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int wm831x_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (wm831x_rtc->alarm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = wm831x_rtc_start_alarm(wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(dev, "Failed to restart RTC alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Unconditionally disable the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int wm831x_rtc_freeze(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) WM831X_RTC_ALM_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(dev, "Failed to stop RTC alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define wm831x_rtc_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define wm831x_rtc_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define wm831x_rtc_freeze NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int wm831x_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct wm831x_rtc *wm831x_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int alm_irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "ALM"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) wm831x_rtc = devm_kzalloc(&pdev->dev, sizeof(*wm831x_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (wm831x_rtc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) platform_set_drvdata(pdev, wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) wm831x_rtc->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(&pdev->dev, "Failed to read RTC control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret & WM831X_RTC_ALM_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) wm831x_rtc->alarm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) wm831x_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (IS_ERR(wm831x_rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return PTR_ERR(wm831x_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) wm831x_rtc->rtc->ops = &wm831x_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) wm831x_rtc->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = rtc_register_device(wm831x_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = devm_request_threaded_irq(&pdev->dev, alm_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) wm831x_alm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "RTC alarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) wm831x_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) alm_irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) wm831x_rtc_add_randomness(wm831x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct dev_pm_ops wm831x_rtc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .suspend = wm831x_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .resume = wm831x_rtc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .freeze = wm831x_rtc_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .thaw = wm831x_rtc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .restore = wm831x_rtc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .poweroff = wm831x_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct platform_driver wm831x_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .probe = wm831x_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .name = "wm831x-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .pm = &wm831x_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) module_platform_driver(wm831x_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_DESCRIPTION("RTC driver for the WM831x series PMICs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_ALIAS("platform:wm831x-rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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