^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/rtc/rtc-vt8500.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on rtc-pxa.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VT8500_RTC_TS 0x00 /* Time set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VT8500_RTC_DS 0x04 /* Date set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VT8500_RTC_AS 0x08 /* Alarm set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VT8500_RTC_CR 0x0c /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VT8500_RTC_TR 0x10 /* Time read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VT8500_RTC_DR 0x14 /* Date read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VT8500_RTC_WS 0x18 /* Write status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VT8500_RTC_CL 0x20 /* Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VT8500_RTC_IS 0x24 /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VT8500_RTC_ST 0x28 /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define INVALID_TIME_BIT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DATE_CENTURY_S 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DATE_YEAR_S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DATE_YEAR_MASK (0xff << DATE_YEAR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DATE_MONTH_S 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DATE_MONTH_MASK (0x1f << DATE_MONTH_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DATE_DAY_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TIME_DOW_S 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIME_DOW_MASK (0x07 << TIME_DOW_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TIME_HOUR_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TIME_HOUR_MASK (0x3f << TIME_HOUR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TIME_MIN_S 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TIME_MIN_MASK (0x7f << TIME_MIN_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TIME_SEC_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ALARM_DAY_S 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ALARM_DAY_MASK (0x3f << ALARM_DAY_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ALARM_DAY_BIT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ALARM_HOUR_BIT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ALARM_MIN_BIT (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ALARM_SEC_BIT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ALARM_ENABLE_MASK (ALARM_DAY_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) | ALARM_HOUR_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) | ALARM_MIN_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) | ALARM_SEC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VT8500_RTC_CR_ENABLE (1 << 0) /* Enable RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VT8500_RTC_CR_12H (1 << 1) /* 12h time format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VT8500_RTC_CR_SM_ENABLE (1 << 2) /* Enable periodic irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VT8500_RTC_CR_SM_SEC (1 << 3) /* 0: 1Hz/60, 1: 1Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VT8500_RTC_CR_CALIB (1 << 4) /* Enable calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VT8500_RTC_IS_ALARM (1 << 0) /* Alarm interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct vt8500_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int irq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spinlock_t lock; /* Protects this structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static irqreturn_t vt8500_rtc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct vt8500_rtc *vt8500_rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spin_lock(&vt8500_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* clear interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_unlock(&vt8500_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (isr & VT8500_RTC_IS_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) events |= RTC_AF | RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rtc_update_irq(vt8500_rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int vt8500_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 date, time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) date = readl(vt8500_rtc->regbase + VT8500_RTC_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) time = readl(vt8500_rtc->regbase + VT8500_RTC_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tm->tm_sec = bcd2bin(time & TIME_SEC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tm->tm_min = bcd2bin((time & TIME_MIN_MASK) >> TIME_MIN_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tm->tm_hour = bcd2bin((time & TIME_HOUR_MASK) >> TIME_HOUR_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tm->tm_mday = bcd2bin(date & DATE_DAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tm->tm_mon = bcd2bin((date & DATE_MONTH_MASK) >> DATE_MONTH_S) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tm->tm_year = bcd2bin((date & DATE_YEAR_MASK) >> DATE_YEAR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) + ((date >> DATE_CENTURY_S) & 1 ? 200 : 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tm->tm_wday = (time & TIME_DOW_MASK) >> TIME_DOW_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int vt8500_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel((bin2bcd(tm->tm_year % 100) << DATE_YEAR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | (bin2bcd(tm->tm_mon + 1) << DATE_MONTH_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | (bin2bcd(tm->tm_mday))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | ((tm->tm_year >= 200) << DATE_CENTURY_S),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) vt8500_rtc->regbase + VT8500_RTC_DS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel((bin2bcd(tm->tm_wday) << TIME_DOW_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | (bin2bcd(tm->tm_hour) << TIME_HOUR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) | (bin2bcd(tm->tm_min) << TIME_MIN_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | (bin2bcd(tm->tm_sec)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) vt8500_rtc->regbase + VT8500_RTC_TS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int vt8500_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 isr, alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) alrm->time.tm_mday = bcd2bin((alarm & ALARM_DAY_MASK) >> ALARM_DAY_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) alrm->time.tm_hour = bcd2bin((alarm & TIME_HOUR_MASK) >> TIME_HOUR_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) alrm->time.tm_min = bcd2bin((alarm & TIME_MIN_MASK) >> TIME_MIN_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) alrm->time.tm_sec = bcd2bin((alarm & TIME_SEC_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) alrm->enabled = (alarm & ALARM_ENABLE_MASK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) alrm->pending = (isr & VT8500_RTC_IS_ALARM) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return rtc_valid_tm(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int vt8500_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) writel((alrm->enabled ? ALARM_ENABLE_MASK : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) | (bin2bcd(alrm->time.tm_mday) << ALARM_DAY_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) | (bin2bcd(alrm->time.tm_hour) << TIME_HOUR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) | (bin2bcd(alrm->time.tm_min) << TIME_MIN_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) | (bin2bcd(alrm->time.tm_sec)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) vt8500_rtc->regbase + VT8500_RTC_AS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int vt8500_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long tmp = readl(vt8500_rtc->regbase + VT8500_RTC_AS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tmp |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tmp &= ~ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(tmp, vt8500_rtc->regbase + VT8500_RTC_AS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct rtc_class_ops vt8500_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .read_time = vt8500_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .set_time = vt8500_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .read_alarm = vt8500_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .set_alarm = vt8500_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .alarm_irq_enable = vt8500_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int vt8500_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct vt8500_rtc *vt8500_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) vt8500_rtc = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sizeof(struct vt8500_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!vt8500_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_lock_init(&vt8500_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) platform_set_drvdata(pdev, vt8500_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) vt8500_rtc->irq_alarm = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (vt8500_rtc->irq_alarm < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return vt8500_rtc->irq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) vt8500_rtc->regbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(vt8500_rtc->regbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return PTR_ERR(vt8500_rtc->regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Enable RTC and set it to 24-hour mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(VT8500_RTC_CR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) vt8500_rtc->regbase + VT8500_RTC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) vt8500_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ERR(vt8500_rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PTR_ERR(vt8500_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vt8500_rtc->rtc->ops = &vt8500_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) vt8500_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vt8500_rtc->rtc->range_max = RTC_TIMESTAMP_END_2199;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = devm_request_irq(&pdev->dev, vt8500_rtc->irq_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vt8500_rtc_irq, 0, "rtc alarm", vt8500_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(&pdev->dev, "can't get irq %i, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) vt8500_rtc->irq_alarm, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return rtc_register_device(vt8500_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int vt8500_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct vt8500_rtc *vt8500_rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Disable alarm matching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel(0, vt8500_rtc->regbase + VT8500_RTC_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct of_device_id wmt_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .compatible = "via,vt8500-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_DEVICE_TABLE(of, wmt_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct platform_driver vt8500_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .probe = vt8500_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .remove = vt8500_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "vt8500-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .of_match_table = wmt_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) module_platform_driver(vt8500_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_DESCRIPTION("VIA VT8500 SoC Realtime Clock Driver (RTC)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_ALIAS("platform:vt8500-rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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