Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for NEC VR4100 series Real Time Clock unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2003-2008  Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* RTC 1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ETIMELREG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ETIMEMREG		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ETIMEHREG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ECMPLREG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ECMPMREG		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ECMPHREG		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RTCL1LREG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RTCL1HREG		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RTCL1CNTLREG		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RTCL1CNTHREG		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTCL2LREG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RTCL2HREG		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RTCL2CNTLREG		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RTCL2CNTHREG		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* RTC 2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TCLKLREG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TCLKHREG		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TCLKCNTLREG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TCLKCNTHREG		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RTCINTREG		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  #define TCLOCK_INT		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  #define RTCLONG2_INT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  #define RTCLONG1_INT		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  #define ELAPSEDTIME_INT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RTC_FREQUENCY		32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MAX_PERIODIC_RATE	6553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static void __iomem *rtc1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void __iomem *rtc2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define rtc1_read(offset)		readw(rtc1_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define rtc2_read(offset)		readw(rtc2_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* 32-bit compat for ioctls that nobody else uses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define RTC_EPOCH_READ32	_IOR('p', 0x0d, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static DEFINE_SPINLOCK(rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static char rtc_name[] = "RTC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static unsigned long periodic_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static unsigned int alarm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int aie_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int pie_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static inline time64_t read_elapsed_second(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned long first_low, first_mid, first_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned long second_low, second_mid, second_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		first_low = rtc1_read(ETIMELREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		first_mid = rtc1_read(ETIMEMREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		first_high = rtc1_read(ETIMEHREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		second_low = rtc1_read(ETIMELREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		second_mid = rtc1_read(ETIMEMREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		second_high = rtc1_read(ETIMEHREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	} while (first_low != second_low || first_mid != second_mid ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 first_high != second_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void write_elapsed_second(time64_t sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	spin_lock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	spin_unlock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	time64_t epoch_sec, elapsed_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	elapsed_sec = read_elapsed_second();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	time64_t epoch_sec, current_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	current_sec = rtc_tm_to_time64(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	write_elapsed_second(current_sec - epoch_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long low, mid, high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct rtc_time *time = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spin_lock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	low = rtc1_read(ECMPLREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mid = rtc1_read(ECMPMREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	high = rtc1_read(ECMPHREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	wkalrm->enabled = alarm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	spin_unlock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	time64_t alarm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	alarm_sec = rtc_tm_to_time64(&wkalrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	spin_lock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (alarm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		disable_irq(aie_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (wkalrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		enable_irq(aie_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	alarm_enabled = wkalrm->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	spin_unlock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case RTC_EPOCH_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return put_user(epoch, (unsigned long __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case RTC_EPOCH_READ32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return put_user(epoch, (unsigned int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case RTC_EPOCH_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		/* Doesn't support before 1900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		if (arg < 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		epoch = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	spin_lock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (!alarm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			enable_irq(aie_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			alarm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (alarm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			disable_irq(aie_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			alarm_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	spin_unlock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct platform_device *pdev = (struct platform_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct rtc_device *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	rtc_update_irq(rtc, 1, RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct platform_device *pdev = (struct platform_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct rtc_device *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	unsigned long count = periodic_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rtc2_write(RTCINTREG, RTCLONG1_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	rtc1_write(RTCL1LREG, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	rtc1_write(RTCL1HREG, count >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	rtc_update_irq(rtc, 1, RTC_PF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct rtc_class_ops vr41xx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.ioctl			= vr41xx_rtc_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.read_time		= vr41xx_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.set_time		= vr41xx_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.read_alarm		= vr41xx_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.set_alarm		= vr41xx_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.alarm_irq_enable	= vr41xx_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (pdev->num_resources != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!rtc1_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		goto err_rtc1_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!rtc2_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		goto err_rtc1_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (IS_ERR(rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		retval = PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		goto err_iounmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	rtc->ops = &vr41xx_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* 48-bit counter at 32.768 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	rtc->range_max = (1ULL << 33) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	rtc->max_user_freq = MAX_PERIODIC_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	spin_lock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	rtc1_write(ECMPLREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	rtc1_write(ECMPMREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	rtc1_write(ECMPHREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	rtc1_write(RTCL1LREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	rtc1_write(RTCL1HREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	spin_unlock_irq(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	aie_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (aie_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		goto err_iounmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				"elapsed_time", pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		goto err_iounmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	pie_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (pie_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		goto err_iounmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				"rtclong1", pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		goto err_iounmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	disable_irq(aie_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	disable_irq(pie_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	retval = rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		goto err_iounmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) err_iounmap_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	rtc2_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err_rtc1_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	rtc1_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_ALIAS("platform:RTC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct platform_driver rtc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.probe		= rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.name	= rtc_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_platform_driver(rtc_platform_driver);