^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/rtc/rtc-v3020.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006 8D Technologies inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Compulab Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Driver for the V3020 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Changelog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 10-May-2006: Raphael Assenat <raph@8d.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Converted to platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - Use the generic rtc class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ??-???-2004: Someone at Compulab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - Initial driver creation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/rtc-v3020.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct v3020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct v3020_chip_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int (*map_io)(struct v3020 *chip, struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct v3020_platform_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void (*unmap_io)(struct v3020 *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned char (*read_bit)(struct v3020 *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void (*write_bit)(struct v3020 *chip, unsigned char bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define V3020_CS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define V3020_WR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define V3020_RD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define V3020_IO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct v3020 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* MMIO access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *ioaddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int leftshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* GPIO access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct v3020_chip_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int v3020_mmio_map(struct v3020 *chip, struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct v3020_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (pdev->num_resources != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (pdev->resource[0].flags != IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) chip->leftshift = pdata->leftshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) chip->ioaddress = ioremap(pdev->resource[0].start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (chip->ioaddress == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void v3020_mmio_unmap(struct v3020 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) iounmap(chip->ioaddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void v3020_mmio_write_bit(struct v3020 *chip, unsigned char bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(bit << chip->leftshift, chip->ioaddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static unsigned char v3020_mmio_read_bit(struct v3020 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return !!(readl(chip->ioaddress) & (1 << chip->leftshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct v3020_chip_ops v3020_mmio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .map_io = v3020_mmio_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .unmap_io = v3020_mmio_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .read_bit = v3020_mmio_read_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .write_bit = v3020_mmio_write_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct gpio v3020_gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0, GPIOF_OUT_INIT_HIGH, "RTC CS"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0, GPIOF_OUT_INIT_HIGH, "RTC WR"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0, GPIOF_OUT_INIT_HIGH, "RTC RD"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0, GPIOF_OUT_INIT_HIGH, "RTC IO"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int v3020_gpio_map(struct v3020 *chip, struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct v3020_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) v3020_gpio[V3020_CS].gpio = pdata->gpio_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) v3020_gpio[V3020_WR].gpio = pdata->gpio_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) v3020_gpio[V3020_RD].gpio = pdata->gpio_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) v3020_gpio[V3020_IO].gpio = pdata->gpio_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) err = gpio_request_array(v3020_gpio, ARRAY_SIZE(v3020_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) chip->gpio = v3020_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void v3020_gpio_unmap(struct v3020 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) gpio_free_array(v3020_gpio, ARRAY_SIZE(v3020_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void v3020_gpio_write_bit(struct v3020 *chip, unsigned char bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) gpio_direction_output(chip->gpio[V3020_IO].gpio, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) gpio_set_value(chip->gpio[V3020_CS].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) gpio_set_value(chip->gpio[V3020_WR].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) gpio_set_value(chip->gpio[V3020_WR].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gpio_set_value(chip->gpio[V3020_CS].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static unsigned char v3020_gpio_read_bit(struct v3020 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) gpio_direction_input(chip->gpio[V3020_IO].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) gpio_set_value(chip->gpio[V3020_CS].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) gpio_set_value(chip->gpio[V3020_RD].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bit = !!gpio_get_value(chip->gpio[V3020_IO].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) gpio_set_value(chip->gpio[V3020_RD].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gpio_set_value(chip->gpio[V3020_CS].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct v3020_chip_ops v3020_gpio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .map_io = v3020_gpio_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .unmap_io = v3020_gpio_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .read_bit = v3020_gpio_read_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .write_bit = v3020_gpio_write_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void v3020_set_reg(struct v3020 *chip, unsigned char address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tmp = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) chip->ops->write_bit(chip, (tmp & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tmp >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Commands dont have data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!V3020_IS_COMMAND(address)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chip->ops->write_bit(chip, (data & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) data >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static unsigned char v3020_get_reg(struct v3020 *chip, unsigned char address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) chip->ops->write_bit(chip, (address & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) address >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) data >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (chip->ops->read_bit(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) data |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int v3020_read_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct v3020 *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Copy the current time to ram... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) v3020_set_reg(chip, V3020_CMD_CLOCK2RAM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* ...and then read constant values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmp = v3020_get_reg(chip, V3020_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dt->tm_sec = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp = v3020_get_reg(chip, V3020_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dt->tm_min = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tmp = v3020_get_reg(chip, V3020_HOURS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dt->tm_hour = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tmp = v3020_get_reg(chip, V3020_MONTH_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dt->tm_mday = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tmp = v3020_get_reg(chip, V3020_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dt->tm_mon = bcd2bin(tmp) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tmp = v3020_get_reg(chip, V3020_WEEK_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dt->tm_wday = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmp = v3020_get_reg(chip, V3020_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dt->tm_year = bcd2bin(tmp)+100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_dbg(dev, "\n%s : Read RTC values\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(dev, "tm_hour: %i\n", dt->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_dbg(dev, "tm_min : %i\n", dt->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_dbg(dev, "tm_sec : %i\n", dt->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_dbg(dev, "tm_year: %i\n", dt->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(dev, "tm_mon : %i\n", dt->tm_mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(dev, "tm_mday: %i\n", dt->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(dev, "tm_wday: %i\n", dt->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int v3020_set_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct v3020 *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_dbg(dev, "\n%s : Setting RTC values\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_dbg(dev, "tm_sec : %i\n", dt->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_dbg(dev, "tm_min : %i\n", dt->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_dbg(dev, "tm_hour: %i\n", dt->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_dbg(dev, "tm_mday: %i\n", dt->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_dbg(dev, "tm_wday: %i\n", dt->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_dbg(dev, "tm_year: %i\n", dt->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Write all the values to ram... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) v3020_set_reg(chip, V3020_SECONDS, bin2bcd(dt->tm_sec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) v3020_set_reg(chip, V3020_MINUTES, bin2bcd(dt->tm_min));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) v3020_set_reg(chip, V3020_HOURS, bin2bcd(dt->tm_hour));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) v3020_set_reg(chip, V3020_MONTH_DAY, bin2bcd(dt->tm_mday));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v3020_set_reg(chip, V3020_MONTH, bin2bcd(dt->tm_mon + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) v3020_set_reg(chip, V3020_WEEK_DAY, bin2bcd(dt->tm_wday));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) v3020_set_reg(chip, V3020_YEAR, bin2bcd(dt->tm_year % 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* ...and set the clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) v3020_set_reg(chip, V3020_CMD_RAM2CLOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Compulab used this delay here. I dont know why,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * the datasheet does not specify a delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*mdelay(5);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct rtc_class_ops v3020_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .read_time = v3020_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .set_time = v3020_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct v3020_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct v3020 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (pdata->use_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) chip->ops = &v3020_gpio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) chip->ops = &v3020_mmio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) retval = chip->ops->map_io(chip, pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Make sure the v3020 expects a communication cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * by reading 8 times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) chip->ops->read_bit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Test chip by doing a write/read sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * to the chip ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) v3020_set_reg(chip, V3020_SECONDS, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (v3020_get_reg(chip, V3020_SECONDS) != 0x33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto err_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Make sure frequency measurement mode, test modes, and lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * are all disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) v3020_set_reg(chip, V3020_STATUS_0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (pdata->use_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_info(&pdev->dev, "Chip available at GPIOs "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "%d, %d, %d, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) chip->gpio[V3020_CS].gpio, chip->gpio[V3020_WR].gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) chip->gpio[V3020_RD].gpio, chip->gpio[V3020_IO].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_info(&pdev->dev, "Chip available at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "physical address 0x%llx,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "data connected to D%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) (unsigned long long)pdev->resource[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) chip->leftshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) chip->rtc = devm_rtc_device_register(&pdev->dev, "v3020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &v3020_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(chip->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) retval = PTR_ERR(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto err_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) err_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) chip->ops->unmap_io(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int rtc_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct v3020 *chip = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) chip->ops->unmap_io(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct platform_driver rtc_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .probe = rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .remove = rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "v3020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) module_platform_driver(rtc_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DESCRIPTION("V3020 RTC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Raphael Assenat");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_ALIAS("platform:v3020");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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