^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TX4939 internal RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright TOSHIBA CORPORATION 2005-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TX4939_RTCCTL_ALME 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TX4939_RTCCTL_ALMD 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TX4939_RTCCTL_BUSY 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TX4939_RTCCTL_COMMAND 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TX4939_RTCCTL_COMMAND_NOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TX4939_RTCTBC_PM 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TX4939_RTCTBC_COMP 0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TX4939_RTC_REG_RAMSIZE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TX4939_RTC_REG_RWBSIZE 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct tx4939_rtc_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __u32 adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __u32 dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __u32 tbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct tx4939rtc_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct tx4939_rtc_reg __iomem *rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int tx4939_rtc_cmd(struct tx4939_rtc_reg __iomem *rtcreg, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __raw_writel(cmd, &rtcreg->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* This might take 30us (next 32.768KHz clock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) while (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* timeout on approx. 100us (@ GBUS200MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (i++ > 200 * 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int tx4939_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long secs = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned char buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) buf[2] = secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) buf[3] = secs >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) buf[4] = secs >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) buf[5] = secs >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __raw_writel(0, &rtcreg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __raw_writel(buf[i], &rtcreg->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = tx4939_rtc_cmd(rtcreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) TX4939_RTCCTL_COMMAND_SETTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int tx4939_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned char buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = tx4939_rtc_cmd(rtcreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) TX4939_RTCCTL_COMMAND_GETTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __raw_writel(2, &rtcreg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 2; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) buf[i] = __raw_readl(&rtcreg->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) sec = ((unsigned long)buf[5] << 24) | (buf[4] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (buf[3] << 8) | buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rtc_time64_to_tm(sec, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int tx4939_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned char buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sec = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) buf[2] = sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) buf[3] = sec >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) buf[4] = sec >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) buf[5] = sec >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __raw_writel(0, &rtcreg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __raw_writel(buf[i], &rtcreg->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = tx4939_rtc_cmd(rtcreg, TX4939_RTCCTL_COMMAND_SETALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (alrm->enabled ? TX4939_RTCCTL_ALME : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int tx4939_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = tx4939_rtc_cmd(rtcreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TX4939_RTCCTL_COMMAND_GETALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __raw_writel(2, &rtcreg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 2; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) buf[i] = __raw_readl(&rtcreg->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ctl = __raw_readl(&rtcreg->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) alrm->enabled = (ctl & TX4939_RTCCTL_ALME) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) alrm->pending = (ctl & TX4939_RTCCTL_ALMD) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sec = ((unsigned long)buf[5] << 24) | (buf[4] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (buf[3] << 8) | buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rtc_time64_to_tm(sec, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return rtc_valid_tm(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int tx4939_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tx4939_rtc_cmd(pdata->rtcreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) TX4939_RTCCTL_COMMAND_NOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (enabled ? TX4939_RTCCTL_ALME : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static irqreturn_t tx4939_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long events = RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALMD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) events |= RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tx4939_rtc_cmd(rtcreg, TX4939_RTCCTL_COMMAND_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spin_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rtc_update_irq(pdata->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct rtc_class_ops tx4939_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .read_time = tx4939_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .read_alarm = tx4939_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .set_alarm = tx4939_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .set_time = tx4939_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .alarm_irq_enable = tx4939_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int tx4939_nvram_read(void *priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct tx4939rtc_plat_data *pdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (; bytes; bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __raw_writel(pos++, &rtcreg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *buf++ = __raw_readl(&rtcreg->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int tx4939_nvram_write(void *priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct tx4939rtc_plat_data *pdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) for (; bytes; bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __raw_writel(pos++, &rtcreg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __raw_writel(*buf++, &rtcreg->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int __init tx4939_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct tx4939rtc_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "tx4939_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .size = TX4939_RTC_REG_RAMSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .reg_read = tx4939_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .reg_write = tx4939_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pdata->rtcreg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (IS_ERR(pdata->rtcreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return PTR_ERR(pdata->rtcreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_lock_init(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tx4939_rtc_cmd(pdata->rtcreg, TX4939_RTCCTL_COMMAND_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (devm_request_irq(&pdev->dev, irq, tx4939_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0, pdev->name, &pdev->dev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) rtc->ops = &tx4939_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pdata->rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) nvmem_cfg.priv = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = rtc_nvmem_register(rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int __exit tx4939_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct tx4939rtc_plat_data *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tx4939_rtc_cmd(pdata->rtcreg, TX4939_RTCCTL_COMMAND_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct platform_driver tx4939_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .remove = __exit_p(tx4939_rtc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .name = "tx4939rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) module_platform_driver_probe(tx4939_rtc_driver, tx4939_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("TX4939 internal RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_ALIAS("platform:tx4939rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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