^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rtc-twl.c -- TWL Real Time Clock interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 MontaVista Software, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Alexandre Rusev <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on original TI driver twl4030-rtc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2006 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on rtc-omap.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2003 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2006 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum twl_class {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) TWL_4030 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) TWL_6030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * RTC block register offsets (use TWL_MODULE_RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) REG_SECONDS_REG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) REG_MINUTES_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) REG_HOURS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) REG_DAYS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) REG_MONTHS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) REG_YEARS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) REG_WEEKS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) REG_ALARM_SECONDS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) REG_ALARM_MINUTES_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) REG_ALARM_HOURS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) REG_ALARM_DAYS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) REG_ALARM_MONTHS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) REG_ALARM_YEARS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) REG_RTC_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) REG_RTC_STATUS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) REG_RTC_INTERRUPTS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) REG_RTC_COMP_LSB_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) REG_RTC_COMP_MSB_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const u8 twl4030_rtc_reg_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [REG_SECONDS_REG] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [REG_MINUTES_REG] = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [REG_HOURS_REG] = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [REG_DAYS_REG] = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [REG_MONTHS_REG] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [REG_YEARS_REG] = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [REG_WEEKS_REG] = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [REG_ALARM_SECONDS_REG] = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [REG_ALARM_MINUTES_REG] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [REG_ALARM_HOURS_REG] = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [REG_ALARM_DAYS_REG] = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [REG_ALARM_MONTHS_REG] = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [REG_ALARM_YEARS_REG] = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [REG_RTC_CTRL_REG] = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [REG_RTC_STATUS_REG] = 0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [REG_RTC_INTERRUPTS_REG] = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [REG_RTC_COMP_LSB_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [REG_RTC_COMP_MSB_REG] = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const u8 twl6030_rtc_reg_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [REG_SECONDS_REG] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [REG_MINUTES_REG] = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [REG_HOURS_REG] = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [REG_DAYS_REG] = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [REG_MONTHS_REG] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [REG_YEARS_REG] = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [REG_WEEKS_REG] = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [REG_ALARM_SECONDS_REG] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [REG_ALARM_MINUTES_REG] = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [REG_ALARM_HOURS_REG] = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [REG_ALARM_DAYS_REG] = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [REG_ALARM_MONTHS_REG] = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [REG_ALARM_YEARS_REG] = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [REG_RTC_CTRL_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [REG_RTC_STATUS_REG] = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [REG_RTC_INTERRUPTS_REG] = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [REG_RTC_COMP_LSB_REG] = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [REG_RTC_COMP_MSB_REG] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* RTC_CTRL_REG bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* RTC_STATUS_REG bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BIT_RTC_STATUS_REG_RUN_M 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BIT_RTC_STATUS_REG_ALARM_M 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* RTC_INTERRUPTS_REG bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ALL_TIME_REGS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct twl_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 *reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Cache the value for timer/alarm interrupts register; this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * only changed by callers holding rtc ops lock (or resume).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char rtc_irq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool wake_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned char irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum twl_class class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Supports 1 byte read from TWL RTC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pr_err("Could not read TWL register %X - error %d\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Supports 1 byte write to TWL RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_err("Could not write TWL register %X - error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Enable 1/second update and/or alarm interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int set_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* if the bit is set, return from here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (twl_rtc->rtc_irq_bits & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = twl_rtc->rtc_irq_bits | bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) twl_rtc->rtc_irq_bits = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Disable update and/or alarm interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int mask_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* if the bit is clear, return from here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!(twl_rtc->rtc_irq_bits & bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = twl_rtc->rtc_irq_bits & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) twl_rtc->rtc_irq_bits = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = set_rtc_irq_bit(twl_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (device_can_wakeup(dev) && !twl_rtc->wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) twl_rtc->wake_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = mask_rtc_irq_bit(twl_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (twl_rtc->wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) disable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) twl_rtc->wake_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Gets current TWL RTC time and date parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * The RTC's time/alarm representation is not what gmtime(3) requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Linux to use:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * - Months are 1..12 vs Linux 0-11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned char rtc_data[ALL_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 save_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 rtc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (twl_rtc->class == TWL_6030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = twl_rtc_write_u8(twl_rtc, save_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(dev, "%s clr GET_TIME, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Copy RTC counting registers to static registers or latches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* for twl6030/32 enable read access to static shadowed registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (twl_rtc->class == TWL_6030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = twl_rtc_write_u8(twl_rtc, rtc_control, REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* for twl6030 restore original state of rtc control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (twl_rtc->class == TWL_6030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(dev, "%s: restore CTRL_REG, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tm->tm_sec = bcd2bin(rtc_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tm->tm_min = bcd2bin(rtc_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tm->tm_hour = bcd2bin(rtc_data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tm->tm_mday = bcd2bin(rtc_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tm->tm_year = bcd2bin(rtc_data[5]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned char save_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned char rtc_data[ALL_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) rtc_data[0] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) rtc_data[1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rtc_data[2] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rtc_data[3] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rtc_data[4] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rtc_data[5] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Stop RTC while updating the TC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* update all the time registers in one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(dev, "rtc_set_time error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Start back RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Gets current TWL RTC alarm time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned char rtc_data[ALL_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(dev, "rtc_read_alarm error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* some of these fields may be wildcard/"match all" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) alm->time.tm_sec = bcd2bin(rtc_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) alm->time.tm_min = bcd2bin(rtc_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) alm->time.tm_hour = bcd2bin(rtc_data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) alm->time.tm_mday = bcd2bin(rtc_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* report cached alarm enable state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (twl_rtc->rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) alm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned char alarm_data[ALL_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = twl_rtc_alarm_irq_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) alarm_data[0] = bin2bcd(alm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) alarm_data[1] = bin2bcd(alm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) alarm_data[2] = bin2bcd(alm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) alarm_data[3] = bin2bcd(alm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* update all the alarm registers in one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(dev, "rtc_set_alarm error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (alm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = twl_rtc_alarm_irq_enable(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static irqreturn_t twl_rtc_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct twl_rtc *twl_rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned long events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 rd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) res = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * only one (ALARM or RTC) interrupt source may be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * at time, we also could check our results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) events = RTC_IRQF | RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) events = RTC_IRQF | RTC_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) res = twl_rtc_write_u8(twl_rtc, BIT_RTC_STATUS_REG_ALARM_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) REG_RTC_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (twl_rtc->class == TWL_4030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * needs 2 reads to clear the interrupt. One read is done in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * do_twl_pwrirq(). Doing the second read, to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * FIXME the reason PWR_ISR1 needs an extra read is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * RTC_IF retriggered until we cleared REG_ALARM_M above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * But re-reading like this is a bad hack; by doing so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * risk wrongly clearing status for some other IRQ (losing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * the interrupt). Be smarter about handling RTC_UF ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) res = twl_i2c_read_u8(TWL4030_MODULE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &rd_reg, TWL4030_INT_PWR_ISR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Notify RTC core on event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rtc_update_irq(twl_rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct rtc_class_ops twl_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .read_time = twl_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .set_time = twl_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .read_alarm = twl_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .set_alarm = twl_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .alarm_irq_enable = twl_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int twl_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct twl_rtc *twl_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 rd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&pdev->dev, "no DT info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) twl_rtc = devm_kzalloc(&pdev->dev, sizeof(*twl_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!twl_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (twl_class_is_4030()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) twl_rtc->class = TWL_4030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) twl_rtc->reg_map = (u8 *)twl4030_rtc_reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } else if (twl_class_is_6030()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) twl_rtc->class = TWL_6030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) twl_rtc->reg_map = (u8 *)twl6030_rtc_reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(&pdev->dev, "TWL Class not supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_warn(&pdev->dev, "Power up reset detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Clear RTC Power up reset and pending alarm interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = twl_rtc_write_u8(twl_rtc, rd_reg, REG_RTC_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (twl_rtc->class == TWL_6030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) REG_INT_MSK_LINE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) REG_INT_MSK_STS_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_info(&pdev->dev, "Enabling TWL-RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = twl_rtc_write_u8(twl_rtc, BIT_RTC_CTRL_REG_STOP_RTC_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) REG_RTC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* ensure interrupts are disabled, bootloaders can be strange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = twl_rtc_write_u8(twl_rtc, 0, REG_RTC_INTERRUPTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_warn(&pdev->dev, "unable to disable interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* init cached IRQ enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = twl_rtc_read_u8(twl_rtc, &twl_rtc->rtc_irq_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) REG_RTC_INTERRUPTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) platform_set_drvdata(pdev, twl_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) twl_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &twl_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(twl_rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PTR_ERR(twl_rtc->rtc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return PTR_ERR(twl_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) twl_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_name(&twl_rtc->rtc->dev), twl_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(&pdev->dev, "IRQ is not free.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Disable all TWL RTC module interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Sets status flag to free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int twl_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* leave rtc running, but disable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (twl_rtc->class == TWL_6030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) REG_INT_MSK_LINE_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) REG_INT_MSK_STS_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void twl_rtc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* mask timer interrupts, but leave alarm interrupts on to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) power-on when alarm is triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int twl_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) twl_rtc->irqstat = twl_rtc->rtc_irq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int twl_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) set_rtc_irq_bit(twl_rtc, twl_rtc->irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct of_device_id twl_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {.compatible = "ti,twl4030-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static struct platform_driver twl4030rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .probe = twl_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .remove = twl_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .shutdown = twl_rtc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "twl_rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .pm = &twl_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .of_match_table = twl_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) module_platform_driver(twl4030rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MODULE_AUTHOR("Texas Instruments, MontaVista Software");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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