^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * rtc-tps80031.c -- TI TPS80031/TPS80032 RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * RTC driver for TI TPS80031/TPS80032 Fully Integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Power Management with Power Path and Battery Charger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 02111-1307, USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mfd/tps80031.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ENABLE_ALARM_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ALARM_INT_STATUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Setting bit to 1 in STOP_RTC will run the RTC and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * setting this bit to 0 will freeze RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STOP_RTC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Power on reset Values of RTC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TPS80031_RTC_POR_YEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TPS80031_RTC_POR_MONTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TPS80031_RTC_POR_DAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Numbers of registers for time and alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TPS80031_RTC_TIME_NUM_REGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TPS80031_RTC_ALARM_NUM_REGS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * PMU RTC have only 2 nibbles to store year information, so using an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * offset of 100 to set the base year as 2000 for our driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RTC_YEAR_OFFSET 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct tps80031_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int tps80031_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 buff[TPS80031_RTC_TIME_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = tps80031_reads(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TPS80031_SECONDS_REG, TPS80031_RTC_TIME_NUM_REGS, buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(dev, "reading RTC_SECONDS_REG failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) tm->tm_sec = bcd2bin(buff[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) tm->tm_min = bcd2bin(buff[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tm->tm_hour = bcd2bin(buff[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tm->tm_mday = bcd2bin(buff[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tm->tm_mon = bcd2bin(buff[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tm->tm_year = bcd2bin(buff[5]) + RTC_YEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tm->tm_wday = bcd2bin(buff[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int tps80031_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 buff[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) buff[0] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) buff[1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) buff[2] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) buff[3] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) buff[4] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) buff[5] = bin2bcd(tm->tm_year % RTC_YEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) buff[6] = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Stop RTC while updating the RTC time registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = tps80031_clr_bits(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) TPS80031_RTC_CTRL_REG, STOP_RTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(dev->parent, "Stop RTC failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = tps80031_writes(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TPS80031_SECONDS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) TPS80031_RTC_TIME_NUM_REGS, buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(dev, "writing RTC_SECONDS_REG failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = tps80031_set_bits(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) TPS80031_RTC_CTRL_REG, STOP_RTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(dev->parent, "Start RTC failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int tps80031_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = tps80031_set_bits(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) TPS80031_RTC_INTERRUPTS_REG, ENABLE_ALARM_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = tps80031_clr_bits(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TPS80031_RTC_INTERRUPTS_REG, ENABLE_ALARM_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(dev, "Update on RTC_INT failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int tps80031_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 buff[TPS80031_RTC_ALARM_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) buff[0] = bin2bcd(alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) buff[1] = bin2bcd(alrm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) buff[2] = bin2bcd(alrm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) buff[3] = bin2bcd(alrm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) buff[4] = bin2bcd(alrm->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) buff[5] = bin2bcd(alrm->time.tm_year % RTC_YEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = tps80031_writes(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TPS80031_ALARM_SECONDS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TPS80031_RTC_ALARM_NUM_REGS, buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(dev, "Writing RTC_ALARM failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return tps80031_rtc_alarm_irq_enable(dev, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int tps80031_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 buff[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = tps80031_reads(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) TPS80031_ALARM_SECONDS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TPS80031_RTC_ALARM_NUM_REGS, buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(dev->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "reading RTC_ALARM failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) alrm->time.tm_sec = bcd2bin(buff[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) alrm->time.tm_min = bcd2bin(buff[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) alrm->time.tm_hour = bcd2bin(buff[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) alrm->time.tm_mday = bcd2bin(buff[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) alrm->time.tm_mon = bcd2bin(buff[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) alrm->time.tm_year = bcd2bin(buff[5]) + RTC_YEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int clear_alarm_int_status(struct device *dev, struct tps80031_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * As per datasheet, A dummy read of this RTC_STATUS_REG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * is necessary before each I2C read in order to update the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = tps80031_read(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) TPS80031_RTC_STATUS_REG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "reading RTC_STATUS failed. err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* clear Alarm status bits.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = tps80031_set_bits(dev->parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) TPS80031_RTC_STATUS_REG, ALARM_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(dev, "clear Alarm INT failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static irqreturn_t tps80031_rtc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct tps80031_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = clear_alarm_int_status(dev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct rtc_class_ops tps80031_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .read_time = tps80031_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .set_time = tps80031_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .set_alarm = tps80031_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .read_alarm = tps80031_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .alarm_irq_enable = tps80031_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int tps80031_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct tps80031_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Start RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = tps80031_set_bits(pdev->dev.parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) TPS80031_RTC_CTRL_REG, STOP_RTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(&pdev->dev, "failed to start RTC. err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* If RTC have POR values, set time 01:01:2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tps80031_rtc_read_time(&pdev->dev, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if ((tm.tm_year == RTC_YEAR_OFFSET + TPS80031_RTC_POR_YEAR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (tm.tm_mon == (TPS80031_RTC_POR_MONTH - 1)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (tm.tm_mday == TPS80031_RTC_POR_DAY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tm.tm_year = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tm.tm_mday = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tm.tm_mon = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = tps80031_rtc_set_time(&pdev->dev, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "RTC set time failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Clear alarm intretupt status if it is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = clear_alarm_int_status(&pdev->dev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(&pdev->dev, "Clear alarm int failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) &tps80031_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (IS_ERR(rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_err(&pdev->dev, "RTC registration failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tps80031_rtc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_name(&pdev->dev), rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&pdev->dev, "request IRQ:%d failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) rtc->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) device_set_wakeup_capable(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int tps80031_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct tps80031_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) enable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int tps80031_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct tps80031_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) disable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static SIMPLE_DEV_PM_OPS(tps80031_pm_ops, tps80031_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tps80031_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct platform_driver tps80031_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = "tps80031-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .pm = &tps80031_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .probe = tps80031_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) module_platform_driver(tps80031_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_ALIAS("platform:tps80031-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_DESCRIPTION("TI TPS80031/TPS80032 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags