^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rtc-tps65910.c -- TPS65910 Real Time Clock interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Venu Byravarasu <vbyravarasu@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on original TI driver rtc-twl.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2007 MontaVista Software, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Alexandre Rusev <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/tps65910.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct tps65910_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Total number of RTC registers needed to set time*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NUM_TIME_REGS (TPS65910_YEARS - TPS65910_SECONDS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Total number of RTC registers needed to set compensation registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NUM_COMP_REGS (TPS65910_RTC_COMP_MSB - TPS65910_RTC_COMP_LSB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Min and max values supported with 'offset' interface (swapped sign) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MIN_OFFSET (-277761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_OFFSET (277778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Number of ticks per hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TICKS_PER_HOUR (32768 * 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Multiplier for ppb conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PPB_MULT (1000000000LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int tps65910_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val = TPS65910_RTC_INTERRUPTS_IT_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return regmap_write(tps->regmap, TPS65910_RTC_INTERRUPTS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Gets current tps65910 RTC time and date parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * The RTC's time/alarm representation is not what gmtime(3) requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Linux to use:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * - Months are 1..12 vs Linux 0-11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int tps65910_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned char rtc_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Copy RTC counting registers to static registers or latches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = regmap_update_bits(tps->regmap, TPS65910_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) TPS65910_RTC_CTRL_GET_TIME, TPS65910_RTC_CTRL_GET_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_err(dev, "RTC CTRL reg update failed with err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = regmap_bulk_read(tps->regmap, TPS65910_SECONDS, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(dev, "reading from RTC failed with err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tm->tm_sec = bcd2bin(rtc_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tm->tm_min = bcd2bin(rtc_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tm->tm_hour = bcd2bin(rtc_data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tm->tm_mday = bcd2bin(rtc_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tm->tm_year = bcd2bin(rtc_data[5]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int tps65910_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned char rtc_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) rtc_data[0] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rtc_data[1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rtc_data[2] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rtc_data[3] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rtc_data[4] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rtc_data[5] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Stop RTC while updating the RTC time registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = regmap_update_bits(tps->regmap, TPS65910_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TPS65910_RTC_CTRL_STOP_RTC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(dev, "RTC stop failed with err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* update all the time registers in one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = regmap_bulk_write(tps->regmap, TPS65910_SECONDS, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(dev, "rtc_set_time error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Start back RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = regmap_update_bits(tps->regmap, TPS65910_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) TPS65910_RTC_CTRL_STOP_RTC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(dev, "RTC start failed with err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Gets current tps65910 RTC alarm time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int tps65910_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned char alarm_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 int_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = regmap_bulk_read(tps->regmap, TPS65910_ALARM_SECONDS, alarm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(dev, "rtc_read_alarm error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) alm->time.tm_sec = bcd2bin(alarm_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) alm->time.tm_min = bcd2bin(alarm_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) alm->time.tm_hour = bcd2bin(alarm_data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) alm->time.tm_mday = bcd2bin(alarm_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) alm->time.tm_mon = bcd2bin(alarm_data[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) alm->time.tm_year = bcd2bin(alarm_data[5]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = regmap_read(tps->regmap, TPS65910_RTC_INTERRUPTS, &int_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (int_val & TPS65910_RTC_INTERRUPTS_IT_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) alm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int tps65910_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned char alarm_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = tps65910_rtc_alarm_irq_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) alarm_data[0] = bin2bcd(alm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) alarm_data[1] = bin2bcd(alm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) alarm_data[2] = bin2bcd(alm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) alarm_data[3] = bin2bcd(alm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* update all the alarm registers in one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_bulk_write(tps->regmap, TPS65910_ALARM_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) alarm_data, NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(dev, "rtc_set_alarm error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (alm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = tps65910_rtc_alarm_irq_enable(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int tps65910_rtc_set_calibration(struct device *dev, int calibration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char comp_data[NUM_COMP_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) s16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * TPS65910 uses two's complement 16 bit value for compensation for RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * crystal inaccuracies. One time every hour when seconds counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * increments from 0 to 1 compensation value will be added to internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * RTC counter value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Compensation value 0x7FFF is prohibited value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Valid range for compensation value: [-32768 .. 32766]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if ((calibration < -32768) || (calibration > 32766)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "RTC calibration value out of range: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) calibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) value = (s16)calibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) comp_data[0] = (u16)value & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) comp_data[1] = ((u16)value >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Update all the compensation registers in one shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = regmap_bulk_write(tps->regmap, TPS65910_RTC_COMP_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) comp_data, NUM_COMP_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev, "rtc_set_calibration error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Enable automatic compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = regmap_update_bits(tps->regmap, TPS65910_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TPS65910_RTC_CTRL_AUTO_COMP, TPS65910_RTC_CTRL_AUTO_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_err(dev, "auto_comp enable failed with error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int tps65910_rtc_get_calibration(struct device *dev, int *calibration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned char comp_data[NUM_COMP_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_read(tps->regmap, TPS65910_RTC_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* If automatic compensation is not enabled report back zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!(ctrl & TPS65910_RTC_CTRL_AUTO_COMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *calibration = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = regmap_bulk_read(tps->regmap, TPS65910_RTC_COMP_LSB, comp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) NUM_COMP_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(dev, "rtc_get_calibration error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) value = (u16)comp_data[0] | ((u16)comp_data[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *calibration = (s16)value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int tps65910_read_offset(struct device *dev, long *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int calibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) s64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = tps65910_rtc_get_calibration(dev, &calibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Convert from RTC calibration register format to ppb format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tmp = calibration * (s64)PPB_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tmp -= TICKS_PER_HOUR / 2LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tmp += TICKS_PER_HOUR / 2LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tmp = div_s64(tmp, TICKS_PER_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Offset value operates in negative way, so swap sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *offset = (long)-tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int tps65910_set_offset(struct device *dev, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int calibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) s64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Make sure offset value is within supported range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (offset < MIN_OFFSET || offset > MAX_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Convert from ppb format to RTC calibration register format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tmp = offset * (s64)TICKS_PER_HOUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tmp -= PPB_MULT / 2LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tmp += PPB_MULT / 2LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tmp = div_s64(tmp, PPB_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Offset value operates in negative way, so swap sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) calibration = (int)-tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = tps65910_rtc_set_calibration(dev, calibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static irqreturn_t tps65910_rtc_interrupt(int irq, void *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct device *dev = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct tps65910 *tps = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct tps65910_rtc *tps_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 rtc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = regmap_read(tps->regmap, TPS65910_RTC_STATUS, &rtc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (rtc_reg & TPS65910_RTC_STATUS_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) events = RTC_IRQF | RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = regmap_write(tps->regmap, TPS65910_RTC_STATUS, rtc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Notify RTC core on event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rtc_update_irq(tps_rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct rtc_class_ops tps65910_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .read_time = tps65910_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .set_time = tps65910_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .read_alarm = tps65910_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .set_alarm = tps65910_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .alarm_irq_enable = tps65910_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .read_offset = tps65910_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .set_offset = tps65910_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct rtc_class_ops tps65910_rtc_ops_noirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .read_time = tps65910_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .set_time = tps65910_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .read_offset = tps65910_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .set_offset = tps65910_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int tps65910_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct tps65910 *tps65910 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct tps65910_rtc *tps_rtc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 rtc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) tps65910 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tps_rtc = devm_kzalloc(&pdev->dev, sizeof(struct tps65910_rtc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!tps_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tps_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (IS_ERR(tps_rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return PTR_ERR(tps_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = regmap_read(tps65910->regmap, TPS65910_RTC_STATUS, &rtc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = regmap_write(tps65910->regmap, TPS65910_RTC_STATUS, rtc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_dbg(&pdev->dev, "Enabling rtc-tps65910.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Enable RTC digital power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = regmap_update_bits(tps65910->regmap, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DEVCTRL_RTC_PWDN_MASK, 0 << DEVCTRL_RTC_PWDN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rtc_reg = TPS65910_RTC_CTRL_STOP_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = regmap_write(tps65910->regmap, TPS65910_RTC_CTRL, rtc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) platform_set_drvdata(pdev, tps_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_warn(&pdev->dev, "Wake up is not possible as irq = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tps65910_rtc_interrupt, IRQF_TRIGGER_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_name(&pdev->dev), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tps_rtc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (irq != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) device_set_wakeup_capable(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tps_rtc->rtc->ops = &tps65910_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tps_rtc->rtc->ops = &tps65910_rtc_ops_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tps_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tps_rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return rtc_register_device(tps_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int tps65910_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct tps65910_rtc *tps_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) enable_irq_wake(tps_rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int tps65910_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct tps65910_rtc *tps_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) disable_irq_wake(tps_rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static SIMPLE_DEV_PM_OPS(tps65910_rtc_pm_ops, tps65910_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) tps65910_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct platform_driver tps65910_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .probe = tps65910_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "tps65910-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .pm = &tps65910_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) module_platform_driver(tps65910_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_ALIAS("platform:tps65910-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_AUTHOR("Venu Byravarasu <vbyravarasu@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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