^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010-2019, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_RTC_REG_BUSY 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_RTC_REG_SECONDS 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* When msec is read, the seconds are buffered into shadow seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_RTC_REG_MILLI_SECONDS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_RTC_REG_INTR_MASK 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* write 1 bits to clear status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_RTC_REG_INTR_STATUS 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* bits in INTR_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* bits in INTR_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct tegra_rtc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *base; /* NULL if not initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int irq; /* alarm and periodic IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * RTC hardware is busy when it is updating its values over AHB once every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * write. CPU is always free to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Wait for hardware to be ready for writing. This function tries to maximize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * the amount of time before the next update. It does this by waiting for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * RTC to become busy with its periodic update, then returning once the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * first becomes not busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * This periodic update (where the seconds and milliseconds are copied to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * function allows us to make some assumptions without introducing a race,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * because 250 us is plenty of time to read/write a value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int tegra_rtc_wait_while_busy(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int retries = 500; /* ~490 us is the worst case, ~250 us is best */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * First wait for the RTC to become busy. This is when it posts its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * updated seconds+msec registers to AHB side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) while (tegra_rtc_check_busy(info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!retries--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto retry_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* now we have about 250 us to manipulate registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) retry_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(dev, "write failed: retry count exceeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * RTC hardware copies seconds to shadow seconds when a read of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * milliseconds occurs. use a lock to keep other threads out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spin_lock_irqsave(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rtc_time64_to_tm(sec, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* convert tm to seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) sec = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* seconds only written if wait succeeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = tegra_rtc_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_vdbg(dev, "time read back as %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) readl(info->base + TEGRA_RTC_REG_SECONDS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 sec, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (sec == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* alarm is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) alarm->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* alarm is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) alarm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rtc_time64_to_tm(sec, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tegra_rtc_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) spin_lock_irqsave(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* read the original value, and OR in the flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (alarm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sec = rtc_tm_to_time64(&alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tegra_rtc_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_vdbg(dev, "alarm read back as %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* if successfully written and alarm is enabled ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tegra_rtc_alarm_irq_enable(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* disable alarm if 0 or write error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_vdbg(dev, "alarm disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tegra_rtc_alarm_irq_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!dev || !dev->driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long events = 0, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* clear the interrupt masks and status on any IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tegra_rtc_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spin_lock_irqsave(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* check if alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) events |= RTC_IRQF | RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* check if periodic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) events |= RTC_IRQF | RTC_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) rtc_update_irq(info->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct rtc_class_ops tegra_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .read_time = tegra_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .set_time = tegra_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .read_alarm = tegra_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .set_alarm = tegra_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .proc = tegra_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct of_device_id tegra_rtc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .compatible = "nvidia,tegra20-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int tegra_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct tegra_rtc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) info->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (IS_ERR(info->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return PTR_ERR(info->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) info->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) info->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (IS_ERR(info->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return PTR_ERR(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) info->rtc->ops = &tegra_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) info->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) info->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (IS_ERR(info->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* set context info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) info->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spin_lock_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* clear out the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = rtc_register_device(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int tegra_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct tegra_rtc_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int tegra_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tegra_rtc_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* only use ALARM0 as a wake source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) info->base + TEGRA_RTC_REG_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_vdbg(dev, "alarm sec = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) device_may_wakeup(dev), info->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* leave the alarms on as a wake source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enable_irq_wake(info->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int tegra_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct tegra_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) device_may_wakeup(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* alarms were left on as a wake source, turn them off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) disable_irq_wake(info->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void tegra_rtc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_vdbg(&pdev->dev, "disabling interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct platform_driver tegra_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .probe = tegra_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .remove = tegra_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .shutdown = tegra_rtc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "tegra_rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .of_match_table = tegra_rtc_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .pm = &tegra_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) module_platform_driver(tegra_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_DESCRIPTION("driver for Tegra internal RTC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags