^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An RTC driver for Allwinner A10/A20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SUNXI_LOSC_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUNXI_RTC_YMD 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUNXI_RTC_HMS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUNXI_ALRM_DHMS 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUNXI_ALRM_EN 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUNXI_ALRM_EN_CNT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUNXI_ALRM_IRQ_EN 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUNXI_ALRM_IRQ_STA 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUNXI_MASK_DH 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUNXI_MASK_SM 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUNXI_MASK_M 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUNXI_MASK_LY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUNXI_MASK_D 0x00000ffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUNXI_MASK_M 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) >> (shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Get date values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Get time values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Get alarm values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Set date values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Set time values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Set alarm values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Time unit conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SEC_IN_MIN 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SEC_IN_HOUR (60 * SEC_IN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SEC_IN_DAY (24 * SEC_IN_HOUR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * The year parameter passed to the driver is usually an offset relative to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * the year 1900. This macro is used to convert this offset to another one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * relative to the minimum year allowed by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SUNXI_YEAR_OFF(x) ((x)->min - 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * min and max year are arbitrary set considering the limited range of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * hardware register field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sunxi_rtc_data_year {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int min; /* min year allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int max; /* max year allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int mask; /* mask for the year field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned char leap_shift; /* bit shift to get the leap year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct sunxi_rtc_data_year data_year_param[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .min = 2010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .max = 2073,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .leap_shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .min = 1970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .max = 2225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .leap_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct sunxi_rtc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct sunxi_rtc_data_year *data_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void sunxi_rtc_setaie(unsigned int to, struct sunxi_rtc_dev *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 alrm_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 alrm_irq_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (to) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) alrm_val = readl(chip->base + SUNXI_ALRM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) alrm_val |= SUNXI_ALRM_EN_CNT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) chip->base + SUNXI_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel(alrm_val, chip->base + SUNXI_ALRM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct rtc_time *alrm_tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 alrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 alrm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) alrm = readl(chip->base + SUNXI_ALRM_DHMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) date = readl(chip->base + SUNXI_RTC_YMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) chip->data_year->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) alrm_tm->tm_mon -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * switch from (data_year->min)-relative offset to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * a (1900)-relative one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) wkalrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 date, time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * read again in case it changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) date = readl(chip->base + SUNXI_RTC_YMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) time = readl(chip->base + SUNXI_RTC_HMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (time != readl(chip->base + SUNXI_RTC_HMS)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) chip->data_year->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rtc_tm->tm_mon -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * switch from (data_year->min)-relative offset to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * a (1900)-relative one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct rtc_time *alrm_tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct rtc_time tm_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 alrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) time64_t diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long time_gap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long time_gap_day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long time_gap_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long time_gap_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = sunxi_rtc_gettime(dev, &tm_now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(dev, "Error in getting time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) diff = rtc_tm_sub(alrm_tm, &tm_now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (diff <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(dev, "Date to set in the past\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (diff > 255 * SEC_IN_DAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(dev, "Day must be in the range 0 - 255\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) time_gap = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) time_gap_day = time_gap / SEC_IN_DAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) time_gap -= time_gap_day * SEC_IN_DAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) time_gap_hour = time_gap / SEC_IN_HOUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) time_gap -= time_gap_hour * SEC_IN_HOUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) time_gap_min = time_gap / SEC_IN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) time_gap -= time_gap_min * SEC_IN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sunxi_rtc_setaie(0, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) writel(0, chip->base + SUNXI_ALRM_DHMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) usleep_range(100, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(alrm, chip->base + SUNXI_ALRM_DHMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sunxi_rtc_setaie(wkalrm->enabled, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int mask, unsigned int ms_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg = readl(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reg &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (reg == mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 date = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * the input rtc_tm->tm_year is the offset relative to 1900. We use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * allowed by the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) year = rtc_tm->tm_year + 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (year < chip->data_year->min || year > chip->data_year->max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(dev, "rtc only supports year in range %u - %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) chip->data_year->min, chip->data_year->max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rtc_tm->tm_mon += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) chip->data_year->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (is_leap_year(year))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(0, chip->base + SUNXI_RTC_HMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(0, chip->base + SUNXI_RTC_YMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(time, chip->base + SUNXI_RTC_HMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * After writing the RTC HH-MM-SS register, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * be cleared until the real writing operation is finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(dev, "Failed to set rtc time.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(date, chip->base + SUNXI_RTC_YMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * After writing the RTC YY-MM-DD register, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * be cleared until the real writing operation is finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(dev, "Failed to set rtc time.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sunxi_rtc_setaie(enabled, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct rtc_class_ops sunxi_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .read_time = sunxi_rtc_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .set_time = sunxi_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .read_alarm = sunxi_rtc_getalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .set_alarm = sunxi_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .alarm_irq_enable = sunxi_rtc_alarm_irq_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct of_device_id sunxi_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { .compatible = "allwinner,sun4i-a10-rtc", .data = &data_year_param[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int sunxi_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct sunxi_rtc_dev *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) chip->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) chip->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (IS_ERR(chip->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return PTR_ERR(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) chip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (IS_ERR(chip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) chip->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0, dev_name(&pdev->dev), chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(&pdev->dev, "Could not request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) chip->data_year = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!chip->data_year) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(&pdev->dev, "Unable to setup RTC data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* clear the alarm count value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel(0, chip->base + SUNXI_ALRM_DHMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* disable alarm, not generate irq pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) writel(0, chip->base + SUNXI_ALRM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* disable alarm week/cnt irq, unset to cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* clear alarm week/cnt irq pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SUNXI_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) chip->rtc->ops = &sunxi_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return rtc_register_device(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct platform_driver sunxi_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .probe = sunxi_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "sunxi-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .of_match_table = sunxi_rtc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) module_platform_driver(sunxi_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_DESCRIPTION("sunxi RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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