^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An RTC driver for Allwinner A31/A23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on rtc-sunxi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * An RTC driver for Allwinner A10/A20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN6I_LOSC_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUN6I_LOSC_CLK_PRESCAL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN6I_RTC_YMD 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN6I_RTC_HMS 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Alarm 0 (counter) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUN6I_ALRM_COUNTER 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUN6I_ALRM_CUR_VAL 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUN6I_ALRM_EN 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN6I_ALRM_EN_CNT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN6I_ALRM_IRQ_EN 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SUN6I_ALRM_IRQ_STA 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Alarm 1 (wall clock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SUN6I_ALRM1_EN 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SUN6I_ALRM1_IRQ_EN 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUN6I_ALRM1_IRQ_STA 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Alarm config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUN6I_ALARM_CONFIG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUN6I_LOSC_OUT_GATING 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Get date values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Get time values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Set date values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Set time values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * The year parameter passed to the driver is usually an offset relative to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * the year 1900. This macro is used to convert this offset to another one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * relative to the minimum year allowed by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * The year range is 1970 - 2033. This range is selected to match Allwinner's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * driver, even though it is somewhat limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SUN6I_YEAR_MIN 1970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * There are other differences between models, including:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * - number of GPIO pins that can be configured to hold a certain level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * - crypto-key related registers (H5, H6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * - boot process related (super standby, secondary processor entry address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * registers (R40, H6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * - SYS power domain controls (R40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * - DCXO controls (H6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * - RC oscillator calibration (H6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * These functions are not covered by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sun6i_rtc_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long rc_osc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int fixed_prescaler : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int has_prescaler : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int has_out_clk : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int export_iosc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int has_losc_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int has_auto_swt : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct sun6i_rtc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct sun6i_rtc_clk_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk_hw *int_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct clk *losc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct clk *ext_losc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct sun6i_rtc_dev *sun6i_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = readl(rtc->base + SUN6I_LOSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (val & SUN6I_LOSC_CTRL_EXT_OSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (rtc->data->fixed_prescaler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) parent_rate /= rtc->data->fixed_prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (rtc->data->has_prescaler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val &= GENMASK(4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return parent_rate / (val + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (index > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = readl(rtc->base + SUN6I_LOSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val |= SUN6I_LOSC_CTRL_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (rtc->data->has_losc_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(val, rtc->base + SUN6I_LOSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct clk_ops sun6i_rtc_osc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .recalc_rate = sun6i_rtc_osc_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .get_parent = sun6i_rtc_osc_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .set_parent = sun6i_rtc_osc_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void __init sun6i_rtc_clk_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct sun6i_rtc_clk_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct sun6i_rtc_dev *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ops = &sun6i_rtc_osc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = "losc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const char *iosc_name = "rtc-int-osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *clkout_name = "osc32k-out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const char *parents[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rtc->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!clk_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) kfree(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spin_lock_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (IS_ERR(rtc->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pr_crit("Can't map RTC registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg = SUN6I_LOSC_CTRL_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (rtc->data->has_auto_swt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Bypass auto-switch to int osc, on ext losc failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(reg, rtc->base + SUN6I_LOSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Switch to the external, more precise, oscillator, if present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (of_get_property(node, "clocks", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg |= SUN6I_LOSC_CTRL_EXT_OSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (rtc->data->has_losc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(reg, rtc->base + SUN6I_LOSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Yes, I know, this is ugly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sun6i_rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Only read IOSC name from device tree if it is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (rtc->data->export_iosc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) of_property_read_string_index(node, "clock-output-names", 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) &iosc_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) iosc_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rtc->data->rc_osc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 300000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (IS_ERR(rtc->int_osc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pr_crit("Couldn't register the internal oscillator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) parents[0] = clk_hw_get_name(rtc->int_osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* If there is no external oscillator, this will be NULL and ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) parents[1] = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rtc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) init.parent_names = parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* ... number of clock parents will be 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) init.num_parents = of_clk_get_parent_count(node) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) of_property_read_string_index(node, "clock-output-names", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rtc->losc = clk_register(NULL, &rtc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (IS_ERR(rtc->losc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_crit("Couldn't register the LOSC clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) of_property_read_string_index(node, "clock-output-names", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) &clkout_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0, rtc->base + SUN6I_LOSC_OUT_GATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (IS_ERR(rtc->ext_losc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pr_crit("Couldn't register the LOSC external gate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk_data->num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk_data->hws[0] = &rtc->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (rtc->data->export_iosc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clk_data->hws[2] = rtc->int_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk_data->num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clk_hw_unregister_fixed_rate(rtc->int_osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .has_prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sun6i_a31_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .has_prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .has_out_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sun8i_a23_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .rc_osc_rate = 16000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .fixed_prescaler = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .has_prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .has_out_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .export_iosc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sun8i_h3_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* As far as we are concerned, clocks for H5 are the same as H3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sun8i_h3_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .rc_osc_rate = 16000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .fixed_prescaler = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .has_prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .has_out_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .export_iosc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .has_losc_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .has_auto_swt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) sun50i_h6_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * The R40 user manual is self-conflicting on whether the prescaler is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * fixed or configurable. The clock diagram shows it as fixed, but there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * is also a configurable divider in the RTC block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .rc_osc_rate = 16000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .fixed_prescaler = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) sun8i_r40_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .rc_osc_rate = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .has_out_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sun8i_v3_rtc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spin_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) spin_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 alrm_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 alrm_irq_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 alrm_wake_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (to) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) alrm_val = SUN6I_ALRM_EN_CNT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) chip->base + SUN6I_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel(alrm_val, chip->base + SUN6I_ALRM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 date, time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * read again in case it changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) date = readl(chip->base + SUN6I_RTC_YMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) time = readl(chip->base + SUN6I_RTC_HMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) (time != readl(chip->base + SUN6I_RTC_HMS)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rtc_tm->tm_mon -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * switch from (data_year->min)-relative offset to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * a (1900)-relative one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rtc_tm->tm_year += SUN6I_YEAR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 alrm_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 alrm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rtc_time64_to_tm(chip->alarm, &wkalrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct rtc_time *alrm_tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct rtc_time tm_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long time_now = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned long time_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned long time_gap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = sun6i_rtc_gettime(dev, &tm_now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_err(dev, "Error in getting time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) time_set = rtc_tm_to_time64(alrm_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) time_now = rtc_tm_to_time64(&tm_now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (time_set <= time_now) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(dev, "Date to set in the past\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) time_gap = time_set - time_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (time_gap > U32_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_err(dev, "Date too far in the future\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sun6i_rtc_setaie(0, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) writel(0, chip->base + SUN6I_ALRM_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) usleep_range(100, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) chip->alarm = time_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sun6i_rtc_setaie(wkalrm->enabled, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned int mask, unsigned int ms_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) reg = readl(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) reg &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 date = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rtc_tm->tm_year -= SUN6I_YEAR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rtc_tm->tm_mon += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) date |= SUN6I_LEAP_SET_VALUE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Check whether registers are writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(dev, "rtc is still busy.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) writel(time, chip->base + SUN6I_RTC_HMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * After writing the RTC HH-MM-SS register, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * be cleared until the real writing operation is finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_err(dev, "Failed to set rtc time.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writel(date, chip->base + SUN6I_RTC_YMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * After writing the RTC YY-MM-DD register, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * be cleared until the real writing operation is finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(dev, "Failed to set rtc time.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) sun6i_rtc_setaie(enabled, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct rtc_class_ops sun6i_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .read_time = sun6i_rtc_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .set_time = sun6i_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .read_alarm = sun6i_rtc_getalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .set_alarm = sun6i_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Enable IRQ wake on suspend, to wake up from RTC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int sun6i_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) enable_irq_wake(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Disable IRQ wake on resume. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int sun6i_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) disable_irq_wake(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) sun6i_rtc_suspend, sun6i_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int sun6i_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct sun6i_rtc_dev *chip = sun6i_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) chip->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 0, dev_name(&pdev->dev), chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_err(&pdev->dev, "Could not request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* clear the alarm counter value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel(0, chip->base + SUN6I_ALRM_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* disable counter alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) writel(0, chip->base + SUN6I_ALRM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* disable counter alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* disable week alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) writel(0, chip->base + SUN6I_ALRM1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* disable week alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* clear counter alarm pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) chip->base + SUN6I_ALRM_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* clear week alarm pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) chip->base + SUN6I_ALRM1_IRQ_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* disable alarm wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) writel(0, chip->base + SUN6I_ALARM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clk_prepare_enable(chip->losc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) chip->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (IS_ERR(chip->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return PTR_ERR(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) chip->rtc->ops = &sun6i_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = rtc_register_device(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_info(&pdev->dev, "RTC enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * As far as RTC functionality goes, all models are the same. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * datasheets claim that different models have different number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * registers available for non-volatile storage, but experiments show
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * that all SoCs have 16 registers available for this purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const struct of_device_id sun6i_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { .compatible = "allwinner,sun6i-a31-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { .compatible = "allwinner,sun8i-a23-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { .compatible = "allwinner,sun8i-h3-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { .compatible = "allwinner,sun8i-r40-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { .compatible = "allwinner,sun8i-v3-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { .compatible = "allwinner,sun50i-h5-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { .compatible = "allwinner,sun50i-h6-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static struct platform_driver sun6i_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .probe = sun6i_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .name = "sun6i-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .of_match_table = sun6i_rtc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .pm = &sun6i_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) builtin_platform_driver(sun6i_rtc_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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