^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Amelie Delaunay <amelie.delaunay@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRIVER_NAME "stm32_rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* STM32_RTC_TR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STM32_RTC_TR_SEC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STM32_RTC_TR_SEC GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM32_RTC_TR_MIN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32_RTC_TR_MIN GENMASK(14, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32_RTC_TR_HOUR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32_RTC_TR_HOUR GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* STM32_RTC_DR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STM32_RTC_DR_DATE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STM32_RTC_DR_DATE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32_RTC_DR_MONTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32_RTC_DR_MONTH GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM32_RTC_DR_WDAY_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32_RTC_DR_WDAY GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32_RTC_DR_YEAR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STM32_RTC_DR_YEAR GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* STM32_RTC_CR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32_RTC_CR_FMT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32_RTC_CR_ALRAE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32_RTC_CR_ALRAIE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STM32_RTC_ISR_ALRAWF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32_RTC_ISR_INITS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STM32_RTC_ISR_RSF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STM32_RTC_ISR_INITF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STM32_RTC_ISR_INIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STM32_RTC_ISR_ALRAF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* STM32_RTC_PRER bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32_RTC_PRER_PRED_S_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32_RTC_PRER_PRED_A_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STM32_RTC_ALRMXR_SEC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STM32_RTC_ALRMXR_MIN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STM32_RTC_ALRMXR_HOUR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32_RTC_ALRMXR_PM BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STM32_RTC_ALRMXR_DATE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STM32_RTC_ALRMXR_WDSEL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STM32_RTC_ALRMXR_WDAY_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* STM32_RTC_SR/_SCR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STM32_RTC_SR_ALRA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* STM32_RTC_VERR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STM32_RTC_VERR_MINREV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STM32_RTC_VERR_MINREV GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STM32_RTC_VERR_MAJREV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* STM32_RTC_WPR key constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RTC_WPR_1ST_KEY 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RTC_WPR_2ND_KEY 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RTC_WPR_WRONG_KEY 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Max STM32 RTC register offset is 0x3FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UNDEF_REG 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct stm32_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct stm32_rtc_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 prer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 alrmar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 wpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 verr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct stm32_rtc_events {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 alra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct stm32_rtc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const struct stm32_rtc_registers regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct stm32_rtc_events events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool has_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool need_dbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool has_wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct stm32_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regmap *dbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int dbp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int dbp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *rtc_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct stm32_rtc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int irq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int wakeirq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int isr = readl_relaxed(rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!(isr & STM32_RTC_ISR_INITF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) isr |= STM32_RTC_ISR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel_relaxed(isr, rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * It takes around 2 rtc_ck clock cycles to enter in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * initialization phase mode (and have INITF flag set). As
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * slowest rtc_ck frequency may be 32kHz and highest should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 1MHz, we poll every 10 us with a timeout of 100ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return readl_relaxed_poll_timeout_atomic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rtc->base + regs->isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) isr, (isr & STM32_RTC_ISR_INITF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int isr = readl_relaxed(rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) isr &= ~STM32_RTC_ISR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel_relaxed(isr, rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int isr = readl_relaxed(rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) isr &= ~STM32_RTC_ISR_RSF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) writel_relaxed(isr, rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Wait for RSF to be set to ensure the calendar registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * synchronised, it takes around 2 rtc_ck clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (isr & STM32_RTC_ISR_RSF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rtc->data->clear_events(rtc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const struct stm32_rtc_events *evts = &rtc->data->events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int status, cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mutex_lock(&rtc->rtc_dev->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) status = readl_relaxed(rtc->base + regs->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cr = readl_relaxed(rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if ((status & evts->alra) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (cr & STM32_RTC_CR_ALRAIE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Alarm A flag - Alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Pass event to the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Clear event flags, otherwise new events won't be received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) stm32_rtc_clear_event_flags(rtc, evts->alra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mutex_unlock(&rtc->rtc_dev->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Convert rtc_time structure from bin to bcd format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void tm2bcd(struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tm->tm_sec = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tm->tm_min = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tm->tm_hour = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tm->tm_mday = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tm->tm_mon = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tm->tm_year = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Number of days since Sunday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * - on kernel side, 0=Sunday...6=Saturday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * - on rtc side, 0=invalid,1=Monday...7=Sunday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Convert rtc_time structure from bcd to bin format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void bcd2tm(struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tm->tm_sec = bcd2bin(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tm->tm_min = bcd2bin(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tm->tm_hour = bcd2bin(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tm->tm_mday = bcd2bin(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tm->tm_year = bcd2bin(tm->tm_year) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Number of days since Sunday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * - on kernel side, 0=Sunday...6=Saturday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * - on rtc side, 0=invalid,1=Monday...7=Sunday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tm->tm_wday %= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int tr, dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Time and Date in BCD format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tr = readl_relaxed(rtc->base + regs->tr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dr = readl_relaxed(rtc->base + regs->dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* We don't report tm_yday and tm_isdst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bcd2tm(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int tr, dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) tm2bcd(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Time in BCD format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Date in BCD format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) stm32_rtc_wpr_unlock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = stm32_rtc_enter_init_mode(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel_relaxed(tr, rtc->base + regs->tr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel_relaxed(dr, rtc->base + regs->dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) stm32_rtc_exit_init_mode(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = stm32_rtc_wait_sync(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) stm32_rtc_wpr_lock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const struct stm32_rtc_events *evts = &rtc->data->events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int alrmar, cr, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) alrmar = readl_relaxed(rtc->base + regs->alrmar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cr = readl_relaxed(rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) status = readl_relaxed(rtc->base + regs->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Date/day doesn't matter in Alarm comparison so alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * triggers every day
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tm->tm_mday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tm->tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Alarm is set to a day of week */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tm->tm_mday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) STM32_RTC_ALRMXR_WDAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tm->tm_wday %= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Alarm is set to a day of month */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tm->tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) STM32_RTC_ALRMXR_DATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Hours don't matter in Alarm comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tm->tm_hour = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) STM32_RTC_ALRMXR_HOUR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (alrmar & STM32_RTC_ALRMXR_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Minutes don't matter in Alarm comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) tm->tm_min = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) STM32_RTC_ALRMXR_MIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Seconds don't matter in Alarm comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tm->tm_sec = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) STM32_RTC_ALRMXR_SEC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bcd2tm(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) alrm->pending = (status & evts->alra) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const struct stm32_rtc_events *evts = &rtc->data->events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cr = readl_relaxed(rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) stm32_rtc_wpr_unlock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* We expose Alarm A to the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) writel_relaxed(cr, rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Clear event flags, otherwise new events won't be received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) stm32_rtc_clear_event_flags(rtc, evts->alra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) stm32_rtc_wpr_lock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int dr = readl_relaxed(rtc->base + regs->dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int tr = readl_relaxed(rtc->base + regs->tr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Assuming current date is M-D-Y H:M:S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * RTC alarm can't be set on a specific month and year.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * So the valid alarm range is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * with a specific case for December...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if ((((tm->tm_year > cur_year) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) (tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ((tm->tm_year == cur_year) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (tm->tm_mon <= cur_mon + 1))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ((tm->tm_mday > cur_day) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ((tm->tm_mday == cur_day) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ((tm->tm_hour > cur_hour) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (tm->tm_sec >= cur_sec))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int cr, isr, alrmar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tm2bcd(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * RTC alarm can't be set on a specific date, unless this date is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * up to the same day of month next month.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(dev, "Alarm can be set only on upcoming month.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) alrmar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* tm_year and tm_mon are not used because not supported by RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) STM32_RTC_ALRMXR_DATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* 24-hour format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) alrmar &= ~STM32_RTC_ALRMXR_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) STM32_RTC_ALRMXR_HOUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) STM32_RTC_ALRMXR_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) STM32_RTC_ALRMXR_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) stm32_rtc_wpr_unlock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Disable Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cr = readl_relaxed(rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cr &= ~STM32_RTC_CR_ALRAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writel_relaxed(cr, rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Poll Alarm write flag to be sure that Alarm update is allowed: it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * takes around 2 rtc_ck clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (isr & STM32_RTC_ISR_ALRAWF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(dev, "Alarm update not allowed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Write to Alarm register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writel_relaxed(alrmar, rtc->base + regs->alrmar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) stm32_rtc_alarm_irq_enable(dev, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) stm32_rtc_wpr_lock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct rtc_class_ops stm32_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .read_time = stm32_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .set_time = stm32_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .read_alarm = stm32_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .set_alarm = stm32_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Flags are cleared by writing 0 in RTC_ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rtc->base + regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct stm32_rtc_data stm32_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .has_pclk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .need_dbp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .has_wakeirq = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .tr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .dr = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .cr = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .isr = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .prer = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .alrmar = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .wpr = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .sr = 0x0C, /* set to ISR offset to ease alarm management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .scr = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .verr = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .alra = STM32_RTC_ISR_ALRAF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .clear_events = stm32_rtc_clear_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct stm32_rtc_data stm32h7_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .has_pclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .need_dbp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .has_wakeirq = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .tr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .dr = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .cr = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .isr = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .prer = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .alrmar = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .wpr = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .sr = 0x0C, /* set to ISR offset to ease alarm management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .scr = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .verr = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .alra = STM32_RTC_ISR_ALRAF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .clear_events = stm32_rtc_clear_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct stm32_rtc_registers regs = rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Flags are cleared by writing 1 in RTC_SCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel_relaxed(flags, rtc->base + regs.scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct stm32_rtc_data stm32mp1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .has_pclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .need_dbp = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .has_wakeirq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .tr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .dr = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .cr = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .prer = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .alrmar = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .wpr = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .sr = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .scr = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .verr = 0x3F4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .alra = STM32_RTC_SR_ALRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .clear_events = stm32mp1_rtc_clear_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct of_device_id stm32_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int stm32_rtc_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct stm32_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rate = clk_get_rate(rtc->rtc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pred_s = (rate / (pred_a + 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (((pred_s + 1) * (pred_a + 1)) == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Can't find a 1Hz, so give priority to RTC power consumption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * by choosing the higher possible value for prediv_a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pred_a = pred_a_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pred_s = (rate / (pred_a + 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_warn(&pdev->dev, "rtc_ck is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (rate < ((pred_a + 1) * (pred_s + 1))) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "fast" : "slow");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) stm32_rtc_wpr_unlock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = stm32_rtc_enter_init_mode(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "Can't enter in init mode. Prescaler config failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel_relaxed(prer, rtc->base + regs->prer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel_relaxed(prer, rtc->base + regs->prer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Force 24h time format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) cr = readl_relaxed(rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cr &= ~STM32_RTC_CR_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) writel_relaxed(cr, rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) stm32_rtc_exit_init_mode(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = stm32_rtc_wait_sync(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) stm32_rtc_wpr_lock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int stm32_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct stm32_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) const struct stm32_rtc_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rtc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (IS_ERR(rtc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return PTR_ERR(rtc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rtc->data = (struct stm32_rtc_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (rtc->data->need_dbp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (IS_ERR(rtc->dbp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(&pdev->dev, "no st,syscfg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return PTR_ERR(rtc->dbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 1, &rtc->dbp_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(&pdev->dev, "can't read DBP register offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 2, &rtc->dbp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_err(&pdev->dev, "can't read DBP register mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!rtc->data->has_pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rtc->pclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (IS_ERR(rtc->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(&pdev->dev, "no pclk clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return PTR_ERR(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (IS_ERR(rtc->rtc_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(&pdev->dev, "no rtc_ck clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return PTR_ERR(rtc->rtc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (rtc->data->has_pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = clk_prepare_enable(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = clk_prepare_enable(rtc->rtc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto err_no_rtc_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (rtc->data->need_dbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) regmap_update_bits(rtc->dbp, rtc->dbp_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rtc->dbp_mask, rtc->dbp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * After a system reset, RTC_ISR.INITS flag can be read to check if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * the calendar has been initialized or not. INITS flag is reset by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * power-on reset (no vbat, no power-supply). It is not reset if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * rtc_ck parent clock has changed (so RTC prescalers need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * changed). That's why we cannot rely on this flag to know if RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * init has to be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = stm32_rtc_init(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) rtc->irq_alarm = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (rtc->irq_alarm <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = rtc->irq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = device_init_wakeup(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (rtc->data->has_wakeirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (rtc->wakeirq_alarm > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) rtc->wakeirq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = rtc->wakeirq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (rtc->wakeirq_alarm == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &stm32_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (IS_ERR(rtc->rtc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = PTR_ERR(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Handle RTC alarm interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) stm32_rtc_alarm_irq, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pdev->name, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) rtc->irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * If INITS flag is reset (calendar year field set to 0x00), calendar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * must be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_warn(&pdev->dev, "Date/Time must be initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (regs->verr != UNDEF_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 ver = readl_relaxed(rtc->base + regs->verr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_info(&pdev->dev, "registered rev:%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) clk_disable_unprepare(rtc->rtc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) err_no_rtc_ck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (rtc->data->has_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk_disable_unprepare(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (rtc->data->need_dbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_pm_clear_wake_irq(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) device_init_wakeup(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int stm32_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct stm32_rtc *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) const struct stm32_rtc_registers *regs = &rtc->data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) unsigned int cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) stm32_rtc_wpr_unlock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) cr = readl_relaxed(rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) cr &= ~STM32_RTC_CR_ALRAIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) writel_relaxed(cr, rtc->base + regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) stm32_rtc_wpr_lock(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) clk_disable_unprepare(rtc->rtc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (rtc->data->has_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) clk_disable_unprepare(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Enable backup domain write protection if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (rtc->data->need_dbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_pm_clear_wake_irq(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) device_init_wakeup(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int stm32_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (rtc->data->has_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) clk_disable_unprepare(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return enable_irq_wake(rtc->irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int stm32_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct stm32_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (rtc->data->has_pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = clk_prepare_enable(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = stm32_rtc_wait_sync(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (rtc->data->has_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) clk_disable_unprepare(rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return disable_irq_wake(rtc->irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) stm32_rtc_suspend, stm32_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static struct platform_driver stm32_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .probe = stm32_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .remove = stm32_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .pm = &stm32_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .of_match_table = stm32_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) module_platform_driver(stm32_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags