Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * rtc-st-lpc.c - ST's LPC RTC, powered by the Low Power Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 STMicroelectronics Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: David Paris <david.paris@st.com> for STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *         Lee Jones <lee.jones@linaro.org> for STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Based on the original driver written by Stuart Menefy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <dt-bindings/mfd/st-lpc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Low Power Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LPC_LPT_LSB_OFF		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LPC_LPT_MSB_OFF		0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPC_LPT_START_OFF	0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Low Power Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LPC_LPA_LSB_OFF		0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LPC_LPA_MSB_OFF		0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LPC_LPA_START_OFF	0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* LPC as WDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LPC_WDT_OFF		0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LPC_WDT_FLAG_OFF	0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct st_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct rtc_wkalrm alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	bool irq_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	short irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void st_rtc_set_hw_alarm(struct st_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				unsigned long msb, unsigned long  lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static irqreturn_t st_rtc_handler(int this_irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct st_rtc *rtc = (struct st_rtc *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	rtc_update_irq(rtc->rtc_dev, 1, RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int st_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned long lpt_lsb, lpt_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long long lpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		lpt_msb = readl_relaxed(rtc->ioaddr + LPC_LPT_MSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		lpt_lsb = readl_relaxed(rtc->ioaddr + LPC_LPT_LSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	} while (readl_relaxed(rtc->ioaddr + LPC_LPT_MSB_OFF) != lpt_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	lpt = ((unsigned long long)lpt_msb << 32) | lpt_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	do_div(lpt, rtc->clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	rtc_time64_to_tm(lpt, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int st_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned long long lpt, secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	secs = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	lpt = (unsigned long long)secs * rtc->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int st_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	memcpy(wkalrm, &rtc->alarm, sizeof(struct rtc_wkalrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int st_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (enabled && !rtc->irq_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		enable_irq(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		rtc->irq_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	} else if (!enabled && rtc->irq_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		disable_irq(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		rtc->irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int st_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct rtc_time now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned long long now_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned long long alarm_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned long long lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	st_rtc_read_time(dev, &now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	now_secs = rtc_tm_to_time64(&now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	alarm_secs = rtc_tm_to_time64(&t->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	memcpy(&rtc->alarm, t, sizeof(struct rtc_wkalrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Now many secs to fire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	alarm_secs -= now_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	lpa = (unsigned long long)alarm_secs * rtc->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	st_rtc_set_hw_alarm(rtc, lpa >> 32, lpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	st_rtc_alarm_irq_enable(dev, t->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct rtc_class_ops st_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.read_time		= st_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.set_time		= st_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.read_alarm		= st_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.set_alarm		= st_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.alarm_irq_enable	= st_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int st_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct st_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	uint32_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ret = of_property_read_u32(np, "st,lpc-mode", &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dev_err(&pdev->dev, "An LPC mode must be provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* LPC can either run as a Clocksource or in RTC or WDT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (mode != ST_LPC_MODE_RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	rtc = devm_kzalloc(&pdev->dev, sizeof(struct st_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (IS_ERR(rtc->rtc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return PTR_ERR(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spin_lock_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	rtc->ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (IS_ERR(rtc->ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return PTR_ERR(rtc->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rtc->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (!rtc->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		dev_err(&pdev->dev, "IRQ missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = devm_request_irq(&pdev->dev, rtc->irq, st_rtc_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			       pdev->name, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		dev_err(&pdev->dev, "Failed to request irq %i\n", rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	enable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	disable_irq(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	rtc->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (IS_ERR(rtc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dev_err(&pdev->dev, "Unable to request clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return PTR_ERR(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	clk_prepare_enable(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rtc->clkrate = clk_get_rate(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!rtc->clkrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(&pdev->dev, "Unable to fetch clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	device_set_wakeup_capable(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	rtc->rtc_dev->ops = &st_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	rtc->rtc_dev->range_max = U64_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	do_div(rtc->rtc_dev->range_max, rtc->clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = rtc_register_device(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		clk_disable_unprepare(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int st_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int st_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct st_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	rtc_alarm_irq_enable(rtc->rtc_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 * clean 'rtc->alarm' to allow a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 * .set_alarm to the upper RTC layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	memset(&rtc->alarm, 0, sizeof(struct rtc_wkalrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	writel_relaxed(0, rtc->ioaddr + LPC_LPA_MSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	writel_relaxed(0, rtc->ioaddr + LPC_LPA_LSB_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static SIMPLE_DEV_PM_OPS(st_rtc_pm_ops, st_rtc_suspend, st_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct of_device_id st_rtc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ .compatible = "st,stih407-lpc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DEVICE_TABLE(of, st_rtc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_driver st_rtc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.name = "st-lpc-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.pm = &st_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.of_match_table = st_rtc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.probe = st_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) module_platform_driver(st_rtc_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_DESCRIPTION("STMicroelectronics LPC RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_AUTHOR("David Paris <david.paris@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_LICENSE("GPL");