^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SNVS_LPREGISTER_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* These register offsets are relative to LP (Low Power) range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SNVS_LPCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SNVS_LPSR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SNVS_LPSRTCMR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SNVS_LPSRTCLR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SNVS_LPTAR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SNVS_LPPGDR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SNVS_LPCR_SRTC_ENV (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SNVS_LPCR_LPTA_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SNVS_LPCR_LPWUI_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SNVS_LPSR_LPTA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SNVS_LPPGDR_INIT 0x41736166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CNTR_TO_SECS_SH 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct snvs_rtc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Read 64 bit timer register, which could be in inconsistent state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 msb, lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return (u64)msb << 32 | lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Read the secure real time counter, taking care to deal with the cases of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * counter updating while being read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u64 read1, read2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* As expected, the registers might update between the read of the LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * reg and the MSB reg. It's also possible that one register might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * in partially modified state as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) read1 = rtc_read_lpsrt(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) read2 = read1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) read1 = rtc_read_lpsrt(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } while (read1 != read2 && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Convert 47-bit counter to 32-bit raw second count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return (u32) (read1 >> CNTR_TO_SECS_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Just read the lsb from the counter, dealing with inconsistent state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 count1, count2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) count2 = count1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } while (count1 != count2 && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *lsb = count1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int rtc_write_sync_lp(struct snvs_rtc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 count1, count2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = rtc_read_lp_counter_lsb(data, &count1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = rtc_read_lp_counter_lsb(data, &count2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) elapsed = count2 - count1; /* wrap around _is_ handled! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } while (elapsed < 3 && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 lpcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enable ? SNVS_LPCR_SRTC_ENV : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (lpcr & SNVS_LPCR_SRTC_ENV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!(lpcr & SNVS_LPCR_SRTC_ENV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (data->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) time = rtc_read_lp_counter(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rtc_time64_to_tm(time, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long time = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (data->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Disable RTC first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = snvs_rtc_enable(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Enable RTC again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = snvs_rtc_enable(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 lptar, lpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (data->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rtc_time64_to_tm(lptar, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (data->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = rtc_write_sync_lp(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long time = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (data->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = rtc_write_sync_lp(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Clear alarm interrupt status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct rtc_class_ops snvs_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .read_time = snvs_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .set_time = snvs_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .read_alarm = snvs_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .set_alarm = snvs_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 lpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (lpsr & SNVS_LPSR_LPTA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) events |= (RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* RTC alarm should be one-shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) snvs_rtc_alarm_irq_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rtc_update_irq(data->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return events ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct regmap_config snvs_rtc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void snvs_rtc_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int snvs_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct snvs_rtc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) data->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(data->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return PTR_ERR(data->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mmio = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (IS_ERR(mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return PTR_ERR(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data->offset = SNVS_LPREGISTER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(&pdev->dev, "Can't find snvs syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (data->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (IS_ERR(data->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "Could not prepare or enable the snvs clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Initialize glitch detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Enable RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = snvs_rtc_enable(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) device_init_wakeup(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&pdev->dev, "failed to enable irq wake\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) IRQF_SHARED, "rtc alarm", &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(&pdev->dev, "failed to request irq %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) data->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) data->rtc->ops = &snvs_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return rtc_register_device(data->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk_disable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct snvs_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return clk_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct dev_pm_ops snvs_rtc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct of_device_id snvs_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_DEVICE_TABLE(of, snvs_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct platform_driver snvs_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "snvs_rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .pm = &snvs_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .of_match_table = snvs_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .probe = snvs_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) module_platform_driver(snvs_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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