^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SiRFSoC Real Time Clock interface for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rtc/sirfsoc_rtciobrg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTC_CN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTC_ALARM0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTC_ALARM1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTC_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RTC_SW_VALUE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIRFSOC_RTC_AL1E (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIRFSOC_RTC_AL1 (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIRFSOC_RTC_HZE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_RTC_AL0E (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIRFSOC_RTC_HZ (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIRFSOC_RTC_AL0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTC_DIV 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTC_DEEP_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTC_CLOCK_SWITCH 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Refer to RTC DIV switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTC_HZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define INTR_SYSRTC_CN 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct sirfsoc_rtc_drv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 rtc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned irq_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Overflow for every 8 years extra time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 overflow_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 saved_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 saved_overflow_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int sirfsoc_rtc_read_alarm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long rtc_alarm, rtc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct sirfsoc_rtc_drv *rtcdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spin_lock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) memset(alrm, 0, sizeof(struct rtc_wkalrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * assume alarm interval not beyond one round counter overflow_rtc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 0->0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* if alarm is in next overflow cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (rtc_count > rtc_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rtc_time64_to_tm((rtcdrv->overflow_rtc + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) << (BITS_PER_LONG - RTC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) | rtc_alarm >> RTC_SHIFT, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) rtc_time64_to_tm(rtcdrv->overflow_rtc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) << (BITS_PER_LONG - RTC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) | rtc_alarm >> RTC_SHIFT, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_unlock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int sirfsoc_rtc_set_alarm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long rtc_status_reg, rtc_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct sirfsoc_rtc_drv *rtcdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rtc_alarm = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_lock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * An ongoing alarm in progress - ingore it and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * to return EBUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rtc_status_reg &= ~0x07; /* mask out the lower status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * This bit RTC_AL sets it as a wake-up source for Sleep Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Writing 1 into this bit will clear it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rtc_status_reg |= SIRFSOC_RTC_AL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* enable the RTC alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rtc_status_reg |= SIRFSOC_RTC_AL0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) spin_unlock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * if this function was called with enabled=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * then it could mean that the application is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * trying to cancel an ongoing alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_lock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* clear the RTC status register's alarm bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rtc_status_reg &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* write 1 into SIRFSOC_RTC_AL0 to force a clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rtc_status_reg |= (SIRFSOC_RTC_AL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Clear the Alarm enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rtc_status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spin_unlock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int sirfsoc_rtc_read_time(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long tmp_rtc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct sirfsoc_rtc_drv *rtcdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * This patch is taken from WinCE - Need to validate this for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * correctness. To work around sirfsoc RTC counter double sync logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * fail, read several times to make sure get stable value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rtc_time64_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) | tmp_rtc >> RTC_SHIFT, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int sirfsoc_rtc_set_time(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long rtc_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct sirfsoc_rtc_drv *rtcdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rtc_time = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long rtc_status_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct sirfsoc_rtc_drv *rtcdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_lock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) rtc_status_reg |= SIRFSOC_RTC_AL0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spin_unlock_irq(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct rtc_class_ops sirfsoc_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .read_time = sirfsoc_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .set_time = sirfsoc_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .read_alarm = sirfsoc_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .set_alarm = sirfsoc_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct sirfsoc_rtc_drv *rtcdrv = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long rtc_status_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long events = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spin_lock(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* this bit will be set ONLY if an alarm was active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * and it expired NOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * So this is being used as an ASSERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (rtc_status_reg & SIRFSOC_RTC_AL0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * clear the RTC status register's alarm bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * mask out the lower status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rtc_status_reg &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) rtc_status_reg |= (SIRFSOC_RTC_AL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Clear the Alarm enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* this should wake up any apps polling/waiting on the read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * after setting the alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) events |= RTC_IRQF | RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rtc_update_irq(rtcdrv->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct of_device_id sirfsoc_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .compatible = "sirf,prima2-sysrtc"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct regmap_config sysrtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int sirfsoc_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned long rtc_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct sirfsoc_rtc_drv *rtcdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rtcdrv = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (rtcdrv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_lock_init(&rtcdrv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) platform_set_drvdata(pdev, rtcdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Register rtc alarm as a wakeup source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) &sysrtc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (IS_ERR(rtcdrv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) err = PTR_ERR(rtcdrv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Set SYS_RTC counter in RTC_HZ HZ Units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * If 16HZ, therefore RTC_DIV = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rtc_div = ((32768 / RTC_HZ) / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* 0x3 -> RTC_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* reset SYS RTC ALARM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* reset SYS RTC ALARM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Restore RTC Overflow From Register After Command Reboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rtcdrv->overflow_rtc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (IS_ERR(rtcdrv->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return PTR_ERR(rtcdrv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rtcdrv->rtc->ops = &sirfsoc_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rtcdrv->rtc->range_max = (1ULL << 60) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rtcdrv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = devm_request_irq(&pdev->dev, rtcdrv->irq, sirfsoc_rtc_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) IRQF_SHARED, pdev->name, rtcdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return rtc_register_device(rtcdrv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int sirfsoc_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rtcdrv->overflow_rtc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rtcdrv->saved_counter =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sirfsoc_rtc_readl(rtcdrv, RTC_CN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rtcdrv->irq_wake = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int sirfsoc_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * if resume from snapshot and the rtc power is lost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * restroe the rtc settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 rtc_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* 0x3 -> RTC_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Set SYS_RTC counter in RTC_HZ HZ Units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * If 16HZ, therefore RTC_DIV = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rtc_div = ((32768 / RTC_HZ) / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* reset SYS RTC ALARM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* reset SYS RTC ALARM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * if current counter is small than previous,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * it means overflow in sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (tmp <= rtcdrv->saved_counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rtcdrv->overflow_rtc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *PWRC Value Be Changed When Suspend, Restore Overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * In Memory To Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) disable_irq_wake(rtcdrv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rtcdrv->irq_wake = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct platform_driver sirfsoc_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "sirfsoc-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pm = &sirfsoc_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .of_match_table = sirfsoc_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .probe = sirfsoc_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) module_platform_driver(sirfsoc_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_DESCRIPTION("SiRF SoC rtc driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_ALIAS("platform:sirfsoc-rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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