^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH On-Chip RTC Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 - 2009 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Jamie Lenehan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Angelo Castello
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on the old arch/sh/kernel/cpu/rtc.c by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Default values for RZ/A RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define rtc_reg_size sizeof(u16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTC_BIT_INVERTED 0 /* no chip bugs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTC_CAP_4_DIGIT_YEAR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_NAME "sh-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTC_REG(r) ((r) * rtc_reg_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R64CNT RTC_REG(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RSECCNT RTC_REG(1) /* RTC sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RMINCNT RTC_REG(2) /* RTC min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RHRCNT RTC_REG(3) /* RTC hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RWKCNT RTC_REG(4) /* RTC week */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RDAYCNT RTC_REG(5) /* RTC day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RMONCNT RTC_REG(6) /* RTC month */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RYRCNT RTC_REG(7) /* RTC year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RSECAR RTC_REG(8) /* ALARM sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RMINAR RTC_REG(9) /* ALARM min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RHRAR RTC_REG(10) /* ALARM hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RWKAR RTC_REG(11) /* ALARM week */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RDAYAR RTC_REG(12) /* ALARM day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RMONAR RTC_REG(13) /* ALARM month */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RCR1 RTC_REG(14) /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RCR2 RTC_REG(15) /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Note on RYRAR and RCR3: Up until this point most of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * definitions are consistent across all of the available parts. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the placement of the optional RYRAR and RCR3 (the RYRAR control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * register used to control RYRCNT/RYRAR compare) varies considerably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * across various parts, occasionally being mapped in to a completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * unrelated address space. For proper RYRAR support a separate resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * would have to be handed off, but as this is purely optional in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * practice, we simply opt not to support it, thereby keeping the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * quite a bit more simplified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ALARM Bits - or with BCD encoded value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AR_ENB 0x80 /* Enable for alarm cmp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Period Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PF_COUNT 0x200 /* Half periodic counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PF_OXS 0x400 /* Periodic One x Second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PF_MASK 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* RCR1 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RCR1_CF 0x80 /* Carry Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RCR1_AF 0x01 /* Alarm Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* RCR2 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RCR2_RTCEN 0x08 /* ENable RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RCR2_RESET 0x02 /* Reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RCR2_START 0x01 /* Start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sh_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long regsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int periodic_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int carry_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long capabilities; /* See asm/rtc.h for cap bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned short periodic_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int __sh_rtc_interrupt(struct sh_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int tmp, pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmp = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pending = tmp & RCR1_CF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tmp &= ~RCR1_CF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writeb(tmp, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Users have requested One x Second IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (pending && rtc->periodic_freq & PF_OXS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int __sh_rtc_alarm(struct sh_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int tmp, pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tmp = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pending = tmp & RCR1_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tmp &= ~(RCR1_AF | RCR1_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writeb(tmp, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int __sh_rtc_periodic(struct sh_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int tmp, pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tmp = readb(rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pending = tmp & RCR2_PEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tmp &= ~RCR2_PEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writeb(tmp, rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Half period enabled than one skipped and the next notified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rtc->periodic_freq &= ~PF_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (rtc->periodic_freq & PF_HP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rtc->periodic_freq |= PF_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sh_rtc *rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spin_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = __sh_rtc_interrupt(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) spin_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct sh_rtc *rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spin_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = __sh_rtc_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct sh_rtc *rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = __sh_rtc_periodic(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spin_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct sh_rtc *rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spin_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = __sh_rtc_interrupt(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret |= __sh_rtc_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret |= __sh_rtc_periodic(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tmp = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tmp |= RCR1_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tmp &= ~RCR1_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writeb(tmp, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tmp = readb(rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) seq_printf(seq, "periodic_IRQ\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (tmp & RCR2_PESMASK) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tmp = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tmp &= ~RCR1_CIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tmp |= RCR1_CIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writeb(tmp, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sh_rtc_setaie(dev, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int sec128, sec2, yr, yr100, cf_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tmp = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) tmp &= ~RCR1_CF; /* Clear CF-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tmp |= RCR1_CIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writeb(tmp, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sec128 = readb(rtc->regbase + R64CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) yr = readw(rtc->regbase + RYRCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) yr100 = bcd2bin(yr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) yr &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) yr = readb(rtc->regbase + RYRCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sec2 = readb(rtc->regbase + R64CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #if RTC_BIT_INVERTED != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if ((sec128 & RTC_BIT_INVERTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tm->tm_sec--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* only keep the carry interrupt enabled if UIE is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!(rtc->periodic_freq & PF_OXS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sh_rtc_setcie(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) tm->tm_sec, tm->tm_min, tm->tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Reset pre-scaler & stop RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tmp = readb(rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tmp |= RCR2_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmp &= ~RCR2_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writeb(tmp, rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writew(year, rtc->regbase + RYRCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) year = tm->tm_year % 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writeb(bin2bcd(year), rtc->regbase + RYRCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Start RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tmp = readb(rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tmp &= ~RCR2_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tmp |= RCR2_RTCEN | RCR2_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writeb(tmp, rtc->regbase + RCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int value = -1; /* return -1 for ignored values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) byte = readb(rtc->regbase + reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (byte & AR_ENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) byte &= ~AR_ENB; /* strip the enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) value = bcd2bin(byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct rtc_time *tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (tm->tm_mon > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int value, int reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* < 0 for a value that is ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writeb(0, rtc->regbase + reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int rcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct rtc_time *tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* disable alarm interrupt and clear the alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rcr1 = readb(rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rcr1 &= ~(RCR1_AF | RCR1_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writeb(rcr1, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* set alarm time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mon = tm->tm_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (mon >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mon += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sh_rtc_write_alarm_value(rtc, mon, RMONAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (wkalrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rcr1 |= RCR1_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writeb(rcr1, rtc->regbase + RCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct rtc_class_ops sh_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .read_time = sh_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .set_time = sh_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .read_alarm = sh_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .set_alarm = sh_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .proc = sh_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .alarm_irq_enable = sh_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int __init sh_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sh_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) char clk_name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int clk_id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (unlikely(!rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spin_lock_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* get periodic/carry/alarm irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (unlikely(ret <= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(&pdev->dev, "No IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rtc->periodic_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rtc->carry_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rtc->alarm_irq = platform_get_irq(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (unlikely(res == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&pdev->dev, "No IO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rtc->regsize = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rtc->res = devm_request_mem_region(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rtc->regsize, pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (unlikely(!rtc->res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) rtc->regbase = devm_ioremap(&pdev->dev, rtc->res->start, rtc->regsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (unlikely(!rtc->regbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk_id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* With a single device, the clock id is still "rtc0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (clk_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) snprintf(clk_name, sizeof(clk_name), "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rtc->clk = devm_clk_get(&pdev->dev, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (IS_ERR(rtc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * No error handling for rtc->clk intentionally, not all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * platforms will have a unique clock for the RTC, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * the clk API can handle the struct clk pointer being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rtc->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(rtc->rtc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return PTR_ERR(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clk_enable(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) rtc->capabilities = RTC_DEF_CAPABILITIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (dev_get_platdata(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct sh_rtc_platform_info *pinfo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Some CPUs have special capabilities in addition to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * default set. Add those in here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) rtc->capabilities |= pinfo->capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (rtc->carry_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* register shared periodic/carry/alarm irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sh_rtc_shared, 0, "sh-rtc", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "request IRQ failed with %d, IRQ %d\n", ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rtc->periodic_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* register periodic/carry/alarm irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sh_rtc_periodic, 0, "sh-rtc period", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "request period IRQ failed with %d, IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret, rtc->periodic_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "request carry IRQ failed with %d, IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret, rtc->carry_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "request alarm IRQ failed with %d, IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret, rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* everything disabled by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sh_rtc_setaie(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sh_rtc_setcie(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) rtc->rtc_dev->ops = &sh_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) rtc->rtc_dev->max_user_freq = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_9999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) rtc->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rtc->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = rtc_register_device(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) clk_disable(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int __exit sh_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct sh_rtc *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sh_rtc_setaie(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) sh_rtc_setcie(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_disable(rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct sh_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) irq_set_irq_wake(rtc->periodic_irq, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (rtc->carry_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) irq_set_irq_wake(rtc->carry_irq, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) irq_set_irq_wake(rtc->alarm_irq, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int __maybe_unused sh_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) sh_rtc_set_irq_wake(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int __maybe_unused sh_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) sh_rtc_set_irq_wake(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static const struct of_device_id sh_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { .compatible = "renesas,sh-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static struct platform_driver sh_rtc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .pm = &sh_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .of_match_table = sh_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .remove = __exit_p(sh_rtc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MODULE_DESCRIPTION("SuperH on-chip RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "Jamie Lenehan <lenehan@twibble.org>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "Angelo Castello <angelo.castello@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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