Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Real Time Clock (RTC) Driver for sd3078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018 Zoro Li
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SD3078_REG_SC			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define SD3078_REG_MN			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SD3078_REG_HR			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SD3078_REG_DW			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SD3078_REG_DM			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SD3078_REG_MO			0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SD3078_REG_YR			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SD3078_REG_CTRL1		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SD3078_REG_CTRL2		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SD3078_REG_CTRL3		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define KEY_WRITE1		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define KEY_WRITE2		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define KEY_WRITE3		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define NUM_TIME_REGS   (SD3078_REG_YR - SD3078_REG_SC + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * The sd3078 has write protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * and we can choose whether or not to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * Write protection is turned off by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WRITE_PROTECT_EN	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct sd3078 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct rtc_device	*rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct regmap		*regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * In order to prevent arbitrary modification of the time register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * when modification of the register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * the "write" bit needs to be written in a certain order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * 1. set WRITE1 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * 2. set WRITE2 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * 3. set WRITE3 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void sd3078_enable_reg_write(struct sd3078 *sd3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			   KEY_WRITE1, KEY_WRITE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			   KEY_WRITE2, KEY_WRITE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			   KEY_WRITE3, KEY_WRITE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #if WRITE_PROTECT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * In order to prevent arbitrary modification of the time register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * we should disable the write function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * when disable write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * the "write" bit needs to be clear in a certain order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * 1. clear WRITE2 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * 2. clear WRITE3 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * 3. clear WRITE1 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void sd3078_disable_reg_write(struct sd3078 *sd3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			   KEY_WRITE2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			   KEY_WRITE3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			   KEY_WRITE1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int sd3078_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned char hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned char rtc_data[NUM_TIME_REGS] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct sd3078 *sd3078 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ret = regmap_bulk_read(sd3078->regmap, SD3078_REG_SC, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			       NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		dev_err(dev, "reading from RTC failed with err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	tm->tm_sec	= bcd2bin(rtc_data[SD3078_REG_SC] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	tm->tm_min	= bcd2bin(rtc_data[SD3078_REG_MN] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * The sd3078 supports 12/24 hour mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * When getting time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * we need to convert the 12 hour mode to the 24 hour mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	hour = rtc_data[SD3078_REG_HR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (hour & 0x80) /* 24H MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		tm->tm_hour = bcd2bin(rtc_data[SD3078_REG_HR] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	else if (hour & 0x20) /* 12H MODE PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		tm->tm_hour = bcd2bin(rtc_data[SD3078_REG_HR] & 0x1F) + 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	else /* 12H MODE AM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		tm->tm_hour = bcd2bin(rtc_data[SD3078_REG_HR] & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	tm->tm_mday = bcd2bin(rtc_data[SD3078_REG_DM] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	tm->tm_wday = rtc_data[SD3078_REG_DW] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	tm->tm_mon	= bcd2bin(rtc_data[SD3078_REG_MO] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	tm->tm_year = bcd2bin(rtc_data[SD3078_REG_YR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int sd3078_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned char rtc_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct sd3078 *sd3078 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	rtc_data[SD3078_REG_SC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	rtc_data[SD3078_REG_MN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	rtc_data[SD3078_REG_HR] = bin2bcd(tm->tm_hour) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	rtc_data[SD3078_REG_DM] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	rtc_data[SD3078_REG_DW] = tm->tm_wday & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	rtc_data[SD3078_REG_MO] = bin2bcd(tm->tm_mon) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	rtc_data[SD3078_REG_YR] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #if WRITE_PROTECT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	sd3078_enable_reg_write(sd3078);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret = regmap_bulk_write(sd3078->regmap, SD3078_REG_SC, rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		dev_err(dev, "writing to RTC failed with err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #if WRITE_PROTECT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	sd3078_disable_reg_write(sd3078);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct rtc_class_ops sd3078_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.read_time	= sd3078_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.set_time	= sd3078_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.max_register = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int sd3078_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct sd3078 *sd3078;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	sd3078 = devm_kzalloc(&client->dev, sizeof(*sd3078), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!sd3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	sd3078->regmap = devm_regmap_init_i2c(client, &regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (IS_ERR(sd3078->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(&client->dev, "regmap allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return PTR_ERR(sd3078->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	i2c_set_clientdata(client, sd3078);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	sd3078->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (IS_ERR(sd3078->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return PTR_ERR(sd3078->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	sd3078->rtc->ops = &sd3078_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	sd3078->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	sd3078->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ret = rtc_register_device(sd3078->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	sd3078_enable_reg_write(sd3078);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct i2c_device_id sd3078_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{"sd3078", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(i2c, sd3078_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct of_device_id rtc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	{ .compatible = "whwave,sd3078" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_DEVICE_TABLE(of, rtc_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct i2c_driver sd3078_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.driver     = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.name   = "sd3078",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.of_match_table = of_match_ptr(rtc_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.probe      = sd3078_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.id_table   = sd3078_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) module_i2c_driver(sd3078_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_AUTHOR("Dianlong Li <long17.cool@163.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_DESCRIPTION("SD3078 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_LICENSE("GPL v2");