^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPRD_RTC_SEC_CNT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_RTC_MIN_CNT_VALUE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPRD_RTC_HOUR_CNT_VALUE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_RTC_DAY_CNT_VALUE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRD_RTC_SEC_CNT_UPD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_RTC_MIN_CNT_UPD 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_RTC_HOUR_CNT_UPD 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_RTC_DAY_CNT_UPD 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_RTC_SEC_ALM_UPD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_RTC_MIN_ALM_UPD 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_RTC_HOUR_ALM_UPD 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_RTC_DAY_ALM_UPD 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPRD_RTC_INT_EN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_RTC_INT_RAW_STS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_RTC_INT_CLR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_RTC_INT_MASK_STS 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPRD_RTC_SEC_ALM_VALUE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPRD_RTC_MIN_ALM_VALUE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPRD_RTC_HOUR_ALM_VALUE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_RTC_DAY_ALM_VALUE 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPRD_RTC_SPG_VALUE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPRD_RTC_SPG_UPD 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_RTC_PWR_CTRL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_RTC_PWR_STS 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPRD_RTC_SEC_AUXALM_UPD 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_RTC_MIN_AUXALM_UPD 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPRD_RTC_HOUR_AUXALM_UPD 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPRD_RTC_DAY_AUXALM_UPD 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* BIT & MASK definition for SPRD_RTC_INT_* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_RTC_SEC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPRD_RTC_MIN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPRD_RTC_HOUR_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPRD_RTC_DAY_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_RTC_ALARM_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_RTC_HRS_FORMAT_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPRD_RTC_AUXALM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPRD_RTC_SPG_UPD_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPRD_RTC_SEC_UPD_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRD_RTC_MIN_UPD_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPRD_RTC_HOUR_UPD_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPRD_RTC_DAY_UPD_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRD_RTC_ALMSEC_UPD_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRD_RTC_ALMMIN_UPD_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPRD_RTC_ALMHOUR_UPD_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPRD_RTC_ALMDAY_UPD_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPRD_RTC_INT_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPRD_RTC_TIME_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (SPRD_RTC_SEC_UPD_EN | SPRD_RTC_MIN_UPD_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SPRD_RTC_HOUR_UPD_EN | SPRD_RTC_DAY_UPD_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPRD_RTC_ALMTIME_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (SPRD_RTC_ALMSEC_UPD_EN | SPRD_RTC_ALMMIN_UPD_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SPRD_RTC_ALMHOUR_UPD_EN | SPRD_RTC_ALMDAY_UPD_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPRD_RTC_ALM_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (SPRD_RTC_SEC_EN | SPRD_RTC_MIN_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SPRD_RTC_HOUR_EN | SPRD_RTC_DAY_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SPRD_RTC_ALARM_EN | SPRD_RTC_AUXALM_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* second/minute/hour/day values mask definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPRD_RTC_SEC_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPRD_RTC_MIN_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPRD_RTC_HOUR_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPRD_RTC_DAY_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* alarm lock definition for SPRD_RTC_SPG_UPD register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPRD_RTC_ALMLOCK_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPRD_RTC_ALM_UNLOCK 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPRD_RTC_ALM_LOCK (~SPRD_RTC_ALM_UNLOCK & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SPRD_RTC_ALMLOCK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* SPG values definition for SPRD_RTC_SPG_UPD register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPRD_RTC_POWEROFF_ALM_FLAG BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* power control/status definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPRD_RTC_POWER_RESET_VALUE 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPRD_RTC_POWER_STS_CLEAR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPRD_RTC_POWER_STS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPRD_RTC_POWER_STS_VALID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (~SPRD_RTC_POWER_RESET_VALUE << SPRD_RTC_POWER_STS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* timeout of synchronizing time and alarm registers (us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPRD_RTC_POLL_TIMEOUT 200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPRD_RTC_POLL_DELAY_US 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct sprd_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The Spreadtrum RTC controller has 3 groups registers, including time, normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * alarm and auxiliary alarm. The time group registers are used to set RTC time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * the normal alarm registers are used to set normal alarm, and the auxiliary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * alarm registers are used to set auxiliary alarm. Both alarm event and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * auxiliary alarm event can wake up system from deep sleep, but only alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * event can power up system from power down status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum sprd_rtc_reg_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SPRD_RTC_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SPRD_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SPRD_RTC_AUX_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int sprd_rtc_clear_alarm_ints(struct sprd_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SPRD_RTC_ALM_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int sprd_rtc_lock_alarm(struct sprd_rtc *rtc, bool lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val &= ~SPRD_RTC_ALMLOCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val |= SPRD_RTC_ALM_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val |= SPRD_RTC_ALM_UNLOCK | SPRD_RTC_POWEROFF_ALM_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_SPG_UPD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* wait until the SPG value is updated successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = regmap_read_poll_timeout(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) rtc->base + SPRD_RTC_INT_RAW_STS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (val & SPRD_RTC_SPG_UPD_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SPRD_RTC_POLL_DELAY_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SPRD_RTC_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(rtc->dev, "failed to update SPG value:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SPRD_RTC_SPG_UPD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int sprd_rtc_get_secs(struct sprd_rtc *rtc, enum sprd_rtc_reg_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) time64_t *secs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 sec_reg, min_reg, hour_reg, day_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 val, sec, min, hour, day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case SPRD_RTC_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sec_reg = SPRD_RTC_SEC_CNT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) min_reg = SPRD_RTC_MIN_CNT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) hour_reg = SPRD_RTC_HOUR_CNT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) day_reg = SPRD_RTC_DAY_CNT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case SPRD_RTC_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sec_reg = SPRD_RTC_SEC_ALM_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) min_reg = SPRD_RTC_MIN_ALM_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) hour_reg = SPRD_RTC_HOUR_ALM_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) day_reg = SPRD_RTC_DAY_ALM_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case SPRD_RTC_AUX_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sec_reg = SPRD_RTC_SEC_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) min_reg = SPRD_RTC_MIN_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) hour_reg = SPRD_RTC_HOUR_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) day_reg = SPRD_RTC_DAY_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = regmap_read(rtc->regmap, rtc->base + sec_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sec = val & SPRD_RTC_SEC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = regmap_read(rtc->regmap, rtc->base + min_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) min = val & SPRD_RTC_MIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = regmap_read(rtc->regmap, rtc->base + hour_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) hour = val & SPRD_RTC_HOUR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = regmap_read(rtc->regmap, rtc->base + day_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) day = val & SPRD_RTC_DAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *secs = (((time64_t)(day * 24) + hour) * 60 + min) * 60 + sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int sprd_rtc_set_secs(struct sprd_rtc *rtc, enum sprd_rtc_reg_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) time64_t secs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 sec_reg, min_reg, hour_reg, day_reg, sts_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 sec, min, hour, day, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret, rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* convert seconds to RTC time format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) day = div_s64_rem(secs, 86400, &rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hour = rem / 3600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rem -= hour * 3600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) min = rem / 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sec = rem - min * 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case SPRD_RTC_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sec_reg = SPRD_RTC_SEC_CNT_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) min_reg = SPRD_RTC_MIN_CNT_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) hour_reg = SPRD_RTC_HOUR_CNT_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) day_reg = SPRD_RTC_DAY_CNT_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sts_mask = SPRD_RTC_TIME_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case SPRD_RTC_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sec_reg = SPRD_RTC_SEC_ALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) min_reg = SPRD_RTC_MIN_ALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) hour_reg = SPRD_RTC_HOUR_ALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) day_reg = SPRD_RTC_DAY_ALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sts_mask = SPRD_RTC_ALMTIME_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SPRD_RTC_AUX_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sec_reg = SPRD_RTC_SEC_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) min_reg = SPRD_RTC_MIN_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) hour_reg = SPRD_RTC_HOUR_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) day_reg = SPRD_RTC_DAY_AUXALM_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sts_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = regmap_write(rtc->regmap, rtc->base + sec_reg, sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = regmap_write(rtc->regmap, rtc->base + min_reg, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = regmap_write(rtc->regmap, rtc->base + hour_reg, hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = regmap_write(rtc->regmap, rtc->base + day_reg, day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (type == SPRD_RTC_AUX_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Since the time and normal alarm registers are put in always-power-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * region supplied by VDDRTC, then these registers changing time will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * be very long, about 125ms. Thus here we should wait until all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * values are updated successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = regmap_read_poll_timeout(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rtc->base + SPRD_RTC_INT_RAW_STS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ((val & sts_mask) == sts_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SPRD_RTC_POLL_DELAY_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SPRD_RTC_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(rtc->dev, "set time/alarm values timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sts_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int sprd_rtc_read_aux_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) time64_t secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = sprd_rtc_get_secs(rtc, SPRD_RTC_AUX_ALARM, &secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rtc_time64_to_tm(secs, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) alrm->enabled = !!(val & SPRD_RTC_AUXALM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_RAW_STS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) alrm->pending = !!(val & SPRD_RTC_AUXALM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int sprd_rtc_set_aux_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) time64_t secs = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* clear the auxiliary alarm interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SPRD_RTC_AUXALM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = sprd_rtc_set_secs(rtc, SPRD_RTC_AUX_ALARM, secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SPRD_RTC_AUXALM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SPRD_RTC_AUXALM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SPRD_RTC_AUXALM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int sprd_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) time64_t secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!rtc->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_warn(dev, "RTC values are invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = sprd_rtc_get_secs(rtc, SPRD_RTC_TIME, &secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rtc_time64_to_tm(secs, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int sprd_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) time64_t secs = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = sprd_rtc_set_secs(rtc, SPRD_RTC_TIME, secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!rtc->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Clear RTC power status firstly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_PWR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SPRD_RTC_POWER_STS_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * Set RTC power status to indicate now RTC has valid time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_PWR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SPRD_RTC_POWER_STS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rtc->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int sprd_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) time64_t secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Before RTC device is registered, it will check to see if there is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * alarm already set in RTC hardware, and we always read the normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * alarm at this time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Or if aie_timer is enabled, we should get the normal alarm time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Otherwise we should get auxiliary alarm time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (rtc->rtc && rtc->rtc->registered && rtc->rtc->aie_timer.enabled == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return sprd_rtc_read_aux_alarm(dev, alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = sprd_rtc_get_secs(rtc, SPRD_RTC_ALARM, &secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rtc_time64_to_tm(secs, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) alrm->enabled = !!(val & SPRD_RTC_ALARM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_RAW_STS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) alrm->pending = !!(val & SPRD_RTC_ALARM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int sprd_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) time64_t secs = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct rtc_time aie_time =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rtc_ktime_to_tm(rtc->rtc->aie_timer.node.expires);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * We have 2 groups alarms: normal alarm and auxiliary alarm. Since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * both normal alarm event and auxiliary alarm event can wake up system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * from deep sleep, but only alarm event can power up system from power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * down status. Moreover we do not need to poll about 125ms when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * updating auxiliary alarm registers. Thus we usually set auxiliary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * alarm when wake up system from deep sleep, and for other scenarios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * we should set normal alarm with polling status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * So here we check if the alarm time is set by aie_timer, if yes, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * should set normal alarm, if not, we should set auxiliary alarm which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * means it is just a wake event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!rtc->rtc->aie_timer.enabled || rtc_tm_sub(&aie_time, &alrm->time))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return sprd_rtc_set_aux_alarm(dev, alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* clear the alarm interrupt status firstly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SPRD_RTC_ALARM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = sprd_rtc_set_secs(rtc, SPRD_RTC_ALARM, secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SPRD_RTC_ALARM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SPRD_RTC_ALARM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* unlock the alarm to enable the alarm function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = sprd_rtc_lock_alarm(rtc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SPRD_RTC_ALARM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Lock the alarm function in case fake alarm event will power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * up systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = sprd_rtc_lock_alarm(rtc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int sprd_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct sprd_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SPRD_RTC_ALARM_EN | SPRD_RTC_AUXALM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SPRD_RTC_ALARM_EN | SPRD_RTC_AUXALM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = sprd_rtc_lock_alarm(rtc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) regmap_update_bits(rtc->regmap, rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SPRD_RTC_ALARM_EN | SPRD_RTC_AUXALM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = sprd_rtc_lock_alarm(rtc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct rtc_class_ops sprd_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .read_time = sprd_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .set_time = sprd_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .read_alarm = sprd_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .set_alarm = sprd_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .alarm_irq_enable = sprd_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static irqreturn_t sprd_rtc_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct sprd_rtc *rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = sprd_rtc_clear_alarm_ints(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) rtc_update_irq(rtc->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int sprd_rtc_check_power_down(struct sprd_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_PWR_STS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * If the RTC power status value is SPRD_RTC_POWER_RESET_VALUE, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * means the RTC has been powered down, so the RTC time values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) rtc->valid = val == SPRD_RTC_POWER_RESET_VALUE ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int sprd_rtc_check_alarm_int(struct sprd_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * The SPRD_RTC_INT_EN register is not put in always-power-on region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * supplied by VDDRTC, so we should check if we need enable the alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * interrupt when system booting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * If we have set SPRD_RTC_POWEROFF_ALM_FLAG which is saved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * always-power-on region, that means we have set one alarm last time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * so we should enable the alarm interrupt to help RTC core to see if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * there is an alarm already set in RTC hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!(val & SPRD_RTC_POWEROFF_ALM_FLAG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return regmap_update_bits(rtc->regmap, rtc->base + SPRD_RTC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SPRD_RTC_ALARM_EN, SPRD_RTC_ALARM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int sprd_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct sprd_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!rtc->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = of_property_read_u32(node, "reg", &rtc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_err(&pdev->dev, "failed to get RTC base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (rtc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return rtc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (IS_ERR(rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rtc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* check if we need set the alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = sprd_rtc_check_alarm_int(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(&pdev->dev, "failed to check RTC alarm interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* check if RTC time values are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = sprd_rtc_check_power_down(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_err(&pdev->dev, "failed to check RTC time values\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) sprd_rtc_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) IRQF_ONESHOT | IRQF_EARLY_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pdev->name, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(&pdev->dev, "failed to request RTC irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) rtc->rtc->ops = &sprd_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) rtc->rtc->range_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rtc->rtc->range_max = 5662310399LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = rtc_register_device(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) device_init_wakeup(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const struct of_device_id sprd_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { .compatible = "sprd,sc2731-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MODULE_DEVICE_TABLE(of, sprd_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static struct platform_driver sprd_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = "sprd-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .of_match_table = sprd_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .probe = sprd_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) module_platform_driver(sprd_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MODULE_DESCRIPTION("Spreadtrum RTC Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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